Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	370169	1			T1	11		T2	16		T3	21
all_values[1]	370169	1			T1	11		T2	16		T3	21
all_values[2]	370169	1			T1	11		T2	16		T3	21
all_values[3]	370169	1			T1	11		T2	16		T3	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

737197

1

T1

23

T2

42

T3

46

auto[1]

743479

1

T1

21

T2

22

T3

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

884858

1

T1

25

T2

11

T3

44

auto[1]

595818

1

T1

19

T2

53

T3

40

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	105523	1			T1	4		T2	2		T3	4
all_values[0]	auto[0]	auto[1]	78823	1			T1	4		T2	9		T3	4
all_values[0]	auto[1]	auto[0]	106963	1			T1	2		T2	2		T3	7
all_values[0]	auto[1]	auto[1]	78860	1			T1	1		T2	3		T3	6
all_values[1]	auto[0]	auto[0]	110039	1			T1	4		T3	6		T4	115
all_values[1]	auto[0]	auto[1]	74225	1			T1	1		T2	8		T3	5
all_values[1]	auto[1]	auto[0]	111559	1			T1	3		T2	1		T3	5
all_values[1]	auto[1]	auto[1]	74346	1			T1	3		T2	7		T3	5
all_values[2]	auto[0]	auto[0]	112077	1			T1	1		T2	3		T3	8
all_values[2]	auto[0]	auto[1]	72134	1			T1	1		T2	8		T3	7
all_values[2]	auto[1]	auto[0]	113252	1			T1	5		T2	1		T3	3
all_values[2]	auto[1]	auto[1]	72706	1			T1	4		T2	4		T3	3
all_values[3]	auto[0]	auto[0]	111854	1			T1	4		T2	1		T3	6
all_values[3]	auto[0]	auto[1]	72522	1			T1	4		T2	11		T3	6
all_values[3]	auto[1]	auto[0]	113591	1			T1	2		T2	1		T3	5
all_values[3]	auto[1]	auto[1]	72202	1			T1	1		T2	3		T3	4