Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	370169	1			T1	11		T2	16		T3	21
all_pins[1]	370169	1			T1	11		T2	16		T3	21
all_pins[2]	370169	1			T1	11		T2	16		T3	21
all_pins[3]	370169	1			T1	11		T2	16		T3	21

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1182562	1			T1	35		T2	47		T3	66
values[0x1]	298114	1			T1	9		T2	17		T3	18
transitions[0x0=>0x1]	198790	1			T1	6		T2	14		T3	10
transitions[0x1=>0x0]	199040	1			T1	6		T2	14		T3	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	291309	1			T1	10		T2	13		T3	15
all_pins[0]	values[0x1]	78860	1			T1	1		T2	3		T3	6
all_pins[0]	transitions[0x0=>0x1]	78218	1			T1	1		T2	3		T3	5
all_pins[0]	transitions[0x1=>0x0]	71810	1			T1	1		T2	3		T3	4
all_pins[1]	values[0x0]	295823	1			T1	8		T2	9		T3	16
all_pins[1]	values[0x1]	74346	1			T1	3		T2	7		T3	5
all_pins[1]	transitions[0x0=>0x1]	40765	1			T1	3		T2	6		T3	1
all_pins[1]	transitions[0x1=>0x0]	45279	1			T1	1		T2	2		T3	2
all_pins[2]	values[0x0]	297463	1			T1	7		T2	12		T3	18
all_pins[2]	values[0x1]	72706	1			T1	4		T2	4		T3	3
all_pins[2]	transitions[0x0=>0x1]	39765	1			T1	2		T2	3		T3	1
all_pins[2]	transitions[0x1=>0x0]	41405	1			T1	1		T2	6		T3	3
all_pins[3]	values[0x0]	297967	1			T1	10		T2	13		T3	17
all_pins[3]	values[0x1]	72202	1			T1	1		T2	3		T3	4
all_pins[3]	transitions[0x0=>0x1]	40042	1			T2	2		T3	3		T4	15
all_pins[3]	transitions[0x1=>0x0]	40546	1			T1	3		T2	3		T3	2