Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T152	4		T153	7		T154	7
all_values[1]	284	1			T152	4		T153	7		T154	7
all_values[2]	284	1			T152	4		T153	7		T154	7
all_values[3]	284	1			T152	4		T153	7		T154	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603

1

T152

5

T153

10

T154

14

auto[1]

533

1

T152

11

T153

18

T154

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

468

1

T152

9

T153

13

T154

8

auto[1]

668

1

T152

7

T153

15

T154

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670

1

T152

10

T153

18

T154

12

auto[1]

466

1

T152

6

T153

10

T154

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

52

1

T152

1

T154

2

T222

1

all_values[0]

auto[0]

auto[0]

auto[1]

35

1

T338

2

T339

2

T340

1

all_values[0]

auto[0]

auto[1]

auto[0]

44

1

T152

3

T153

3

T154

1

all_values[0]

auto[0]

auto[1]

auto[1]

23

1

T153

1

T341

2

T342

1

all_values[0]

auto[1]

auto[0]

auto[1]

78

1

T153

2

T154

4

T222

1

all_values[0]

auto[1]

auto[1]

auto[1]

52

1

T153

1

T222

4

T338

3

all_values[1]

auto[0]

auto[0]

auto[0]

66

1

T152

1

T153

1

T339

1

all_values[1]

auto[0]

auto[0]

auto[1]

23

1

T222

1

T339

1

T341

1

all_values[1]

auto[0]

auto[1]

auto[0]

61

1

T153

2

T154

3

T222

2

all_values[1]

auto[0]

auto[1]

auto[1]

20

1

T153

1

T338

1

T343

2

all_values[1]

auto[1]

auto[0]

auto[1]

56

1

T152

1

T222

4

T338

1

all_values[1]

auto[1]

auto[1]

auto[1]

58

1

T152

2

T153

3

T154

4

all_values[2]

auto[0]

auto[0]

auto[0]

70

1

T152

2

T153

2

T222

2

all_values[2]

auto[0]

auto[0]

auto[1]

23

1

T153

2

T154

2

T222

1

all_values[2]

auto[0]

auto[1]

auto[0]

61

1

T154

1

T339

1

T340

1

all_values[2]

auto[0]

auto[1]

auto[1]

29

1

T153

1

T222

1

T338

2

all_values[2]

auto[1]

auto[0]

auto[1]

48

1

T153

2

T154

3

T222

1

all_values[2]

auto[1]

auto[1]

auto[1]

53

1

T152

2

T154

1

T222

2

all_values[3]

auto[0]

auto[0]

auto[0]

63

1

T153

1

T339

1

T344

2

all_values[3]

auto[0]

auto[0]

auto[1]

32

1

T154

2

T338

2

T339

1

all_values[3]

auto[0]

auto[1]

auto[0]

51

1

T152

2

T153

4

T154

1

all_values[3]

auto[0]

auto[1]

auto[1]

17

1

T152

1

T222

2

T338

1

all_values[3]

auto[1]

auto[0]

auto[1]

57

1

T154

1

T222

4

T339

1

all_values[3]

auto[1]

auto[1]

auto[1]

64

1

T152

1

T153

2

T154

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal