Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87443	1			T7	79		T23	29		T15	1403
accum_cnt_1000	251228	1			T4	57		T27	56		T5	690
accum_cnt_100	31534	1			T4	18		T27	15		T5	84
accum_cnt_50	75002	1			T2	12		T3	18		T4	41
accum_cnt_10	199968	1			T1	4		T2	50		T3	36
accum_cnt_0	405809	1			T1	16		T2	26		T3	26

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	272173	1			T1	5		T2	22		T3	20
class_index[0x1]	272173	1			T1	5		T2	22		T3	20
class_index[0x2]	272173	1			T1	5		T2	22		T3	20
class_index[0x3]	272173	1			T1	5		T2	22		T3	20

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24896	1			T15	524		T16	500		T18	475
class_index[0x0]	accum_cnt_1000	74026	1			T4	57		T5	690		T20	4
class_index[0x0]	accum_cnt_100	9611	1			T4	18		T5	84		T20	13
class_index[0x0]	accum_cnt_50	19743	1			T3	6		T4	23		T5	70
class_index[0x0]	accum_cnt_10	47581	1			T3	12		T4	25		T27	3
class_index[0x0]	accum_cnt_0	82749	1			T1	5		T2	22		T3	2
class_index[0x1]	accum_cnt_2000	21493	1			T16	480		T18	408		T19	654
class_index[0x1]	accum_cnt_1000	60812	1			T16	515		T17	374		T18	396
class_index[0x1]	accum_cnt_100	8019	1			T23	34		T16	37		T17	141
class_index[0x1]	accum_cnt_50	18089	1			T4	18		T28	9		T23	19
class_index[0x1]	accum_cnt_10	51006	1			T1	4		T2	22		T4	80
class_index[0x1]	accum_cnt_0	106367	1			T1	1		T3	20		T4	115
class_index[0x2]	accum_cnt_2000	18949	1			T7	79		T23	29		T15	634
class_index[0x2]	accum_cnt_1000	59276	1			T7	467		T23	148		T24	85
class_index[0x2]	accum_cnt_100	6841	1			T7	21		T23	40		T24	19
class_index[0x2]	accum_cnt_50	18820	1			T28	8		T7	21		T23	58
class_index[0x2]	accum_cnt_10	52756	1			T2	18		T3	17		T4	17
class_index[0x2]	accum_cnt_0	107462	1			T1	5		T2	4		T3	3
class_index[0x3]	accum_cnt_2000	22105	1			T15	245		T16	330		T110	36
class_index[0x3]	accum_cnt_1000	57114	1			T27	56		T23	37		T15	191
class_index[0x3]	accum_cnt_100	7063	1			T27	15		T23	2		T15	14
class_index[0x3]	accum_cnt_50	18350	1			T2	12		T3	12		T27	13
class_index[0x3]	accum_cnt_10	48625	1			T2	10		T3	7		T27	9
class_index[0x3]	accum_cnt_0	109231	1			T1	5		T3	1		T4	213