Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2798	1			T64	4		T72	1		T191	26
alert[0x1]	11206	1			T15	5		T67	819		T69	213
alert[0x2]	2264	1			T67	62		T39	614		T33	126
alert[0x3]	4130	1			T23	536		T67	81		T39	7
alert[0x4]	6259	1			T39	21		T33	2094		T38	6
alert[0x5]	9525	1			T2	1		T23	85		T69	357
alert[0x6]	3026	1			T2	7		T23	8		T33	174
alert[0x7]	3890	1			T23	9		T39	128		T38	1283
alert[0x8]	8212	1			T15	1		T8	1		T67	614
alert[0x9]	5330	1			T23	8		T8	1		T67	253
alert[0xa]	9979	1			T23	8		T69	32		T191	2
alert[0xb]	4353	1			T23	384		T67	38		T69	8
alert[0xc]	5141	1			T191	4		T282	5		T95	33
alert[0xd]	4666	1			T23	2		T67	287		T33	1102
alert[0xe]	3768	1			T33	9		T44	20		T10	923
alert[0xf]	1783	1			T23	15		T15	1		T8	1
alert[0x10]	4813	1			T15	3		T52	2		T67	33
alert[0x11]	15976	1			T23	195		T69	32		T33	85
alert[0x12]	5188	1			T23	377		T15	1		T67	135
alert[0x13]	3403	1			T67	11		T39	35		T38	23
alert[0x14]	2126	1			T15	1		T67	338		T69	380
alert[0x15]	4528	1			T67	47		T39	16		T69	259
alert[0x16]	10335	1			T67	541		T33	144		T103	5
alert[0x17]	2900	1			T23	4		T52	1		T72	6
alert[0x18]	4080	1			T8	1		T73	3		T33	69
alert[0x19]	5460	1			T23	5		T67	57		T33	71
alert[0x1a]	6306	1			T39	138		T69	188		T44	24
alert[0x1b]	3488	1			T2	5		T52	4		T67	74
alert[0x1c]	3068	1			T2	11		T23	154		T67	104
alert[0x1d]	3739	1			T39	4		T33	407		T44	187
alert[0x1e]	2719	1			T52	1		T39	85		T33	129
alert[0x1f]	3876	1			T67	22		T39	102		T69	872
alert[0x20]	2186	1			T64	1		T67	32		T69	11
alert[0x21]	2721	1			T23	1		T67	3		T39	324
alert[0x22]	4412	1			T5	1		T39	5		T69	135
alert[0x23]	4678	1			T23	129		T39	8		T69	4
alert[0x24]	5511	1			T23	1		T39	21		T69	30
alert[0x25]	7296	1			T2	3		T8	1		T64	1
alert[0x26]	1224	1			T23	17		T39	1		T73	1
alert[0x27]	5627	1			T23	18		T15	5		T8	2
alert[0x28]	8454	1			T23	16		T64	3		T39	23
alert[0x29]	7105	1			T67	289		T39	99		T69	51
alert[0x2a]	3742	1			T23	7		T8	1		T67	572
alert[0x2b]	4229	1			T23	2		T52	13		T39	59
alert[0x2c]	6609	1			T23	197		T64	3		T67	181
alert[0x2d]	10056	1			T8	1		T69	72		T33	242
alert[0x2e]	5643	1			T23	24		T8	1		T52	2
alert[0x2f]	2078	1			T67	142		T38	21		T44	347
alert[0x30]	5087	1			T2	28		T44	373		T9	1
alert[0x31]	7950	1			T23	386		T67	4		T39	8
alert[0x32]	6556	1			T2	2		T52	1		T67	52
alert[0x33]	6735	1			T23	1		T8	1		T52	44
alert[0x34]	8863	1			T33	201		T38	3191		T44	22
alert[0x35]	7338	1			T67	1844		T39	32		T69	15
alert[0x36]	9551	1			T8	1		T33	212		T44	7
alert[0x37]	12188	1			T23	96		T67	42		T69	4
alert[0x38]	5428	1			T8	1		T52	1		T67	34
alert[0x39]	5312	1			T67	4		T39	61		T69	273
alert[0x3a]	5035	1			T23	10		T8	2		T67	692
alert[0x3b]	4605	1			T23	9		T33	26		T38	1
alert[0x3c]	7397	1			T39	8		T69	21		T191	1
alert[0x3d]	8739	1			T23	22		T39	8		T69	1102
alert[0x3e]	1386	1			T23	2		T8	1		T67	23
alert[0x3f]	2894	1			T2	57		T23	1		T15	2
alert[0x40]	5891	1			T39	282		T69	8		T95	15

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	91461	1			T2	114		T23	521		T15	12
class_i[0x1]	96503	1			T23	1		T8	15		T52	28
class_i[0x2]	106517	1			T23	1709		T52	30		T225	5
class_i[0x3]	66380	1			T5	1		T23	498		T15	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

360216

1

T2

114

T23

2729

T15

19

alert_ping_fail

645

1

T5

1

T8

16

T9

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2791	1			T64	4		T72	1		T191	26
alert_integrity_fail	alert[0x1]	11197	1			T15	5		T67	819		T69	213
alert_integrity_fail	alert[0x2]	2251	1			T67	62		T39	614		T33	126
alert_integrity_fail	alert[0x3]	4120	1			T23	536		T67	81		T39	7
alert_integrity_fail	alert[0x4]	6251	1			T39	21		T33	2094		T38	6
alert_integrity_fail	alert[0x5]	9508	1			T2	1		T23	85		T69	357
alert_integrity_fail	alert[0x6]	3012	1			T2	7		T23	8		T33	174
alert_integrity_fail	alert[0x7]	3876	1			T23	9		T39	128		T38	1283
alert_integrity_fail	alert[0x8]	8196	1			T15	1		T67	614		T39	1
alert_integrity_fail	alert[0x9]	5317	1			T23	8		T67	253		T33	187
alert_integrity_fail	alert[0xa]	9968	1			T23	8		T69	32		T191	2
alert_integrity_fail	alert[0xb]	4345	1			T23	384		T67	38		T69	8
alert_integrity_fail	alert[0xc]	5129	1			T191	4		T282	5		T95	33
alert_integrity_fail	alert[0xd]	4657	1			T23	2		T67	287		T33	1102
alert_integrity_fail	alert[0xe]	3763	1			T33	9		T44	20		T10	923
alert_integrity_fail	alert[0xf]	1774	1			T23	15		T15	1		T67	39
alert_integrity_fail	alert[0x10]	4803	1			T15	3		T52	2		T67	33
alert_integrity_fail	alert[0x11]	15968	1			T23	195		T69	32		T33	85
alert_integrity_fail	alert[0x12]	5177	1			T23	377		T15	1		T67	135
alert_integrity_fail	alert[0x13]	3396	1			T67	11		T39	35		T38	23
alert_integrity_fail	alert[0x14]	2122	1			T15	1		T67	338		T69	380
alert_integrity_fail	alert[0x15]	4522	1			T67	47		T39	16		T69	259
alert_integrity_fail	alert[0x16]	10322	1			T67	541		T33	144		T103	5
alert_integrity_fail	alert[0x17]	2891	1			T23	4		T52	1		T72	6
alert_integrity_fail	alert[0x18]	4070	1			T73	3		T33	69		T38	6
alert_integrity_fail	alert[0x19]	5454	1			T23	5		T67	57		T33	71
alert_integrity_fail	alert[0x1a]	6303	1			T39	138		T69	188		T44	24
alert_integrity_fail	alert[0x1b]	3480	1			T2	5		T52	4		T67	74
alert_integrity_fail	alert[0x1c]	3058	1			T2	11		T23	154		T67	104
alert_integrity_fail	alert[0x1d]	3728	1			T39	4		T33	407		T44	187
alert_integrity_fail	alert[0x1e]	2709	1			T52	1		T39	85		T33	129
alert_integrity_fail	alert[0x1f]	3865	1			T67	22		T39	102		T69	872
alert_integrity_fail	alert[0x20]	2170	1			T64	1		T67	32		T69	11
alert_integrity_fail	alert[0x21]	2707	1			T23	1		T67	3		T39	324
alert_integrity_fail	alert[0x22]	4400	1			T39	5		T69	135		T191	48
alert_integrity_fail	alert[0x23]	4667	1			T23	129		T39	8		T69	4
alert_integrity_fail	alert[0x24]	5504	1			T23	1		T39	21		T69	30
alert_integrity_fail	alert[0x25]	7286	1			T2	3		T64	1		T33	4629
alert_integrity_fail	alert[0x26]	1214	1			T23	17		T39	1		T73	1
alert_integrity_fail	alert[0x27]	5622	1			T23	18		T15	5		T67	23
alert_integrity_fail	alert[0x28]	8440	1			T23	16		T64	3		T39	23
alert_integrity_fail	alert[0x29]	7097	1			T67	289		T39	99		T69	51
alert_integrity_fail	alert[0x2a]	3732	1			T23	7		T67	572		T39	6
alert_integrity_fail	alert[0x2b]	4215	1			T23	2		T52	13		T39	59
alert_integrity_fail	alert[0x2c]	6599	1			T23	197		T64	3		T67	181
alert_integrity_fail	alert[0x2d]	10046	1			T69	72		T33	242		T38	25
alert_integrity_fail	alert[0x2e]	5630	1			T23	24		T52	2		T67	27
alert_integrity_fail	alert[0x2f]	2066	1			T67	142		T38	21		T44	347
alert_integrity_fail	alert[0x30]	5074	1			T2	28		T44	373		T172	9
alert_integrity_fail	alert[0x31]	7939	1			T23	386		T67	4		T39	8
alert_integrity_fail	alert[0x32]	6549	1			T2	2		T52	1		T67	52
alert_integrity_fail	alert[0x33]	6724	1			T23	1		T52	44		T69	65
alert_integrity_fail	alert[0x34]	8850	1			T33	201		T38	3191		T44	22
alert_integrity_fail	alert[0x35]	7329	1			T67	1844		T39	32		T69	15
alert_integrity_fail	alert[0x36]	9538	1			T33	212		T44	7		T10	1334
alert_integrity_fail	alert[0x37]	12184	1			T23	96		T67	42		T69	4
alert_integrity_fail	alert[0x38]	5416	1			T52	1		T67	34		T39	8
alert_integrity_fail	alert[0x39]	5303	1			T67	4		T39	61		T69	273
alert_integrity_fail	alert[0x3a]	5019	1			T23	10		T67	692		T39	22
alert_integrity_fail	alert[0x3b]	4597	1			T23	9		T33	26		T38	1
alert_integrity_fail	alert[0x3c]	7388	1			T39	8		T69	21		T191	1
alert_integrity_fail	alert[0x3d]	8733	1			T23	22		T39	8		T69	1102
alert_integrity_fail	alert[0x3e]	1375	1			T23	2		T67	23		T39	8
alert_integrity_fail	alert[0x3f]	2890	1			T2	57		T23	1		T15	2
alert_integrity_fail	alert[0x40]	5890	1			T39	282		T69	8		T95	15
alert_ping_fail	alert[0x0]	7	1			T283	1		T284	1		T285	2
alert_ping_fail	alert[0x1]	9	1			T286	1		T287	2		T288	1
alert_ping_fail	alert[0x2]	13	1			T289	1		T290	1		T291	2
alert_ping_fail	alert[0x3]	10	1			T290	2		T292	1		T284	1
alert_ping_fail	alert[0x4]	8	1			T287	1		T293	1		T294	1
alert_ping_fail	alert[0x5]	17	1			T279	1		T295	1		T84	1
alert_ping_fail	alert[0x6]	14	1			T296	2		T175	1		T292	1
alert_ping_fail	alert[0x7]	14	1			T175	1		T292	1		T297	1
alert_ping_fail	alert[0x8]	16	1			T8	1		T290	2		T292	1
alert_ping_fail	alert[0x9]	13	1			T8	1		T295	1		T290	1
alert_ping_fail	alert[0xa]	11	1			T9	1		T85	1		T287	1
alert_ping_fail	alert[0xb]	8	1			T85	1		T286	1		T84	1
alert_ping_fail	alert[0xc]	12	1			T84	1		T290	1		T292	1
alert_ping_fail	alert[0xd]	9	1			T84	1		T290	1		T287	1
alert_ping_fail	alert[0xe]	5	1			T297	1		T284	1		T298	1
alert_ping_fail	alert[0xf]	9	1			T8	1		T295	1		T299	1
alert_ping_fail	alert[0x10]	10	1			T295	1		T286	1		T300	1
alert_ping_fail	alert[0x11]	8	1			T288	1		T301	1		T302	1
alert_ping_fail	alert[0x12]	11	1			T296	1		T303	2		T288	1
alert_ping_fail	alert[0x13]	7	1			T287	1		T284	1		T304	1
alert_ping_fail	alert[0x14]	4	1			T305	1		T297	1		T306	1
alert_ping_fail	alert[0x15]	6	1			T296	1		T284	1		T218	1
alert_ping_fail	alert[0x16]	13	1			T307	2		T293	2		T308	1
alert_ping_fail	alert[0x17]	9	1			T309	1		T285	1		T310	1
alert_ping_fail	alert[0x18]	10	1			T8	1		T84	1		T290	2
alert_ping_fail	alert[0x19]	6	1			T286	2		T289	2		T291	1
alert_ping_fail	alert[0x1a]	3	1			T287	1		T297	1		T311	1
alert_ping_fail	alert[0x1b]	8	1			T287	1		T297	2		T293	1
alert_ping_fail	alert[0x1c]	10	1			T286	1		T305	1		T292	1
alert_ping_fail	alert[0x1d]	11	1			T280	1		T296	1		T84	2
alert_ping_fail	alert[0x1e]	10	1			T283	2		T284	1		T303	1
alert_ping_fail	alert[0x1f]	11	1			T286	1		T287	1		T283	2
alert_ping_fail	alert[0x20]	16	1			T286	2		T312	1		T300	1
alert_ping_fail	alert[0x21]	14	1			T292	1		T297	1		T284	1
alert_ping_fail	alert[0x22]	12	1			T5	1		T85	1		T289	1
alert_ping_fail	alert[0x23]	11	1			T84	1		T297	1		T283	1
alert_ping_fail	alert[0x24]	7	1			T286	1		T289	1		T293	1
alert_ping_fail	alert[0x25]	10	1			T8	1		T288	1		T313	1
alert_ping_fail	alert[0x26]	10	1			T290	1		T291	1		T299	1
alert_ping_fail	alert[0x27]	5	1			T8	2		T313	1		T314	2
alert_ping_fail	alert[0x28]	14	1			T280	1		T295	1		T315	1
alert_ping_fail	alert[0x29]	8	1			T290	2		T285	1		T316	1
alert_ping_fail	alert[0x2a]	10	1			T8	1		T9	1		T213	1
alert_ping_fail	alert[0x2b]	14	1			T9	1		T287	1		T293	1
alert_ping_fail	alert[0x2c]	10	1			T295	1		T287	1		T299	1
alert_ping_fail	alert[0x2d]	10	1			T8	1		T9	1		T312	1
alert_ping_fail	alert[0x2e]	13	1			T8	1		T281	1		T312	1
alert_ping_fail	alert[0x2f]	12	1			T286	1		T84	1		T300	1
alert_ping_fail	alert[0x30]	13	1			T9	1		T296	1		T278	1
alert_ping_fail	alert[0x31]	11	1			T287	1		T291	1		T293	1
alert_ping_fail	alert[0x32]	7	1			T9	1		T290	2		T313	1
alert_ping_fail	alert[0x33]	11	1			T8	1		T9	1		T291	1
alert_ping_fail	alert[0x34]	13	1			T296	1		T286	1		T284	1
alert_ping_fail	alert[0x35]	9	1			T9	2		T286	1		T293	1
alert_ping_fail	alert[0x36]	13	1			T8	1		T9	1		T283	1
alert_ping_fail	alert[0x37]	4	1			T300	1		T292	1		T317	1
alert_ping_fail	alert[0x38]	12	1			T8	1		T9	1		T84	1
alert_ping_fail	alert[0x39]	9	1			T287	1		T297	1		T284	1
alert_ping_fail	alert[0x3a]	16	1			T8	2		T290	2		T292	1
alert_ping_fail	alert[0x3b]	8	1			T283	1		T294	1		T317	2
alert_ping_fail	alert[0x3c]	9	1			T296	1		T283	1		T293	1
alert_ping_fail	alert[0x3d]	6	1			T84	1		T299	1		T318	1
alert_ping_fail	alert[0x3e]	11	1			T8	1		T295	1		T296	1
alert_ping_fail	alert[0x3f]	4	1			T9	2		T318	1		T319	1
alert_ping_fail	alert[0x40]	1	1			T319	1		-	-		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	91295	1			T2	114		T23	521		T15	12
alert_integrity_fail	class_i[0x1]	96343	1			T23	1		T52	28		T67	7519
alert_integrity_fail	class_i[0x2]	106414	1			T23	1709		T52	30		T225	5
alert_integrity_fail	class_i[0x3]	66164	1			T23	498		T15	7		T64	14
alert_ping_fail	class_i[0x0]	166	1			T9	2		T295	3		T286	3
alert_ping_fail	class_i[0x1]	160	1			T8	15		T9	1		T213	1
alert_ping_fail	class_i[0x2]	103	1			T9	10		T85	3		T296	2
alert_ping_fail	class_i[0x3]	216	1			T5	1		T8	1		T280	2