Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.69 100.00 100.00 100.00 99.38 99.60


Total test records in report: 834
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T767 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4057907227 Jun 30 05:33:45 PM PDT 24 Jun 30 05:33:48 PM PDT 24 41769640 ps
T768 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3053593583 Jun 30 05:34:08 PM PDT 24 Jun 30 05:34:10 PM PDT 24 10687093 ps
T166 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1730868735 Jun 30 05:33:40 PM PDT 24 Jun 30 05:34:26 PM PDT 24 1206735428 ps
T769 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4017000021 Jun 30 05:33:37 PM PDT 24 Jun 30 05:33:46 PM PDT 24 332026382 ps
T770 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1934938340 Jun 30 05:34:07 PM PDT 24 Jun 30 05:34:09 PM PDT 24 8593792 ps
T771 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1498069795 Jun 30 05:34:00 PM PDT 24 Jun 30 05:34:08 PM PDT 24 373736569 ps
T156 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.548988850 Jun 30 05:33:43 PM PDT 24 Jun 30 05:34:28 PM PDT 24 3617115489 ps
T772 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4055840521 Jun 30 05:33:33 PM PDT 24 Jun 30 05:33:44 PM PDT 24 55073230 ps
T773 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1729407614 Jun 30 05:34:14 PM PDT 24 Jun 30 05:34:16 PM PDT 24 17538416 ps
T774 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.809057091 Jun 30 05:34:04 PM PDT 24 Jun 30 05:34:32 PM PDT 24 350517471 ps
T775 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2314942080 Jun 30 05:33:39 PM PDT 24 Jun 30 05:33:50 PM PDT 24 1296255621 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2979471598 Jun 30 05:33:25 PM PDT 24 Jun 30 05:33:42 PM PDT 24 853488664 ps
T777 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.471222100 Jun 30 05:33:24 PM PDT 24 Jun 30 05:33:35 PM PDT 24 133427840 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1175675957 Jun 30 05:33:20 PM PDT 24 Jun 30 05:33:31 PM PDT 24 60994836 ps
T161 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3075898932 Jun 30 05:33:54 PM PDT 24 Jun 30 05:34:32 PM PDT 24 1076811442 ps
T779 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.633340314 Jun 30 05:33:59 PM PDT 24 Jun 30 05:34:07 PM PDT 24 84191405 ps
T780 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4145027473 Jun 30 05:33:42 PM PDT 24 Jun 30 05:33:44 PM PDT 24 7538579 ps
T781 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1288983605 Jun 30 05:33:26 PM PDT 24 Jun 30 05:34:59 PM PDT 24 3406049705 ps
T782 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.807718010 Jun 30 05:34:09 PM PDT 24 Jun 30 05:34:11 PM PDT 24 11991690 ps
T158 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2650678594 Jun 30 05:33:39 PM PDT 24 Jun 30 05:33:42 PM PDT 24 168367029 ps
T783 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2222680641 Jun 30 05:34:09 PM PDT 24 Jun 30 05:34:11 PM PDT 24 9113854 ps
T784 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3946434485 Jun 30 05:33:26 PM PDT 24 Jun 30 05:33:32 PM PDT 24 306487091 ps
T785 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.122580961 Jun 30 05:33:45 PM PDT 24 Jun 30 05:33:51 PM PDT 24 51316522 ps
T155 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3528728681 Jun 30 05:33:39 PM PDT 24 Jun 30 05:33:43 PM PDT 24 30225080 ps
T786 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1422838049 Jun 30 05:33:46 PM PDT 24 Jun 30 05:34:12 PM PDT 24 349910777 ps
T787 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.706777015 Jun 30 05:33:29 PM PDT 24 Jun 30 05:33:31 PM PDT 24 16617008 ps
T788 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.643196327 Jun 30 05:33:39 PM PDT 24 Jun 30 05:34:04 PM PDT 24 348507758 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1130936061 Jun 30 05:33:24 PM PDT 24 Jun 30 05:34:12 PM PDT 24 1447904560 ps
T790 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3364137716 Jun 30 05:33:47 PM PDT 24 Jun 30 05:33:59 PM PDT 24 319691324 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2162773530 Jun 30 05:33:24 PM PDT 24 Jun 30 05:37:44 PM PDT 24 6449891705 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2569395132 Jun 30 05:33:29 PM PDT 24 Jun 30 05:39:00 PM PDT 24 17818301752 ps
T133 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2151327700 Jun 30 05:33:30 PM PDT 24 Jun 30 05:36:32 PM PDT 24 2718562234 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1078044220 Jun 30 05:33:25 PM PDT 24 Jun 30 05:33:43 PM PDT 24 481267752 ps
T794 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4203858330 Jun 30 05:33:54 PM PDT 24 Jun 30 05:34:21 PM PDT 24 421390449 ps
T795 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2464091842 Jun 30 05:34:08 PM PDT 24 Jun 30 05:34:13 PM PDT 24 19277667 ps
T163 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3078424702 Jun 30 05:33:47 PM PDT 24 Jun 30 05:33:52 PM PDT 24 63208091 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3008046337 Jun 30 05:33:23 PM PDT 24 Jun 30 05:36:16 PM PDT 24 7055223227 ps
T797 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.669058112 Jun 30 05:33:40 PM PDT 24 Jun 30 05:34:02 PM PDT 24 335754927 ps
T798 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1244960658 Jun 30 05:33:53 PM PDT 24 Jun 30 05:34:34 PM PDT 24 966848572 ps
T799 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3323785715 Jun 30 05:33:39 PM PDT 24 Jun 30 05:34:05 PM PDT 24 162334866 ps
T346 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4100908716 Jun 30 05:33:53 PM PDT 24 Jun 30 05:54:41 PM PDT 24 61250948276 ps
T800 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.101986732 Jun 30 05:33:33 PM PDT 24 Jun 30 05:34:00 PM PDT 24 362531455 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2260338792 Jun 30 05:33:19 PM PDT 24 Jun 30 05:37:34 PM PDT 24 4450855888 ps
T802 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2709410014 Jun 30 05:34:06 PM PDT 24 Jun 30 05:34:08 PM PDT 24 20705269 ps
T803 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2883555741 Jun 30 05:33:46 PM PDT 24 Jun 30 05:33:52 PM PDT 24 124293384 ps
T144 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2988853028 Jun 30 05:33:24 PM PDT 24 Jun 30 05:45:05 PM PDT 24 4966919086 ps
T804 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4288075414 Jun 30 05:34:07 PM PDT 24 Jun 30 05:34:08 PM PDT 24 8382230 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.338904932 Jun 30 05:33:53 PM PDT 24 Jun 30 05:34:01 PM PDT 24 338755776 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2011317988 Jun 30 05:33:23 PM PDT 24 Jun 30 05:33:32 PM PDT 24 246242022 ps
T807 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4184222056 Jun 30 05:34:10 PM PDT 24 Jun 30 05:34:12 PM PDT 24 6790192 ps
T808 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.711699795 Jun 30 05:33:54 PM PDT 24 Jun 30 05:33:59 PM PDT 24 169718579 ps
T116 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2540379265 Jun 30 05:33:25 PM PDT 24 Jun 30 05:37:28 PM PDT 24 6762925357 ps
T809 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.914494411 Jun 30 05:34:08 PM PDT 24 Jun 30 05:34:10 PM PDT 24 10914269 ps
T810 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3594636165 Jun 30 05:33:52 PM PDT 24 Jun 30 05:33:57 PM PDT 24 72525569 ps
T137 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3525718340 Jun 30 05:33:53 PM PDT 24 Jun 30 05:43:44 PM PDT 24 33215091033 ps
T811 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4219570809 Jun 30 05:33:29 PM PDT 24 Jun 30 05:34:13 PM PDT 24 2985627838 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1768466980 Jun 30 05:33:17 PM PDT 24 Jun 30 05:33:29 PM PDT 24 130426060 ps
T813 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3226518398 Jun 30 05:33:45 PM PDT 24 Jun 30 05:33:57 PM PDT 24 713636931 ps
T814 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.900259871 Jun 30 05:33:36 PM PDT 24 Jun 30 05:33:43 PM PDT 24 150432977 ps
T815 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3276504481 Jun 30 05:33:17 PM PDT 24 Jun 30 05:33:26 PM PDT 24 137417364 ps
T816 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1144541856 Jun 30 05:33:30 PM PDT 24 Jun 30 05:33:43 PM PDT 24 318591706 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.80871593 Jun 30 05:33:47 PM PDT 24 Jun 30 05:34:27 PM PDT 24 517147950 ps
T143 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1615267477 Jun 30 05:33:59 PM PDT 24 Jun 30 05:36:32 PM PDT 24 2247750186 ps
T818 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.359086130 Jun 30 05:33:46 PM PDT 24 Jun 30 05:33:52 PM PDT 24 214856490 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3165943891 Jun 30 05:33:45 PM PDT 24 Jun 30 05:34:01 PM PDT 24 342720029 ps
T820 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3852774519 Jun 30 05:33:54 PM PDT 24 Jun 30 05:34:34 PM PDT 24 4504340270 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2818013712 Jun 30 05:33:44 PM PDT 24 Jun 30 05:33:46 PM PDT 24 10665192 ps
T140 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1713680489 Jun 30 05:33:59 PM PDT 24 Jun 30 05:40:11 PM PDT 24 9583149272 ps
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2696086970 Jun 30 05:33:38 PM PDT 24 Jun 30 05:40:39 PM PDT 24 2285356519 ps
T135 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1502263537 Jun 30 05:33:46 PM PDT 24 Jun 30 05:49:14 PM PDT 24 23653002848 ps
T822 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.10743008 Jun 30 05:34:01 PM PDT 24 Jun 30 05:34:03 PM PDT 24 12443052 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4147686698 Jun 30 05:33:17 PM PDT 24 Jun 30 05:33:20 PM PDT 24 11179171 ps
T824 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.304160278 Jun 30 05:33:38 PM PDT 24 Jun 30 05:33:40 PM PDT 24 8447100 ps
T825 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.801211894 Jun 30 05:33:53 PM PDT 24 Jun 30 05:33:56 PM PDT 24 17024974 ps
T826 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2163987394 Jun 30 05:34:07 PM PDT 24 Jun 30 05:34:10 PM PDT 24 51282234 ps
T827 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1141473816 Jun 30 05:34:10 PM PDT 24 Jun 30 05:34:12 PM PDT 24 9124047 ps
T828 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2397954364 Jun 30 05:33:53 PM PDT 24 Jun 30 05:33:58 PM PDT 24 119022292 ps
T829 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.260995586 Jun 30 05:33:41 PM PDT 24 Jun 30 05:33:49 PM PDT 24 47854252 ps
T830 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3664440996 Jun 30 05:33:23 PM PDT 24 Jun 30 05:33:25 PM PDT 24 8095831 ps
T831 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.18484471 Jun 30 05:33:24 PM PDT 24 Jun 30 05:35:12 PM PDT 24 4085502100 ps
T832 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3847801343 Jun 30 05:34:10 PM PDT 24 Jun 30 05:34:49 PM PDT 24 705487519 ps
T833 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1068484274 Jun 30 05:33:25 PM PDT 24 Jun 30 05:33:32 PM PDT 24 39757258 ps
T148 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4120541079 Jun 30 05:33:49 PM PDT 24 Jun 30 05:42:25 PM PDT 24 6107497077 ps
T834 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.111387549 Jun 30 05:33:45 PM PDT 24 Jun 30 05:36:58 PM PDT 24 8300176984 ps

Test location /workspace/coverage/default/0.alert_handler_stress_all.3859853451
Short name T4
Test name
Test status
Simulation time 40229803819 ps
CPU time 404.71 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:25:52 PM PDT 24
Peak memory 257132 kb
Host smart-c2317ad9-488a-43fb-9bbe-4e7a9d0ab85b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859853451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3859853451
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3389050508
Short name T23
Test name
Test status
Simulation time 444182283192 ps
CPU time 5051.51 seconds
Started Jun 30 05:21:32 PM PDT 24
Finished Jun 30 06:45:45 PM PDT 24
Peak memory 290488 kb
Host smart-37eea56a-c7fa-46cb-b8e3-6599a2c72510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389050508 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3389050508
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3252700845
Short name T6
Test name
Test status
Simulation time 1033414909 ps
CPU time 43.61 seconds
Started Jun 30 05:19:35 PM PDT 24
Finished Jun 30 05:20:19 PM PDT 24
Peak memory 249216 kb
Host smart-8402b1bc-df85-4f89-a5fe-8cbdda792c9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3252700845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3252700845
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1641005105
Short name T12
Test name
Test status
Simulation time 433544899 ps
CPU time 22.9 seconds
Started Jun 30 05:19:07 PM PDT 24
Finished Jun 30 05:19:34 PM PDT 24
Peak memory 267496 kb
Host smart-7b01d087-63ba-4d32-80ae-987c71c0271e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1641005105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1641005105
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.138765170
Short name T150
Test name
Test status
Simulation time 915219548 ps
CPU time 77.72 seconds
Started Jun 30 05:33:55 PM PDT 24
Finished Jun 30 05:35:13 PM PDT 24
Peak memory 246036 kb
Host smart-a4fdeb64-5b88-4e70-86e3-ab96105ccd89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=138765170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.138765170
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1011831704
Short name T33
Test name
Test status
Simulation time 13486780313 ps
CPU time 1491.96 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:45:15 PM PDT 24
Peak memory 290272 kb
Host smart-3c24fc3f-fd88-40be-b23f-93460e2669e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011831704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1011831704
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.247329113
Short name T429
Test name
Test status
Simulation time 43506466933 ps
CPU time 4185.26 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 06:28:52 PM PDT 24
Peak memory 338892 kb
Host smart-95496317-a621-44a6-8aad-65505a3c5e73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247329113 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.247329113
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3456144358
Short name T118
Test name
Test status
Simulation time 1566222165 ps
CPU time 234.99 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:37:13 PM PDT 24
Peak memory 265360 kb
Host smart-51e7696f-38de-49f4-b72c-97cdf77bcdf4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3456144358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3456144358
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1983641457
Short name T96
Test name
Test status
Simulation time 112304157914 ps
CPU time 1834.76 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:50:12 PM PDT 24
Peak memory 290384 kb
Host smart-97491a2b-bb76-4af7-b8fd-44e475597393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983641457 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1983641457
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3436748192
Short name T39
Test name
Test status
Simulation time 96246588867 ps
CPU time 1423.05 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:42:50 PM PDT 24
Peak memory 304208 kb
Host smart-7f224360-760f-46c1-a761-da5dbf83fbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436748192 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3436748192
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1782153573
Short name T213
Test name
Test status
Simulation time 123443889066 ps
CPU time 3273.21 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 06:14:56 PM PDT 24
Peak memory 289688 kb
Host smart-8fdb9c5f-01cb-4f82-8fed-d9caa99af4bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782153573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1782153573
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1738593500
Short name T83
Test name
Test status
Simulation time 229116938615 ps
CPU time 3074.94 seconds
Started Jun 30 05:18:57 PM PDT 24
Finished Jun 30 06:10:13 PM PDT 24
Peak memory 315036 kb
Host smart-3ae9d789-d0c9-47a6-968b-45cb2e1dced0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738593500 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1738593500
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2918808952
Short name T111
Test name
Test status
Simulation time 12430193125 ps
CPU time 1145.63 seconds
Started Jun 30 05:33:31 PM PDT 24
Finished Jun 30 05:52:37 PM PDT 24
Peak memory 265500 kb
Host smart-79a3ac00-66fe-47db-8a3b-ebd88f33cec3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918808952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2918808952
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2824322025
Short name T172
Test name
Test status
Simulation time 143811792869 ps
CPU time 5258.98 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 06:47:27 PM PDT 24
Peak memory 320056 kb
Host smart-c5db4a2a-59d7-4d73-bace-d69bf8eae9fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824322025 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2824322025
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.466411028
Short name T114
Test name
Test status
Simulation time 7414697000 ps
CPU time 305.85 seconds
Started Jun 30 05:33:31 PM PDT 24
Finished Jun 30 05:38:37 PM PDT 24
Peak memory 265464 kb
Host smart-82bf1821-da2e-4bac-b6b8-4bdca98205bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=466411028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.466411028
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4241354625
Short name T272
Test name
Test status
Simulation time 39584806737 ps
CPU time 1201.62 seconds
Started Jun 30 05:20:28 PM PDT 24
Finished Jun 30 05:40:31 PM PDT 24
Peak memory 265732 kb
Host smart-402af9f3-a38e-4328-bf37-aed54426761d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241354625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4241354625
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.983036298
Short name T26
Test name
Test status
Simulation time 58007392038 ps
CPU time 1554.38 seconds
Started Jun 30 05:20:32 PM PDT 24
Finished Jun 30 05:46:27 PM PDT 24
Peak memory 290236 kb
Host smart-c3264c5b-6144-4650-98d2-42ad0bb0028b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983036298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.983036298
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1662873225
Short name T124
Test name
Test status
Simulation time 19157417849 ps
CPU time 1083.65 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:51:22 PM PDT 24
Peak memory 273536 kb
Host smart-2aea0bc0-8d9e-441c-8404-988053669b61
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662873225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1662873225
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.632802386
Short name T67
Test name
Test status
Simulation time 59517985290 ps
CPU time 3408.08 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 06:16:27 PM PDT 24
Peak memory 301856 kb
Host smart-81a151ea-530b-4103-9dc7-a24ab6a90021
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632802386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.632802386
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3228096410
Short name T339
Test name
Test status
Simulation time 10846883 ps
CPU time 1.37 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:09 PM PDT 24
Peak memory 237616 kb
Host smart-13a2c98c-df92-4577-9eff-5e45720aed89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3228096410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3228096410
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1180505110
Short name T142
Test name
Test status
Simulation time 23049336390 ps
CPU time 1227.46 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:53:54 PM PDT 24
Peak memory 265640 kb
Host smart-c10d1b07-c27f-421f-a308-0b58bb180ab8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180505110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1180505110
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1804523170
Short name T287
Test name
Test status
Simulation time 13085224211 ps
CPU time 528.61 seconds
Started Jun 30 05:20:05 PM PDT 24
Finished Jun 30 05:28:54 PM PDT 24
Peak memory 249304 kb
Host smart-c1bf9f11-453b-4b6a-8fc3-b9550011a05d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804523170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1804523170
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.4047451690
Short name T305
Test name
Test status
Simulation time 62893645821 ps
CPU time 1954.79 seconds
Started Jun 30 05:19:27 PM PDT 24
Finished Jun 30 05:52:02 PM PDT 24
Peak memory 289156 kb
Host smart-aaac220d-e0eb-4f60-b84e-cf265ffc4f92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047451690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4047451690
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1948822649
Short name T115
Test name
Test status
Simulation time 3139864440 ps
CPU time 173.51 seconds
Started Jun 30 05:33:38 PM PDT 24
Finished Jun 30 05:36:32 PM PDT 24
Peak memory 265616 kb
Host smart-b7f13a41-af64-41ec-8f9b-9eb7c3d55417
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1948822649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1948822649
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1217781431
Short name T284
Test name
Test status
Simulation time 22482632837 ps
CPU time 469.32 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:29:30 PM PDT 24
Peak memory 248364 kb
Host smart-6a06870c-8ef7-4736-93fb-bb736d7c9213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217781431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1217781431
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4250070518
Short name T328
Test name
Test status
Simulation time 117461807044 ps
CPU time 2695.74 seconds
Started Jun 30 05:19:19 PM PDT 24
Finished Jun 30 06:04:15 PM PDT 24
Peak memory 282080 kb
Host smart-a6b6028e-89af-4db9-b00a-e33af0645e2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250070518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4250070518
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1961456862
Short name T117
Test name
Test status
Simulation time 6076867346 ps
CPU time 817.19 seconds
Started Jun 30 05:33:31 PM PDT 24
Finished Jun 30 05:47:09 PM PDT 24
Peak memory 271936 kb
Host smart-2249b36e-688f-467d-93c7-22ade83fd0fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961456862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1961456862
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2698452358
Short name T8
Test name
Test status
Simulation time 53990248277 ps
CPU time 560.17 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:28:31 PM PDT 24
Peak memory 249388 kb
Host smart-21b35961-e817-4e13-bd88-0a1f42c2d822
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698452358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2698452358
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2666981018
Short name T307
Test name
Test status
Simulation time 91083525854 ps
CPU time 2116.18 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:54:21 PM PDT 24
Peak memory 273920 kb
Host smart-2189e393-4f35-495e-b00b-10ac0d8dd5cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666981018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2666981018
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4075907069
Short name T103
Test name
Test status
Simulation time 75259622558 ps
CPU time 5205.81 seconds
Started Jun 30 05:20:23 PM PDT 24
Finished Jun 30 06:47:10 PM PDT 24
Peak memory 331808 kb
Host smart-de9b3825-732e-4c0b-bfd0-42ea333eef87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075907069 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4075907069
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2988853028
Short name T144
Test name
Test status
Simulation time 4966919086 ps
CPU time 700.42 seconds
Started Jun 30 05:33:24 PM PDT 24
Finished Jun 30 05:45:05 PM PDT 24
Peak memory 265392 kb
Host smart-e41d3f11-07c2-4d6a-8fcd-3a14cfbfec21
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988853028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2988853028
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2019012082
Short name T640
Test name
Test status
Simulation time 24061081429 ps
CPU time 419.32 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:26:48 PM PDT 24
Peak memory 249368 kb
Host smart-04294eb4-1edd-4fc5-8882-56f44c538146
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019012082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2019012082
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3412698758
Short name T286
Test name
Test status
Simulation time 15718252093 ps
CPU time 328.58 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:25:17 PM PDT 24
Peak memory 249384 kb
Host smart-2dfe5bf4-8434-4cf9-b579-5491166c0650
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412698758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3412698758
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3431222185
Short name T10
Test name
Test status
Simulation time 44394120904 ps
CPU time 1357.52 seconds
Started Jun 30 05:19:26 PM PDT 24
Finished Jun 30 05:42:04 PM PDT 24
Peak memory 273880 kb
Host smart-be7d3ab6-7e43-43b4-acb7-6b5758c5ead9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431222185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3431222185
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3474167856
Short name T88
Test name
Test status
Simulation time 24194706394 ps
CPU time 993.13 seconds
Started Jun 30 05:19:11 PM PDT 24
Finished Jun 30 05:35:46 PM PDT 24
Peak memory 283892 kb
Host smart-228c509a-ce23-4c7b-b808-f98e07897632
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474167856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3474167856
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2151327700
Short name T133
Test name
Test status
Simulation time 2718562234 ps
CPU time 181.97 seconds
Started Jun 30 05:33:30 PM PDT 24
Finished Jun 30 05:36:32 PM PDT 24
Peak memory 257284 kb
Host smart-26bac0f4-c75d-47e9-a17a-9f70a55591be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2151327700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2151327700
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1521325662
Short name T705
Test name
Test status
Simulation time 78290875149 ps
CPU time 2324.72 seconds
Started Jun 30 05:21:01 PM PDT 24
Finished Jun 30 05:59:46 PM PDT 24
Peak memory 287128 kb
Host smart-ad5618c0-907e-4d7a-a561-bde01790bbb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521325662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1521325662
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.479707788
Short name T175
Test name
Test status
Simulation time 145625818137 ps
CPU time 1206.13 seconds
Started Jun 30 05:21:22 PM PDT 24
Finished Jun 30 05:41:29 PM PDT 24
Peak memory 273604 kb
Host smart-41f725a5-43ae-44a8-8fc2-d970d3e3bfe5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479707788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.479707788
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.621927436
Short name T250
Test name
Test status
Simulation time 217692647826 ps
CPU time 2945.11 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 06:08:13 PM PDT 24
Peak memory 289724 kb
Host smart-90fcb74b-8fdc-4758-93dc-ea0a704e4620
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621927436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.621927436
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2819478716
Short name T134
Test name
Test status
Simulation time 2696867907 ps
CPU time 226.51 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:37:40 PM PDT 24
Peak memory 265392 kb
Host smart-4d182ce2-2e0a-4011-8017-af061dc406ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819478716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2819478716
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1550217039
Short name T222
Test name
Test status
Simulation time 7887852 ps
CPU time 1.33 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:33:49 PM PDT 24
Peak memory 237612 kb
Host smart-657a8761-35dc-40bd-8c36-430f8f34a9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1550217039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1550217039
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2639226906
Short name T268
Test name
Test status
Simulation time 86350651217 ps
CPU time 772.66 seconds
Started Jun 30 05:20:32 PM PDT 24
Finished Jun 30 05:33:26 PM PDT 24
Peak memory 265736 kb
Host smart-760d3ac0-99ce-45cf-9c90-f74b113cb26f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639226906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2639226906
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.128313266
Short name T136
Test name
Test status
Simulation time 17761874630 ps
CPU time 1294.31 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:55:01 PM PDT 24
Peak memory 265448 kb
Host smart-5365fd48-3989-45ed-9a6e-e1c896fe7a8d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128313266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.128313266
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1914082411
Short name T282
Test name
Test status
Simulation time 151395087375 ps
CPU time 1623.63 seconds
Started Jun 30 05:19:29 PM PDT 24
Finished Jun 30 05:46:33 PM PDT 24
Peak memory 273912 kb
Host smart-1cc76ca5-79fa-4862-ab5c-7f5bd705d949
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914082411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1914082411
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.4244319064
Short name T663
Test name
Test status
Simulation time 54951776859 ps
CPU time 1498.27 seconds
Started Jun 30 05:19:34 PM PDT 24
Finished Jun 30 05:44:33 PM PDT 24
Peak memory 273192 kb
Host smart-a5f2cae0-6f48-4351-a951-6f717a6bb32e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244319064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.4244319064
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1968100484
Short name T252
Test name
Test status
Simulation time 34597261390 ps
CPU time 1309.41 seconds
Started Jun 30 05:19:43 PM PDT 24
Finished Jun 30 05:41:34 PM PDT 24
Peak memory 289868 kb
Host smart-81a1c952-a08b-479d-a73e-bb3a3a967912
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968100484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1968100484
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2098146230
Short name T274
Test name
Test status
Simulation time 13474138962 ps
CPU time 558.19 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 05:29:05 PM PDT 24
Peak memory 256488 kb
Host smart-423b2715-1c68-4c14-8f69-8e25b9660155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098146230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2098146230
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1571818207
Short name T317
Test name
Test status
Simulation time 14713377214 ps
CPU time 155.79 seconds
Started Jun 30 05:21:19 PM PDT 24
Finished Jun 30 05:23:55 PM PDT 24
Peak memory 249396 kb
Host smart-e1a740b3-3ecf-4ef8-8bc5-933b8d25e93f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571818207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1571818207
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.4120541079
Short name T148
Test name
Test status
Simulation time 6107497077 ps
CPU time 515.82 seconds
Started Jun 30 05:33:49 PM PDT 24
Finished Jun 30 05:42:25 PM PDT 24
Peak memory 268808 kb
Host smart-3d2bec27-ab1c-4a78-9d78-54ed190d7709
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120541079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.4120541079
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3078424702
Short name T163
Test name
Test status
Simulation time 63208091 ps
CPU time 3.16 seconds
Started Jun 30 05:33:47 PM PDT 24
Finished Jun 30 05:33:52 PM PDT 24
Peak memory 238028 kb
Host smart-b810d184-e5bc-4656-b2ff-1ce5bd95a6db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3078424702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3078424702
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2347287018
Short name T21
Test name
Test status
Simulation time 100138957 ps
CPU time 3.57 seconds
Started Jun 30 05:19:05 PM PDT 24
Finished Jun 30 05:19:13 PM PDT 24
Peak memory 249516 kb
Host smart-84e2395c-2e27-45ff-b579-2209b4e00146
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2347287018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2347287018
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.635566012
Short name T201
Test name
Test status
Simulation time 38884008 ps
CPU time 2.21 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:09 PM PDT 24
Peak memory 249256 kb
Host smart-4b4ed530-6e54-45ce-81f0-20a33680bcc6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=635566012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.635566012
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4225419390
Short name T205
Test name
Test status
Simulation time 95654017 ps
CPU time 3.54 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:19:17 PM PDT 24
Peak memory 249500 kb
Host smart-9659b275-d2c3-455e-b2e1-34d8f9a81324
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4225419390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4225419390
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1543281955
Short name T202
Test name
Test status
Simulation time 17660654 ps
CPU time 2.92 seconds
Started Jun 30 05:19:33 PM PDT 24
Finished Jun 30 05:19:36 PM PDT 24
Peak memory 249468 kb
Host smart-6c9de7ed-b5cf-4aeb-b16d-057e7501e919
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1543281955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1543281955
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2439758360
Short name T743
Test name
Test status
Simulation time 13352222 ps
CPU time 1.64 seconds
Started Jun 30 05:34:09 PM PDT 24
Finished Jun 30 05:34:11 PM PDT 24
Peak memory 237584 kb
Host smart-963ee871-7774-4d7b-b26c-0d4758ae5332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2439758360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2439758360
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1084891336
Short name T241
Test name
Test status
Simulation time 120081752436 ps
CPU time 2409.19 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:59:47 PM PDT 24
Peak memory 290320 kb
Host smart-3b785bec-97bb-439f-90fe-c497bf327cb5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084891336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1084891336
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2013842794
Short name T319
Test name
Test status
Simulation time 33591188867 ps
CPU time 380.94 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:25:59 PM PDT 24
Peak memory 249372 kb
Host smart-a59b9880-ca81-499a-bfd0-7e25ea776226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013842794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2013842794
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2173983952
Short name T192
Test name
Test status
Simulation time 42013757131 ps
CPU time 3969.01 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 06:25:46 PM PDT 24
Peak memory 339128 kb
Host smart-c8b34649-06d9-43a3-9ad5-99a633b8e7fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173983952 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2173983952
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2263273896
Short name T125
Test name
Test status
Simulation time 12797680509 ps
CPU time 1006.4 seconds
Started Jun 30 05:33:59 PM PDT 24
Finished Jun 30 05:50:46 PM PDT 24
Peak memory 273088 kb
Host smart-88a9b421-45bf-46d4-b679-1a5b95eb2e74
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263273896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2263273896
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3525718340
Short name T137
Test name
Test status
Simulation time 33215091033 ps
CPU time 590.14 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:43:44 PM PDT 24
Peak memory 265424 kb
Host smart-9c560014-08d6-4d4a-bd6e-af9b850cb847
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525718340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3525718340
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3336243780
Short name T2
Test name
Test status
Simulation time 3725257823 ps
CPU time 61.62 seconds
Started Jun 30 05:20:29 PM PDT 24
Finished Jun 30 05:21:31 PM PDT 24
Peak memory 249316 kb
Host smart-41fa8627-d16b-4eef-a494-6037861eb56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362
43780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3336243780
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3982690118
Short name T31
Test name
Test status
Simulation time 386989909375 ps
CPU time 2245.75 seconds
Started Jun 30 05:19:19 PM PDT 24
Finished Jun 30 05:56:45 PM PDT 24
Peak memory 289660 kb
Host smart-81c4f3dd-1791-4737-8894-1dfb78eb4890
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982690118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3982690118
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2655291727
Short name T54
Test name
Test status
Simulation time 3782999743 ps
CPU time 31.7 seconds
Started Jun 30 05:19:05 PM PDT 24
Finished Jun 30 05:19:41 PM PDT 24
Peak memory 257504 kb
Host smart-bda7ed38-ceab-47e7-8d78-90ce5e838a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26552
91727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2655291727
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2783801845
Short name T275
Test name
Test status
Simulation time 4695276372 ps
CPU time 52.61 seconds
Started Jun 30 05:19:04 PM PDT 24
Finished Jun 30 05:20:01 PM PDT 24
Peak memory 249404 kb
Host smart-65a90c5e-0a62-4418-9a19-1dba4176ca06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27838
01845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2783801845
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1186989808
Short name T315
Test name
Test status
Simulation time 13490969070 ps
CPU time 1235.08 seconds
Started Jun 30 05:19:25 PM PDT 24
Finished Jun 30 05:40:00 PM PDT 24
Peak memory 273840 kb
Host smart-6d0e9bf6-0319-48d8-823c-6e7b6911a001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186989808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1186989808
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.571120149
Short name T240
Test name
Test status
Simulation time 46204316463 ps
CPU time 4639.05 seconds
Started Jun 30 05:19:39 PM PDT 24
Finished Jun 30 06:36:59 PM PDT 24
Peak memory 338984 kb
Host smart-00b411a4-e6c1-4051-ba7f-86c8bcf72a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571120149 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.571120149
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3128947662
Short name T239
Test name
Test status
Simulation time 768964549 ps
CPU time 50.98 seconds
Started Jun 30 05:19:19 PM PDT 24
Finished Jun 30 05:20:10 PM PDT 24
Peak memory 250276 kb
Host smart-4e497c4f-5bf0-4c05-8a3b-6b6fa132c3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31289
47662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3128947662
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3981414814
Short name T74
Test name
Test status
Simulation time 474758910 ps
CPU time 14.88 seconds
Started Jun 30 05:19:50 PM PDT 24
Finished Jun 30 05:20:06 PM PDT 24
Peak memory 248756 kb
Host smart-c27867b9-de3b-4aea-841a-a8052471acf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39814
14814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3981414814
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.889230138
Short name T277
Test name
Test status
Simulation time 766828756 ps
CPU time 70.54 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:20:47 PM PDT 24
Peak memory 257472 kb
Host smart-58833cab-2853-497a-97d1-88977c51dd99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889230138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.889230138
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3046269177
Short name T82
Test name
Test status
Simulation time 87249806363 ps
CPU time 4375.01 seconds
Started Jun 30 05:19:57 PM PDT 24
Finished Jun 30 06:32:52 PM PDT 24
Peak memory 339232 kb
Host smart-c74d9347-d55f-4c00-953f-2239281562dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046269177 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3046269177
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.4192694074
Short name T242
Test name
Test status
Simulation time 1173132417 ps
CPU time 36.36 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:20:30 PM PDT 24
Peak memory 256992 kb
Host smart-012b1360-4a13-4111-a932-f781f125bec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41926
94074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.4192694074
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1157553534
Short name T56
Test name
Test status
Simulation time 2662887195 ps
CPU time 51.82 seconds
Started Jun 30 05:20:02 PM PDT 24
Finished Jun 30 05:20:55 PM PDT 24
Peak memory 249396 kb
Host smart-d3d507ad-a645-4c79-94fa-2a05a8038d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11575
53534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1157553534
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3239649895
Short name T254
Test name
Test status
Simulation time 498282520 ps
CPU time 19.72 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:20:40 PM PDT 24
Peak memory 248764 kb
Host smart-691b7663-51cf-4d73-b83f-2d67df619d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
49895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3239649895
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3894738787
Short name T265
Test name
Test status
Simulation time 56885560791 ps
CPU time 2938.67 seconds
Started Jun 30 05:18:59 PM PDT 24
Finished Jun 30 06:07:59 PM PDT 24
Peak memory 323008 kb
Host smart-ef9a07b6-c3c9-4ef4-9304-2cccb87044b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894738787 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3894738787
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3848967211
Short name T251
Test name
Test status
Simulation time 3860492146 ps
CPU time 27.53 seconds
Started Jun 30 05:20:46 PM PDT 24
Finished Jun 30 05:21:14 PM PDT 24
Peak memory 256168 kb
Host smart-6f6bc280-f1be-42b2-ab50-84c2d64d909d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38489
67211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3848967211
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1838220318
Short name T138
Test name
Test status
Simulation time 14683103236 ps
CPU time 279.47 seconds
Started Jun 30 05:33:33 PM PDT 24
Finished Jun 30 05:38:13 PM PDT 24
Peak memory 265472 kb
Host smart-7f15ec20-6781-459f-abcf-b5ea7319f2d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1838220318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1838220318
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2650678594
Short name T158
Test name
Test status
Simulation time 168367029 ps
CPU time 2.45 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:33:42 PM PDT 24
Peak memory 238592 kb
Host smart-16644a1f-d315-4be4-92ee-cf00365eab65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2650678594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2650678594
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.548988850
Short name T156
Test name
Test status
Simulation time 3617115489 ps
CPU time 44.53 seconds
Started Jun 30 05:33:43 PM PDT 24
Finished Jun 30 05:34:28 PM PDT 24
Peak memory 240600 kb
Host smart-6734590f-70c6-4365-b2ac-b972dc494bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=548988850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.548988850
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3495992265
Short name T159
Test name
Test status
Simulation time 205836384 ps
CPU time 4.17 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:13 PM PDT 24
Peak memory 236652 kb
Host smart-372f06d7-1a03-4c7f-9144-6ce3a571d702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3495992265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3495992265
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2719865376
Short name T165
Test name
Test status
Simulation time 55932893 ps
CPU time 2.94 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:33:20 PM PDT 24
Peak memory 237584 kb
Host smart-707298b8-6521-409a-8570-3882231192d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2719865376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2719865376
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2162389949
Short name T160
Test name
Test status
Simulation time 1211196379 ps
CPU time 47.05 seconds
Started Jun 30 05:33:47 PM PDT 24
Finished Jun 30 05:34:35 PM PDT 24
Peak memory 240692 kb
Host smart-e0eb2d1c-a027-4f6b-9e55-0325a52fdf29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2162389949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2162389949
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3075898932
Short name T161
Test name
Test status
Simulation time 1076811442 ps
CPU time 37.59 seconds
Started Jun 30 05:33:54 PM PDT 24
Finished Jun 30 05:34:32 PM PDT 24
Peak memory 237816 kb
Host smart-fa2aa0bb-65cf-480e-a599-08a78653011c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3075898932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3075898932
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3780998205
Short name T167
Test name
Test status
Simulation time 4022512611 ps
CPU time 66.89 seconds
Started Jun 30 05:34:02 PM PDT 24
Finished Jun 30 05:35:09 PM PDT 24
Peak memory 238784 kb
Host smart-1ad1e073-b401-421f-b08d-86d752d6f79a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3780998205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3780998205
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3523976693
Short name T157
Test name
Test status
Simulation time 623321732 ps
CPU time 39.6 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:48 PM PDT 24
Peak memory 240664 kb
Host smart-cb2d365d-6252-422d-ba9a-40c0419399af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3523976693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3523976693
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2151021475
Short name T162
Test name
Test status
Simulation time 603862338 ps
CPU time 22.22 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:49 PM PDT 24
Peak memory 245788 kb
Host smart-4ba7b3ae-d626-4935-afad-36c968bc6c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2151021475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2151021475
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3113616139
Short name T151
Test name
Test status
Simulation time 925655777 ps
CPU time 64.37 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:34:31 PM PDT 24
Peak memory 240496 kb
Host smart-26ff39ab-ef63-4b10-b367-f30fe3fc5fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3113616139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3113616139
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2256301926
Short name T149
Test name
Test status
Simulation time 1713070883 ps
CPU time 38.18 seconds
Started Jun 30 05:33:18 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 240532 kb
Host smart-bfe236e6-6475-42fc-a070-62e55e6d23e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2256301926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2256301926
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2492151564
Short name T170
Test name
Test status
Simulation time 62521788 ps
CPU time 3.53 seconds
Started Jun 30 05:33:54 PM PDT 24
Finished Jun 30 05:33:58 PM PDT 24
Peak memory 236664 kb
Host smart-d6a0ecbc-c3bd-42cb-8276-b61b0b2c00d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2492151564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2492151564
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3528728681
Short name T155
Test name
Test status
Simulation time 30225080 ps
CPU time 2.74 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:33:43 PM PDT 24
Peak memory 237568 kb
Host smart-0277d311-bf72-4774-a7ce-0c7143ed510e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3528728681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3528728681
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.231387595
Short name T164
Test name
Test status
Simulation time 92005424 ps
CPU time 3.64 seconds
Started Jun 30 05:33:32 PM PDT 24
Finished Jun 30 05:33:36 PM PDT 24
Peak memory 237596 kb
Host smart-391564f5-d069-4b6c-8446-95ec9b393b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=231387595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.231387595
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1730868735
Short name T166
Test name
Test status
Simulation time 1206735428 ps
CPU time 45.56 seconds
Started Jun 30 05:33:40 PM PDT 24
Finished Jun 30 05:34:26 PM PDT 24
Peak memory 237816 kb
Host smart-cefc969d-390e-4a19-beb8-42eeef01473c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1730868735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1730868735
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3333469198
Short name T753
Test name
Test status
Simulation time 4445787615 ps
CPU time 316.7 seconds
Started Jun 30 05:33:20 PM PDT 24
Finished Jun 30 05:38:38 PM PDT 24
Peak memory 241052 kb
Host smart-45d439b8-4551-4945-a5ef-8fde9ba1e888
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3333469198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3333469198
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1372637892
Short name T747
Test name
Test status
Simulation time 3407454055 ps
CPU time 103.15 seconds
Started Jun 30 05:33:23 PM PDT 24
Finished Jun 30 05:35:06 PM PDT 24
Peak memory 240616 kb
Host smart-08fbd048-63f9-40f4-b9f0-34f74b07dbad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1372637892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1372637892
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4235620294
Short name T724
Test name
Test status
Simulation time 77636889 ps
CPU time 5.88 seconds
Started Jun 30 05:33:18 PM PDT 24
Finished Jun 30 05:33:24 PM PDT 24
Peak memory 249072 kb
Host smart-32d4f980-9c52-4a3a-9cd6-7fd880a37bfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4235620294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4235620294
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2225837527
Short name T744
Test name
Test status
Simulation time 45245800 ps
CPU time 6.33 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:33:24 PM PDT 24
Peak memory 243140 kb
Host smart-873cfc42-1b65-4b37-900a-d5e1797f1091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225837527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2225837527
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3085869411
Short name T745
Test name
Test status
Simulation time 72962576 ps
CPU time 5.83 seconds
Started Jun 30 05:33:18 PM PDT 24
Finished Jun 30 05:33:25 PM PDT 24
Peak memory 240396 kb
Host smart-86a49b7e-70a6-43e7-a614-5cbb7dfb34c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3085869411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3085869411
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4147686698
Short name T823
Test name
Test status
Simulation time 11179171 ps
CPU time 1.6 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:33:20 PM PDT 24
Peak memory 237620 kb
Host smart-3c7852d7-c9a2-4d0f-aa16-ddbcb4ae8a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4147686698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4147686698
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3493831700
Short name T757
Test name
Test status
Simulation time 95131144 ps
CPU time 15.18 seconds
Started Jun 30 05:33:20 PM PDT 24
Finished Jun 30 05:33:36 PM PDT 24
Peak memory 245812 kb
Host smart-cdee0ccc-c76a-46fa-9776-46427d1c47a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3493831700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3493831700
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4058382339
Short name T122
Test name
Test status
Simulation time 1740839299 ps
CPU time 111.53 seconds
Started Jun 30 05:33:18 PM PDT 24
Finished Jun 30 05:35:10 PM PDT 24
Peak memory 265352 kb
Host smart-e455a474-9965-4e50-ba40-c234c6e82e3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4058382339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4058382339
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3939083520
Short name T123
Test name
Test status
Simulation time 13051499312 ps
CPU time 1133.52 seconds
Started Jun 30 05:33:18 PM PDT 24
Finished Jun 30 05:52:12 PM PDT 24
Peak memory 265600 kb
Host smart-f2c917d1-fd46-40d6-bfe3-8aa87ff9e81b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939083520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3939083520
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1175675957
Short name T778
Test name
Test status
Simulation time 60994836 ps
CPU time 9.78 seconds
Started Jun 30 05:33:20 PM PDT 24
Finished Jun 30 05:33:31 PM PDT 24
Peak memory 252888 kb
Host smart-1ee91f55-0104-4cf9-a74c-cd4fd6ca7b54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1175675957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1175675957
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3008046337
Short name T796
Test name
Test status
Simulation time 7055223227 ps
CPU time 172.19 seconds
Started Jun 30 05:33:23 PM PDT 24
Finished Jun 30 05:36:16 PM PDT 24
Peak memory 240620 kb
Host smart-91892ae0-c962-418f-a5af-0f8c59b2e94e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3008046337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3008046337
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2260338792
Short name T801
Test name
Test status
Simulation time 4450855888 ps
CPU time 254.38 seconds
Started Jun 30 05:33:19 PM PDT 24
Finished Jun 30 05:37:34 PM PDT 24
Peak memory 237676 kb
Host smart-1ced41d1-d9e9-4ca8-a093-ad1577b1ddc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2260338792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2260338792
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1768466980
Short name T812
Test name
Test status
Simulation time 130426060 ps
CPU time 10.59 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:33:29 PM PDT 24
Peak memory 249216 kb
Host smart-d492acc8-1db3-4994-a032-007d25ee3e25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1768466980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1768466980
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.563604622
Short name T194
Test name
Test status
Simulation time 483965818 ps
CPU time 5.41 seconds
Started Jun 30 05:33:20 PM PDT 24
Finished Jun 30 05:33:26 PM PDT 24
Peak memory 240380 kb
Host smart-45aae523-e285-4f82-a1e3-5d87cdb306b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563604622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.563604622
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3276504481
Short name T815
Test name
Test status
Simulation time 137417364 ps
CPU time 7.84 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:33:26 PM PDT 24
Peak memory 237560 kb
Host smart-f801343a-8da4-4ec2-983b-b045d47cd047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3276504481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3276504481
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3664440996
Short name T830
Test name
Test status
Simulation time 8095831 ps
CPU time 1.33 seconds
Started Jun 30 05:33:23 PM PDT 24
Finished Jun 30 05:33:25 PM PDT 24
Peak memory 237608 kb
Host smart-c46d1074-1ac5-4d8b-b00d-45c62ca1ba53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3664440996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3664440996
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3005733889
Short name T185
Test name
Test status
Simulation time 2025341482 ps
CPU time 25.65 seconds
Started Jun 30 05:33:22 PM PDT 24
Finished Jun 30 05:33:48 PM PDT 24
Peak memory 240560 kb
Host smart-068d6403-d9f3-4ed3-bced-7051493bb0ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3005733889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3005733889
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1518897248
Short name T740
Test name
Test status
Simulation time 1063422804 ps
CPU time 16.09 seconds
Started Jun 30 05:33:18 PM PDT 24
Finished Jun 30 05:33:35 PM PDT 24
Peak memory 248360 kb
Host smart-b6e8b5d4-07b5-40ca-8f2a-8f892cf5e537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1518897248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1518897248
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3226518398
Short name T813
Test name
Test status
Simulation time 713636931 ps
CPU time 11.95 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 251876 kb
Host smart-b209e7d0-934a-4aa8-9bb8-3043873cc04f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226518398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3226518398
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3364653563
Short name T720
Test name
Test status
Simulation time 62994963 ps
CPU time 6.01 seconds
Started Jun 30 05:33:44 PM PDT 24
Finished Jun 30 05:33:50 PM PDT 24
Peak memory 240504 kb
Host smart-d6054689-a1bd-414c-bb0f-035f0b37e9b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3364653563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3364653563
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1884861737
Short name T728
Test name
Test status
Simulation time 1385046478 ps
CPU time 24.17 seconds
Started Jun 30 05:33:47 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 245968 kb
Host smart-a15f0d9e-36fd-4dd5-8dc0-d9bc3179fa0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1884861737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1884861737
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2829445562
Short name T121
Test name
Test status
Simulation time 73144496736 ps
CPU time 280.01 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:38:19 PM PDT 24
Peak memory 265468 kb
Host smart-308306bc-a6aa-46eb-8c0b-942dc2bf8c49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2829445562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2829445562
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2696086970
Short name T147
Test name
Test status
Simulation time 2285356519 ps
CPU time 420.2 seconds
Started Jun 30 05:33:38 PM PDT 24
Finished Jun 30 05:40:39 PM PDT 24
Peak memory 270028 kb
Host smart-30ddfceb-69bd-452e-8416-b48c246accc7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696086970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2696086970
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1252989730
Short name T231
Test name
Test status
Simulation time 151524372 ps
CPU time 10.47 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:33:50 PM PDT 24
Peak memory 248808 kb
Host smart-d6317875-6bea-4ba7-a602-3bdd6ca225a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1252989730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1252989730
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4057907227
Short name T767
Test name
Test status
Simulation time 41769640 ps
CPU time 2.35 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:33:48 PM PDT 24
Peak memory 237596 kb
Host smart-02c94bcd-e627-46fe-a9b1-e97b2d5d6295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4057907227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4057907227
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2468924714
Short name T716
Test name
Test status
Simulation time 255560085 ps
CPU time 12.45 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:34:00 PM PDT 24
Peak memory 256296 kb
Host smart-cd432d15-14e8-41d8-ad69-b9cc305331ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468924714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2468924714
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.122580961
Short name T785
Test name
Test status
Simulation time 51316522 ps
CPU time 5.03 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:33:51 PM PDT 24
Peak memory 237600 kb
Host smart-c171d1c4-9e7d-4b29-87ba-75e598ef4694
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=122580961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.122580961
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2818013712
Short name T821
Test name
Test status
Simulation time 10665192 ps
CPU time 1.45 seconds
Started Jun 30 05:33:44 PM PDT 24
Finished Jun 30 05:33:46 PM PDT 24
Peak memory 236620 kb
Host smart-14c69fdf-e94d-4b7f-9e56-1b26a814bafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2818013712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2818013712
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.80871593
Short name T817
Test name
Test status
Simulation time 517147950 ps
CPU time 38.81 seconds
Started Jun 30 05:33:47 PM PDT 24
Finished Jun 30 05:34:27 PM PDT 24
Peak memory 244876 kb
Host smart-48f623b7-a735-4571-9411-e34b034b4310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=80871593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outs
tanding.80871593
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2425656643
Short name T141
Test name
Test status
Simulation time 8637747070 ps
CPU time 135.73 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:36:02 PM PDT 24
Peak memory 265680 kb
Host smart-0076930c-5c0e-4159-862a-93c1ea3845b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2425656643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2425656643
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3012805760
Short name T131
Test name
Test status
Simulation time 84051396295 ps
CPU time 572.95 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:43:21 PM PDT 24
Peak memory 269624 kb
Host smart-f6072271-b85f-4279-b2f6-770715ef6a1a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012805760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3012805760
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3163024712
Short name T756
Test name
Test status
Simulation time 86974364 ps
CPU time 6.69 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:33:53 PM PDT 24
Peak memory 247328 kb
Host smart-e2c41407-88e3-42b5-846f-47e218055560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3163024712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3163024712
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.655325593
Short name T751
Test name
Test status
Simulation time 34107488 ps
CPU time 5.9 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:33:53 PM PDT 24
Peak memory 242124 kb
Host smart-72b36487-8e49-461f-a915-3c5646a780d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655325593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.655325593
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.359086130
Short name T818
Test name
Test status
Simulation time 214856490 ps
CPU time 4.92 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:33:52 PM PDT 24
Peak memory 237620 kb
Host smart-48ffdfe2-c383-4956-9b0e-7dc27a1a10de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=359086130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.359086130
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1042729167
Short name T714
Test name
Test status
Simulation time 9375814 ps
CPU time 1.56 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:33:49 PM PDT 24
Peak memory 235660 kb
Host smart-6fb53173-aae0-45cc-ace5-2b567040ad5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1042729167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1042729167
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1422838049
Short name T786
Test name
Test status
Simulation time 349910777 ps
CPU time 25.38 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 248656 kb
Host smart-449ae45c-ad26-4bb1-ab69-1c1ca9eae0f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1422838049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1422838049
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.253589840
Short name T113
Test name
Test status
Simulation time 4386550525 ps
CPU time 320.72 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:39:06 PM PDT 24
Peak memory 272932 kb
Host smart-9ef915c3-da3c-4cdb-accb-dcf145fcd181
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=253589840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.253589840
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1502263537
Short name T135
Test name
Test status
Simulation time 23653002848 ps
CPU time 925.99 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:49:14 PM PDT 24
Peak memory 265396 kb
Host smart-a111f867-4820-4c9d-ab8e-9824c34cfe85
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502263537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1502263537
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1225642445
Short name T731
Test name
Test status
Simulation time 1314436328 ps
CPU time 24.88 seconds
Started Jun 30 05:33:44 PM PDT 24
Finished Jun 30 05:34:09 PM PDT 24
Peak memory 248764 kb
Host smart-b260c553-b8e9-400a-9d75-359e455423d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1225642445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1225642445
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2883555741
Short name T803
Test name
Test status
Simulation time 124293384 ps
CPU time 5.28 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:33:52 PM PDT 24
Peak memory 248820 kb
Host smart-ad3aa55e-abc1-4dd5-bfc8-f44888aa2bb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883555741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2883555741
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2168114683
Short name T183
Test name
Test status
Simulation time 118758759 ps
CPU time 8.46 seconds
Started Jun 30 05:33:47 PM PDT 24
Finished Jun 30 05:33:56 PM PDT 24
Peak memory 240552 kb
Host smart-c526b8d2-0948-4c4a-9a15-13eaa2300ff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2168114683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2168114683
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1441116262
Short name T712
Test name
Test status
Simulation time 9735026 ps
CPU time 1.27 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:33:48 PM PDT 24
Peak memory 235684 kb
Host smart-b4bb075a-828d-4e0b-b0d3-8a6be91d5984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1441116262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1441116262
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3165943891
Short name T819
Test name
Test status
Simulation time 342720029 ps
CPU time 15.05 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:34:01 PM PDT 24
Peak memory 240460 kb
Host smart-58f49e22-a611-4d4e-8b19-b2c48979a3ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3165943891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3165943891
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1946376195
Short name T120
Test name
Test status
Simulation time 2746652813 ps
CPU time 176.88 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:36:45 PM PDT 24
Peak memory 269900 kb
Host smart-fa774ad6-0cc8-4fb0-8ca7-075e982b2ef2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1946376195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1946376195
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3364137716
Short name T790
Test name
Test status
Simulation time 319691324 ps
CPU time 11.39 seconds
Started Jun 30 05:33:47 PM PDT 24
Finished Jun 30 05:33:59 PM PDT 24
Peak memory 255852 kb
Host smart-467906d9-0bad-4d93-bf8a-72f1dc2784be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3364137716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3364137716
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.756853636
Short name T732
Test name
Test status
Simulation time 130676267 ps
CPU time 5.4 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:33:59 PM PDT 24
Peak memory 256876 kb
Host smart-4c3894ab-2c8c-4979-9197-14812fec9470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756853636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.756853636
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.711699795
Short name T808
Test name
Test status
Simulation time 169718579 ps
CPU time 4.73 seconds
Started Jun 30 05:33:54 PM PDT 24
Finished Jun 30 05:33:59 PM PDT 24
Peak memory 236656 kb
Host smart-326e3f79-046a-47c6-938f-0b5347f69d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=711699795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.711699795
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.791992957
Short name T715
Test name
Test status
Simulation time 27943142 ps
CPU time 1.39 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:33:55 PM PDT 24
Peak memory 235636 kb
Host smart-8e16a23e-215c-4f97-a76d-5b22d1d696f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=791992957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.791992957
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1244960658
Short name T798
Test name
Test status
Simulation time 966848572 ps
CPU time 40.01 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:34:34 PM PDT 24
Peak memory 245796 kb
Host smart-2eaad737-c0c0-43a0-9d48-fe7d938e03f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1244960658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1244960658
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.111387549
Short name T834
Test name
Test status
Simulation time 8300176984 ps
CPU time 193.13 seconds
Started Jun 30 05:33:45 PM PDT 24
Finished Jun 30 05:36:58 PM PDT 24
Peak memory 265564 kb
Host smart-b365a653-7547-48b9-899c-4bc7fcc25c1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111387549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.111387549
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3977805770
Short name T128
Test name
Test status
Simulation time 7200360142 ps
CPU time 472.36 seconds
Started Jun 30 05:33:46 PM PDT 24
Finished Jun 30 05:41:40 PM PDT 24
Peak memory 265412 kb
Host smart-7a786ace-6ebe-463e-a9b4-6fe0433af3d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977805770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3977805770
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1117377608
Short name T713
Test name
Test status
Simulation time 1804779474 ps
CPU time 15.5 seconds
Started Jun 30 05:33:47 PM PDT 24
Finished Jun 30 05:34:03 PM PDT 24
Peak memory 248580 kb
Host smart-9a852887-7ed1-4030-a88e-b123ed827169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1117377608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1117377608
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2690878651
Short name T730
Test name
Test status
Simulation time 172707809 ps
CPU time 3.64 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:33:58 PM PDT 24
Peak memory 237692 kb
Host smart-24ba4764-0418-425d-8c48-8928f2852633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690878651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2690878651
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3594636165
Short name T810
Test name
Test status
Simulation time 72525569 ps
CPU time 3.53 seconds
Started Jun 30 05:33:52 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 240472 kb
Host smart-ccbf2abd-e2c2-4225-8fab-3efb58a9bb98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3594636165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3594636165
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.801211894
Short name T825
Test name
Test status
Simulation time 17024974 ps
CPU time 1.34 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:33:56 PM PDT 24
Peak memory 235656 kb
Host smart-6fad95fd-2e88-4346-8fa6-356e9186fd4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=801211894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.801211894
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3852774519
Short name T820
Test name
Test status
Simulation time 4504340270 ps
CPU time 39.3 seconds
Started Jun 30 05:33:54 PM PDT 24
Finished Jun 30 05:34:34 PM PDT 24
Peak memory 245848 kb
Host smart-7472d6b7-6b7f-4ba4-929e-524ca6f8949d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3852774519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3852774519
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3599270033
Short name T126
Test name
Test status
Simulation time 81152879987 ps
CPU time 337.67 seconds
Started Jun 30 05:33:54 PM PDT 24
Finished Jun 30 05:39:32 PM PDT 24
Peak memory 265456 kb
Host smart-532f0284-7036-429c-ac1f-4ce891e98ad9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3599270033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3599270033
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3350434028
Short name T145
Test name
Test status
Simulation time 8770405321 ps
CPU time 442.65 seconds
Started Jun 30 05:33:52 PM PDT 24
Finished Jun 30 05:41:16 PM PDT 24
Peak memory 265524 kb
Host smart-6d746fb5-f2b8-47f4-aacf-334ef1de7036
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350434028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3350434028
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2397954364
Short name T828
Test name
Test status
Simulation time 119022292 ps
CPU time 4.62 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:33:58 PM PDT 24
Peak memory 251452 kb
Host smart-aa723c2c-3eb1-45a9-9cee-61be3f7f6609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2397954364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2397954364
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.338904932
Short name T805
Test name
Test status
Simulation time 338755776 ps
CPU time 7.1 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:34:01 PM PDT 24
Peak memory 241216 kb
Host smart-e228f4c1-aa9a-4c22-8935-7d15347b8a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338904932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.338904932
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.556592540
Short name T749
Test name
Test status
Simulation time 21340242 ps
CPU time 3.3 seconds
Started Jun 30 05:33:55 PM PDT 24
Finished Jun 30 05:33:59 PM PDT 24
Peak memory 236652 kb
Host smart-fc774ef8-d534-4626-b8ae-e79e3e6cba4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=556592540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.556592540
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.126973276
Short name T343
Test name
Test status
Simulation time 18710513 ps
CPU time 1.42 seconds
Started Jun 30 05:33:54 PM PDT 24
Finished Jun 30 05:33:56 PM PDT 24
Peak memory 237608 kb
Host smart-e154c648-eef5-4fb1-a02c-15da884fea11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126973276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.126973276
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.87995189
Short name T762
Test name
Test status
Simulation time 520743933 ps
CPU time 34.22 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:34:28 PM PDT 24
Peak memory 245816 kb
Host smart-36eb5a27-008b-4fb5-a589-40d2a9bbaa01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=87995189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outs
tanding.87995189
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4203858330
Short name T794
Test name
Test status
Simulation time 421390449 ps
CPU time 25.99 seconds
Started Jun 30 05:33:54 PM PDT 24
Finished Jun 30 05:34:21 PM PDT 24
Peak memory 248796 kb
Host smart-ef94f1df-5c67-4310-908d-a8608e85bb95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4203858330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4203858330
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1498069795
Short name T771
Test name
Test status
Simulation time 373736569 ps
CPU time 7.57 seconds
Started Jun 30 05:34:00 PM PDT 24
Finished Jun 30 05:34:08 PM PDT 24
Peak memory 240536 kb
Host smart-68233ea1-46b3-400f-8be1-33bff8d8d715
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498069795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1498069795
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1515250338
Short name T738
Test name
Test status
Simulation time 21426227 ps
CPU time 3.72 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:11 PM PDT 24
Peak memory 236808 kb
Host smart-b792a404-d2a2-49a5-8675-20324f991598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1515250338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1515250338
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.10743008
Short name T822
Test name
Test status
Simulation time 12443052 ps
CPU time 1.47 seconds
Started Jun 30 05:34:01 PM PDT 24
Finished Jun 30 05:34:03 PM PDT 24
Peak memory 237592 kb
Host smart-f0e42df6-aec6-430a-baac-afba0c32c101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=10743008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.10743008
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.809057091
Short name T774
Test name
Test status
Simulation time 350517471 ps
CPU time 27.1 seconds
Started Jun 30 05:34:04 PM PDT 24
Finished Jun 30 05:34:32 PM PDT 24
Peak memory 245820 kb
Host smart-ac806438-82e8-4afa-8819-c20d93259a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=809057091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.809057091
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3921713711
Short name T129
Test name
Test status
Simulation time 4909075519 ps
CPU time 107.38 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:35:41 PM PDT 24
Peak memory 268880 kb
Host smart-34f6a12b-437d-4c38-8e8d-20f5c2babc7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3921713711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3921713711
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4100908716
Short name T346
Test name
Test status
Simulation time 61250948276 ps
CPU time 1246.7 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:54:41 PM PDT 24
Peak memory 265436 kb
Host smart-f26fa10a-43e6-4d30-b587-5e73baac13b1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100908716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.4100908716
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2403018011
Short name T709
Test name
Test status
Simulation time 311431614 ps
CPU time 6.19 seconds
Started Jun 30 05:33:53 PM PDT 24
Finished Jun 30 05:34:00 PM PDT 24
Peak memory 256508 kb
Host smart-45cb3857-2902-49a6-95de-495bf3c6dbcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2403018011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2403018011
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.633340314
Short name T779
Test name
Test status
Simulation time 84191405 ps
CPU time 7.11 seconds
Started Jun 30 05:33:59 PM PDT 24
Finished Jun 30 05:34:07 PM PDT 24
Peak memory 241296 kb
Host smart-8e4b8131-af9d-4976-ba18-96905425f9f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633340314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.633340314
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2464091842
Short name T795
Test name
Test status
Simulation time 19277667 ps
CPU time 4.08 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:13 PM PDT 24
Peak memory 237744 kb
Host smart-25b7590c-1cb7-47ac-b985-a192edc542ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2464091842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2464091842
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1842628678
Short name T341
Test name
Test status
Simulation time 8033498 ps
CPU time 1.38 seconds
Started Jun 30 05:33:59 PM PDT 24
Finished Jun 30 05:34:01 PM PDT 24
Peak memory 237596 kb
Host smart-072f4f94-51cb-4d61-81e8-3d735ab25965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1842628678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1842628678
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3847801343
Short name T832
Test name
Test status
Simulation time 705487519 ps
CPU time 38.85 seconds
Started Jun 30 05:34:10 PM PDT 24
Finished Jun 30 05:34:49 PM PDT 24
Peak memory 244988 kb
Host smart-f95e3283-7f07-4f93-af2c-75eda7ee2e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3847801343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3847801343
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2742047785
Short name T139
Test name
Test status
Simulation time 8418105080 ps
CPU time 166.65 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:36:54 PM PDT 24
Peak memory 267232 kb
Host smart-18bee9df-784a-41f6-b04d-8077d522f203
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2742047785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2742047785
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3635794278
Short name T711
Test name
Test status
Simulation time 1252638566 ps
CPU time 21.1 seconds
Started Jun 30 05:34:00 PM PDT 24
Finished Jun 30 05:34:22 PM PDT 24
Peak memory 248796 kb
Host smart-b5a169ec-1870-4474-a6c9-0ad676699a48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3635794278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3635794278
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2314736302
Short name T168
Test name
Test status
Simulation time 131341198 ps
CPU time 6.62 seconds
Started Jun 30 05:33:59 PM PDT 24
Finished Jun 30 05:34:06 PM PDT 24
Peak memory 252780 kb
Host smart-cbe371b0-9cea-4d14-8e6e-36a38e68b8f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314736302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2314736302
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2651049831
Short name T181
Test name
Test status
Simulation time 191650060 ps
CPU time 4.92 seconds
Started Jun 30 05:34:03 PM PDT 24
Finished Jun 30 05:34:09 PM PDT 24
Peak memory 237504 kb
Host smart-57427cbb-7717-49ad-b7c4-2771eaf32428
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2651049831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2651049831
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1842748439
Short name T727
Test name
Test status
Simulation time 21016153 ps
CPU time 1.49 seconds
Started Jun 30 05:34:00 PM PDT 24
Finished Jun 30 05:34:02 PM PDT 24
Peak memory 236668 kb
Host smart-32d3d368-baf6-4343-a117-4bf95cee50e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1842748439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1842748439
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3971114538
Short name T750
Test name
Test status
Simulation time 91353376 ps
CPU time 14 seconds
Started Jun 30 05:34:03 PM PDT 24
Finished Jun 30 05:34:18 PM PDT 24
Peak memory 245708 kb
Host smart-1509f41d-d0b7-4425-b26f-e1c11f94234f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3971114538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3971114538
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1615267477
Short name T143
Test name
Test status
Simulation time 2247750186 ps
CPU time 152.82 seconds
Started Jun 30 05:33:59 PM PDT 24
Finished Jun 30 05:36:32 PM PDT 24
Peak memory 265392 kb
Host smart-2370c889-02bb-4be9-a2b9-ca9df21aab6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1615267477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1615267477
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1713680489
Short name T140
Test name
Test status
Simulation time 9583149272 ps
CPU time 371.39 seconds
Started Jun 30 05:33:59 PM PDT 24
Finished Jun 30 05:40:11 PM PDT 24
Peak memory 265400 kb
Host smart-508af3f3-dcbf-44c6-a638-034ff6564113
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713680489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1713680489
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3618664981
Short name T229
Test name
Test status
Simulation time 87352275 ps
CPU time 7.23 seconds
Started Jun 30 05:34:04 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 248828 kb
Host smart-e473d0a4-59a3-42a1-a3d0-4b2fd2c5d1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3618664981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3618664981
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.721500031
Short name T754
Test name
Test status
Simulation time 1107850519 ps
CPU time 72.39 seconds
Started Jun 30 05:33:30 PM PDT 24
Finished Jun 30 05:34:43 PM PDT 24
Peak memory 237612 kb
Host smart-479dec22-7b89-41b8-b0f7-e1ead6baa9bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=721500031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.721500031
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2930996218
Short name T764
Test name
Test status
Simulation time 17823887977 ps
CPU time 495.5 seconds
Started Jun 30 05:33:28 PM PDT 24
Finished Jun 30 05:41:45 PM PDT 24
Peak memory 240632 kb
Host smart-4a447206-19ad-4c61-9469-c65132564960
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2930996218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2930996218
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1076699947
Short name T763
Test name
Test status
Simulation time 78835087 ps
CPU time 3.98 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:30 PM PDT 24
Peak memory 248740 kb
Host smart-cac6c7af-cb94-41fb-af10-0750e3b7f078
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1076699947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1076699947
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.471222100
Short name T777
Test name
Test status
Simulation time 133427840 ps
CPU time 10.75 seconds
Started Jun 30 05:33:24 PM PDT 24
Finished Jun 30 05:33:35 PM PDT 24
Peak memory 238004 kb
Host smart-c93bbf62-d9cd-4461-ba77-dd64ea96ceb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471222100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.471222100
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2234434022
Short name T230
Test name
Test status
Simulation time 1234241915 ps
CPU time 5.8 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:32 PM PDT 24
Peak memory 237440 kb
Host smart-2c45acd4-4320-4c74-896f-a112ccfaec77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2234434022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2234434022
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3808910795
Short name T755
Test name
Test status
Simulation time 10900928 ps
CPU time 1.38 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:33:28 PM PDT 24
Peak memory 237532 kb
Host smart-2d403b0f-edc1-44ff-9fbd-b424155d6062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3808910795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3808910795
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4219570809
Short name T811
Test name
Test status
Simulation time 2985627838 ps
CPU time 44.02 seconds
Started Jun 30 05:33:29 PM PDT 24
Finished Jun 30 05:34:13 PM PDT 24
Peak memory 245712 kb
Host smart-408d6a56-d660-4300-9d28-aea8858d1bfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4219570809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4219570809
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2540379265
Short name T116
Test name
Test status
Simulation time 6762925357 ps
CPU time 243.11 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:37:28 PM PDT 24
Peak memory 265432 kb
Host smart-9cfa7e8e-d39e-4c7d-b071-3e6e1dced77e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2540379265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2540379265
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2979471598
Short name T776
Test name
Test status
Simulation time 853488664 ps
CPU time 16.3 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:42 PM PDT 24
Peak memory 254836 kb
Host smart-4a39b567-98e5-43e6-95fd-5619a33013b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2979471598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2979471598
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3266644500
Short name T729
Test name
Test status
Simulation time 12236232 ps
CPU time 1.51 seconds
Started Jun 30 05:34:02 PM PDT 24
Finished Jun 30 05:34:04 PM PDT 24
Peak memory 236728 kb
Host smart-a041b430-0016-4d25-86f8-3dbc2393af2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3266644500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3266644500
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3022940210
Short name T344
Test name
Test status
Simulation time 6259936 ps
CPU time 1.41 seconds
Started Jun 30 05:34:05 PM PDT 24
Finished Jun 30 05:34:07 PM PDT 24
Peak memory 235644 kb
Host smart-a2d2d35e-d2cb-47c9-9243-6a01fdff5d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3022940210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3022940210
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2874596034
Short name T739
Test name
Test status
Simulation time 10908520 ps
CPU time 1.55 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 236664 kb
Host smart-e68889d6-a4a3-44cd-be5f-cfbeaa6accc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2874596034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2874596034
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1111238369
Short name T340
Test name
Test status
Simulation time 7069720 ps
CPU time 1.53 seconds
Started Jun 30 05:34:10 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 235656 kb
Host smart-8a62f172-754a-4405-8f44-af95b5a39991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1111238369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1111238369
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1934938340
Short name T770
Test name
Test status
Simulation time 8593792 ps
CPU time 1.49 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:09 PM PDT 24
Peak memory 236676 kb
Host smart-e47d1769-a4c0-4523-9709-55f2c8eac82e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1934938340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1934938340
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3792171486
Short name T718
Test name
Test status
Simulation time 15762656 ps
CPU time 1.29 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 237544 kb
Host smart-ddddaf5c-f563-4e2d-abd7-66c893216054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3792171486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3792171486
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3939962227
Short name T760
Test name
Test status
Simulation time 6390320 ps
CPU time 1.46 seconds
Started Jun 30 05:34:06 PM PDT 24
Finished Jun 30 05:34:08 PM PDT 24
Peak memory 235652 kb
Host smart-5920b760-8e1c-466e-a97e-870924518bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939962227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3939962227
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3053593583
Short name T768
Test name
Test status
Simulation time 10687093 ps
CPU time 1.35 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 236588 kb
Host smart-eab676c5-3b2a-4084-9486-72fad7fb785d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3053593583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3053593583
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.244539569
Short name T154
Test name
Test status
Simulation time 14302462 ps
CPU time 1.72 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 236648 kb
Host smart-b5ce10aa-a9a1-4cd5-85aa-b37dbc1253d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=244539569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.244539569
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3937519470
Short name T737
Test name
Test status
Simulation time 9446439 ps
CPU time 1.45 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:08 PM PDT 24
Peak memory 235628 kb
Host smart-8600e6fc-39a9-4047-b1bc-5847f52b5983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3937519470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3937519470
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2162773530
Short name T791
Test name
Test status
Simulation time 6449891705 ps
CPU time 258.88 seconds
Started Jun 30 05:33:24 PM PDT 24
Finished Jun 30 05:37:44 PM PDT 24
Peak memory 241844 kb
Host smart-4d2f3a2f-4c0a-4330-b29a-e53966c693af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2162773530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2162773530
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.18484471
Short name T831
Test name
Test status
Simulation time 4085502100 ps
CPU time 107.01 seconds
Started Jun 30 05:33:24 PM PDT 24
Finished Jun 30 05:35:12 PM PDT 24
Peak memory 237668 kb
Host smart-0d154350-08dc-4e16-b1f8-e6e072726931
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=18484471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.18484471
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3946434485
Short name T784
Test name
Test status
Simulation time 306487091 ps
CPU time 5.37 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:33:32 PM PDT 24
Peak memory 240572 kb
Host smart-bde37a23-3871-4ee9-ae50-777cb8437927
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3946434485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3946434485
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2011317988
Short name T806
Test name
Test status
Simulation time 246242022 ps
CPU time 9.11 seconds
Started Jun 30 05:33:23 PM PDT 24
Finished Jun 30 05:33:32 PM PDT 24
Peak memory 256072 kb
Host smart-669f2626-6ea2-4ca6-afb4-3ab6b21363ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011317988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2011317988
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1437863170
Short name T725
Test name
Test status
Simulation time 1441660748 ps
CPU time 7.95 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:33:35 PM PDT 24
Peak memory 240552 kb
Host smart-fc843782-5e1b-445d-9768-6375a55548c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1437863170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1437863170
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.693108095
Short name T736
Test name
Test status
Simulation time 21302781 ps
CPU time 1.48 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:27 PM PDT 24
Peak memory 236672 kb
Host smart-ae791e7c-d2e8-41a0-aaeb-8cf3e39a5c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=693108095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.693108095
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1144541856
Short name T816
Test name
Test status
Simulation time 318591706 ps
CPU time 13.42 seconds
Started Jun 30 05:33:30 PM PDT 24
Finished Jun 30 05:33:43 PM PDT 24
Peak memory 245840 kb
Host smart-7e97e928-6328-4c20-b6af-5899ccab810c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1144541856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1144541856
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.989624430
Short name T765
Test name
Test status
Simulation time 159222531 ps
CPU time 6.04 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:33:33 PM PDT 24
Peak memory 254008 kb
Host smart-7740b16c-f634-4831-a5f0-52943f487e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=989624430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.989624430
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3851778134
Short name T717
Test name
Test status
Simulation time 11942897 ps
CPU time 1.53 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 237612 kb
Host smart-7a20ec9c-d99e-44fd-98d8-8d33f38b52a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3851778134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3851778134
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1141473816
Short name T827
Test name
Test status
Simulation time 9124047 ps
CPU time 1.46 seconds
Started Jun 30 05:34:10 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 235604 kb
Host smart-6a6b9812-5ccf-4694-8f15-0a6275ffcb70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1141473816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1141473816
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3675659116
Short name T735
Test name
Test status
Simulation time 10976823 ps
CPU time 1.56 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 236684 kb
Host smart-c6baacbf-9a99-4cbc-a568-0f3e13811f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3675659116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3675659116
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2222680641
Short name T783
Test name
Test status
Simulation time 9113854 ps
CPU time 1.48 seconds
Started Jun 30 05:34:09 PM PDT 24
Finished Jun 30 05:34:11 PM PDT 24
Peak memory 237544 kb
Host smart-a3907a58-e8fa-4d5e-a8ad-138696a86e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2222680641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2222680641
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2171566491
Short name T766
Test name
Test status
Simulation time 7663446 ps
CPU time 1.4 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:09 PM PDT 24
Peak memory 236676 kb
Host smart-d3ae2fec-d303-440f-a0cd-05d337bab1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2171566491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2171566491
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4288075414
Short name T804
Test name
Test status
Simulation time 8382230 ps
CPU time 1.49 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:08 PM PDT 24
Peak memory 237576 kb
Host smart-6edf0346-6cea-42a8-a3a0-af4d8cf0a364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4288075414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4288075414
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.807718010
Short name T782
Test name
Test status
Simulation time 11991690 ps
CPU time 1.45 seconds
Started Jun 30 05:34:09 PM PDT 24
Finished Jun 30 05:34:11 PM PDT 24
Peak memory 236756 kb
Host smart-47e10fc1-a730-4b46-adef-35599d074fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=807718010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.807718010
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3421171954
Short name T761
Test name
Test status
Simulation time 6261280 ps
CPU time 1.38 seconds
Started Jun 30 05:34:10 PM PDT 24
Finished Jun 30 05:34:11 PM PDT 24
Peak memory 235644 kb
Host smart-33bbc552-ee2b-4e4d-8fff-78f909193ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3421171954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3421171954
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2163987394
Short name T826
Test name
Test status
Simulation time 51282234 ps
CPU time 1.46 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 236596 kb
Host smart-a82cdc19-7773-4fc2-84d8-47c78a980d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2163987394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2163987394
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2569395132
Short name T792
Test name
Test status
Simulation time 17818301752 ps
CPU time 331.01 seconds
Started Jun 30 05:33:29 PM PDT 24
Finished Jun 30 05:39:00 PM PDT 24
Peak memory 240480 kb
Host smart-5b7b700c-d521-4a8b-b195-2eede6659171
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2569395132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2569395132
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1288983605
Short name T781
Test name
Test status
Simulation time 3406049705 ps
CPU time 92.08 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:34:59 PM PDT 24
Peak memory 236716 kb
Host smart-f74710f4-01c4-4bc3-ac78-ad32531c356b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1288983605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1288983605
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3792242927
Short name T742
Test name
Test status
Simulation time 600565533 ps
CPU time 10.49 seconds
Started Jun 30 05:33:24 PM PDT 24
Finished Jun 30 05:33:35 PM PDT 24
Peak memory 249152 kb
Host smart-ce1255e8-2a8e-4ccc-b52d-afb71877375b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3792242927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3792242927
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1068484274
Short name T833
Test name
Test status
Simulation time 39757258 ps
CPU time 6.32 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:32 PM PDT 24
Peak memory 248808 kb
Host smart-e1a8cc82-c84e-4a77-a1e9-8018a2a7e116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068484274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1068484274
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1805188874
Short name T752
Test name
Test status
Simulation time 143418755 ps
CPU time 6.49 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:33 PM PDT 24
Peak memory 237600 kb
Host smart-47ebcde2-6be4-408e-951e-c1dfe7b1c6a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1805188874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1805188874
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.706777015
Short name T787
Test name
Test status
Simulation time 16617008 ps
CPU time 1.58 seconds
Started Jun 30 05:33:29 PM PDT 24
Finished Jun 30 05:33:31 PM PDT 24
Peak memory 237552 kb
Host smart-473a031e-13ed-47e6-85ed-c96c0cc5eb83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=706777015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.706777015
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1130936061
Short name T789
Test name
Test status
Simulation time 1447904560 ps
CPU time 47.35 seconds
Started Jun 30 05:33:24 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 245792 kb
Host smart-d0bcd6ae-5cd4-4b74-9046-00a3f6882d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1130936061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1130936061
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2788308012
Short name T132
Test name
Test status
Simulation time 1881781713 ps
CPU time 153.66 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:36:01 PM PDT 24
Peak memory 265632 kb
Host smart-30f88c73-1353-403f-8455-d712b54c17da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2788308012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2788308012
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1078044220
Short name T793
Test name
Test status
Simulation time 481267752 ps
CPU time 17.52 seconds
Started Jun 30 05:33:25 PM PDT 24
Finished Jun 30 05:33:43 PM PDT 24
Peak memory 248812 kb
Host smart-471f0073-5d9c-4258-b7fe-f016672c6990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1078044220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1078044220
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1367634272
Short name T758
Test name
Test status
Simulation time 221449737 ps
CPU time 2.54 seconds
Started Jun 30 05:33:26 PM PDT 24
Finished Jun 30 05:33:29 PM PDT 24
Peak memory 237804 kb
Host smart-cab9f7c6-aaae-4c02-b5de-3ec9c8a77e97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1367634272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1367634272
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1256157163
Short name T722
Test name
Test status
Simulation time 16826284 ps
CPU time 1.9 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 236660 kb
Host smart-4e1cc7f8-9365-4260-ab03-69a5ea96bbba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1256157163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1256157163
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.330789868
Short name T153
Test name
Test status
Simulation time 8437429 ps
CPU time 1.61 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:11 PM PDT 24
Peak memory 237588 kb
Host smart-9473834c-c877-45a5-8d74-760cee8ba831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=330789868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.330789868
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2090071574
Short name T759
Test name
Test status
Simulation time 13083592 ps
CPU time 1.34 seconds
Started Jun 30 05:34:06 PM PDT 24
Finished Jun 30 05:34:08 PM PDT 24
Peak memory 236556 kb
Host smart-41bbfdb1-2514-48b7-9536-a15c18c8dd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2090071574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2090071574
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2709410014
Short name T802
Test name
Test status
Simulation time 20705269 ps
CPU time 1.39 seconds
Started Jun 30 05:34:06 PM PDT 24
Finished Jun 30 05:34:08 PM PDT 24
Peak memory 237612 kb
Host smart-04c23b55-4613-4730-a001-7d1b8f795fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2709410014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2709410014
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3758434274
Short name T338
Test name
Test status
Simulation time 20490941 ps
CPU time 1.43 seconds
Started Jun 30 05:34:07 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 237596 kb
Host smart-e12702b6-0a7c-482a-add1-77e4b6f389a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3758434274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3758434274
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4184222056
Short name T807
Test name
Test status
Simulation time 6790192 ps
CPU time 1.55 seconds
Started Jun 30 05:34:10 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 237624 kb
Host smart-695d67bd-d225-4b64-a614-cc570f2763b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4184222056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4184222056
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.914494411
Short name T809
Test name
Test status
Simulation time 10914269 ps
CPU time 1.67 seconds
Started Jun 30 05:34:08 PM PDT 24
Finished Jun 30 05:34:10 PM PDT 24
Peak memory 237596 kb
Host smart-1dd34c0e-16a9-4ab3-80b6-e43e25148f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=914494411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.914494411
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1729407614
Short name T773
Test name
Test status
Simulation time 17538416 ps
CPU time 1.43 seconds
Started Jun 30 05:34:14 PM PDT 24
Finished Jun 30 05:34:16 PM PDT 24
Peak memory 235616 kb
Host smart-08a3f5ad-f2b4-45f7-a374-48bf0d97ed6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1729407614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1729407614
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.119690118
Short name T741
Test name
Test status
Simulation time 14600203 ps
CPU time 1.54 seconds
Started Jun 30 05:34:16 PM PDT 24
Finished Jun 30 05:34:18 PM PDT 24
Peak memory 236668 kb
Host smart-90058a4a-bf44-4718-8e79-bae7300070a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=119690118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.119690118
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.374741827
Short name T748
Test name
Test status
Simulation time 245533447 ps
CPU time 9.65 seconds
Started Jun 30 05:33:31 PM PDT 24
Finished Jun 30 05:33:42 PM PDT 24
Peak memory 252984 kb
Host smart-b3875556-ac62-4d21-a773-5518451360d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374741827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.374741827
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2512545007
Short name T169
Test name
Test status
Simulation time 186253920 ps
CPU time 4.26 seconds
Started Jun 30 05:33:31 PM PDT 24
Finished Jun 30 05:33:36 PM PDT 24
Peak memory 237552 kb
Host smart-c073fa2d-f055-468a-99e6-74e452470826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2512545007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2512545007
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.726290701
Short name T152
Test name
Test status
Simulation time 6306673 ps
CPU time 1.44 seconds
Started Jun 30 05:33:33 PM PDT 24
Finished Jun 30 05:33:35 PM PDT 24
Peak memory 236668 kb
Host smart-f6e72aa8-1850-4d13-a372-8066535d2625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=726290701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.726290701
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.974765195
Short name T184
Test name
Test status
Simulation time 1249680598 ps
CPU time 25.82 seconds
Started Jun 30 05:33:33 PM PDT 24
Finished Jun 30 05:34:00 PM PDT 24
Peak memory 245824 kb
Host smart-de5abcba-5202-4838-b6ea-c2af641cc682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=974765195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.974765195
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1894567144
Short name T119
Test name
Test status
Simulation time 21000495400 ps
CPU time 367.69 seconds
Started Jun 30 05:33:32 PM PDT 24
Finished Jun 30 05:39:41 PM PDT 24
Peak memory 265400 kb
Host smart-d58ae7ab-27d5-4b40-ab2f-8fcc72928581
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894567144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1894567144
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1537613236
Short name T726
Test name
Test status
Simulation time 531260121 ps
CPU time 10.5 seconds
Started Jun 30 05:33:33 PM PDT 24
Finished Jun 30 05:33:44 PM PDT 24
Peak memory 247996 kb
Host smart-744073df-16e4-4434-93a9-27b8f20292a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1537613236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1537613236
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4055840521
Short name T772
Test name
Test status
Simulation time 55073230 ps
CPU time 9.62 seconds
Started Jun 30 05:33:33 PM PDT 24
Finished Jun 30 05:33:44 PM PDT 24
Peak memory 251116 kb
Host smart-c1c84780-793d-406d-8c98-b45d80e91ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055840521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4055840521
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.177966286
Short name T719
Test name
Test status
Simulation time 33374717 ps
CPU time 5.96 seconds
Started Jun 30 05:33:32 PM PDT 24
Finished Jun 30 05:33:39 PM PDT 24
Peak memory 237604 kb
Host smart-886f3087-f6de-404b-ac27-e7728b3c3ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=177966286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.177966286
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3016834898
Short name T342
Test name
Test status
Simulation time 28566345 ps
CPU time 1.28 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:33:41 PM PDT 24
Peak memory 235668 kb
Host smart-8836e329-5780-4f28-9a56-f04fe1d6200b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3016834898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3016834898
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.101986732
Short name T800
Test name
Test status
Simulation time 362531455 ps
CPU time 26.02 seconds
Started Jun 30 05:33:33 PM PDT 24
Finished Jun 30 05:34:00 PM PDT 24
Peak memory 248752 kb
Host smart-05dfd3ec-d4bd-49b4-9b03-070d57e7bd33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=101986732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.101986732
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1711822733
Short name T733
Test name
Test status
Simulation time 297032977 ps
CPU time 14.62 seconds
Started Jun 30 05:33:38 PM PDT 24
Finished Jun 30 05:33:53 PM PDT 24
Peak memory 248780 kb
Host smart-62d1a0f0-54da-486d-9547-e610c708891e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1711822733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1711822733
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.900259871
Short name T814
Test name
Test status
Simulation time 150432977 ps
CPU time 6.73 seconds
Started Jun 30 05:33:36 PM PDT 24
Finished Jun 30 05:33:43 PM PDT 24
Peak memory 240272 kb
Host smart-43e87f45-4193-45f5-ae1c-0a32d732fde2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900259871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.900259871
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4017000021
Short name T769
Test name
Test status
Simulation time 332026382 ps
CPU time 8.72 seconds
Started Jun 30 05:33:37 PM PDT 24
Finished Jun 30 05:33:46 PM PDT 24
Peak memory 237528 kb
Host smart-3033a152-acd9-4ac1-9ac8-c3d0744c1ca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4017000021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4017000021
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1404341522
Short name T734
Test name
Test status
Simulation time 26381174 ps
CPU time 1.33 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:33:41 PM PDT 24
Peak memory 237576 kb
Host smart-7f23ed51-f89c-495f-b250-667fa95c4339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1404341522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1404341522
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.643196327
Short name T788
Test name
Test status
Simulation time 348507758 ps
CPU time 24.89 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:34:04 PM PDT 24
Peak memory 245796 kb
Host smart-f51ee524-54af-4779-b2e8-b94c0130e9ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=643196327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.643196327
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4090701823
Short name T723
Test name
Test status
Simulation time 110217365 ps
CPU time 8.33 seconds
Started Jun 30 05:33:32 PM PDT 24
Finished Jun 30 05:33:41 PM PDT 24
Peak memory 248776 kb
Host smart-72fdaed0-5a9f-4150-a0e5-3e6fa8feeab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4090701823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4090701823
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3479195647
Short name T345
Test name
Test status
Simulation time 873627173 ps
CPU time 8.48 seconds
Started Jun 30 05:33:42 PM PDT 24
Finished Jun 30 05:33:51 PM PDT 24
Peak memory 252732 kb
Host smart-5c40f98b-679c-46dc-ac4d-28f54ca84ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479195647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3479195647
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.654207725
Short name T721
Test name
Test status
Simulation time 20488834 ps
CPU time 3.64 seconds
Started Jun 30 05:33:37 PM PDT 24
Finished Jun 30 05:33:41 PM PDT 24
Peak memory 237772 kb
Host smart-f0b80cba-0693-44fc-8ce6-78c7d170e48a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=654207725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.654207725
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.304160278
Short name T824
Test name
Test status
Simulation time 8447100 ps
CPU time 1.45 seconds
Started Jun 30 05:33:38 PM PDT 24
Finished Jun 30 05:33:40 PM PDT 24
Peak memory 236572 kb
Host smart-b7e3218f-a229-4fe6-9e6f-55dd939d88b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=304160278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.304160278
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.669058112
Short name T797
Test name
Test status
Simulation time 335754927 ps
CPU time 21.72 seconds
Started Jun 30 05:33:40 PM PDT 24
Finished Jun 30 05:34:02 PM PDT 24
Peak memory 240564 kb
Host smart-0181e5b2-98e7-4354-8157-396f302df1d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=669058112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.669058112
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3814922517
Short name T130
Test name
Test status
Simulation time 2480698692 ps
CPU time 185.06 seconds
Started Jun 30 05:33:38 PM PDT 24
Finished Jun 30 05:36:44 PM PDT 24
Peak memory 265448 kb
Host smart-f4007da3-1151-4bf8-b8d0-747f19107a3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3814922517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3814922517
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2756299681
Short name T146
Test name
Test status
Simulation time 4796652075 ps
CPU time 392.79 seconds
Started Jun 30 05:33:42 PM PDT 24
Finished Jun 30 05:40:15 PM PDT 24
Peak memory 265508 kb
Host smart-e9199c8a-1b94-4a7f-9ac2-0aba6870d400
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756299681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2756299681
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1780538778
Short name T710
Test name
Test status
Simulation time 76993191 ps
CPU time 8.65 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:33:48 PM PDT 24
Peak memory 253344 kb
Host smart-3b7b50e6-8226-4c9f-b380-26dde6519d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1780538778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1780538778
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3323785715
Short name T799
Test name
Test status
Simulation time 162334866 ps
CPU time 25.13 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:34:05 PM PDT 24
Peak memory 240492 kb
Host smart-14a53765-d90f-48fd-be6d-7c90499b2f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3323785715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3323785715
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2314942080
Short name T775
Test name
Test status
Simulation time 1296255621 ps
CPU time 10.61 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:33:50 PM PDT 24
Peak memory 238308 kb
Host smart-b83d415a-ca3b-4509-8b33-9a8f101c8c1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314942080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2314942080
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3437179183
Short name T182
Test name
Test status
Simulation time 37038678 ps
CPU time 5.46 seconds
Started Jun 30 05:33:38 PM PDT 24
Finished Jun 30 05:33:44 PM PDT 24
Peak memory 240568 kb
Host smart-a07bbc82-55fc-4740-b82e-df21a57840f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3437179183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3437179183
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4145027473
Short name T780
Test name
Test status
Simulation time 7538579 ps
CPU time 1.51 seconds
Started Jun 30 05:33:42 PM PDT 24
Finished Jun 30 05:33:44 PM PDT 24
Peak memory 237532 kb
Host smart-6f9e1fee-461d-4108-9d3b-4e39dd4b83e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145027473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4145027473
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1458481691
Short name T746
Test name
Test status
Simulation time 636669652 ps
CPU time 46.66 seconds
Started Jun 30 05:33:37 PM PDT 24
Finished Jun 30 05:34:24 PM PDT 24
Peak memory 245784 kb
Host smart-0f97b3f2-a418-4d7d-a2c4-17b6771593ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1458481691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1458481691
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2672034403
Short name T112
Test name
Test status
Simulation time 51904692247 ps
CPU time 210.48 seconds
Started Jun 30 05:33:38 PM PDT 24
Finished Jun 30 05:37:09 PM PDT 24
Peak memory 267316 kb
Host smart-2a4aa8fa-9e04-4a33-942a-db838a450941
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2672034403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2672034403
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.824027628
Short name T127
Test name
Test status
Simulation time 8422651510 ps
CPU time 602.92 seconds
Started Jun 30 05:33:39 PM PDT 24
Finished Jun 30 05:43:43 PM PDT 24
Peak memory 265548 kb
Host smart-47e81239-cf7b-4983-baad-0fdbb9a1e6b9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824027628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.824027628
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.260995586
Short name T829
Test name
Test status
Simulation time 47854252 ps
CPU time 7.4 seconds
Started Jun 30 05:33:41 PM PDT 24
Finished Jun 30 05:33:49 PM PDT 24
Peak memory 247984 kb
Host smart-0830dfbe-b358-47c1-b673-5a814d4a4198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=260995586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.260995586
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3354873416
Short name T72
Test name
Test status
Simulation time 76253232846 ps
CPU time 2397.21 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:59:04 PM PDT 24
Peak memory 289196 kb
Host smart-a5fab7ec-a3ae-438b-8c8e-e3d208434eed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354873416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3354873416
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2356313747
Short name T383
Test name
Test status
Simulation time 359149000 ps
CPU time 17.33 seconds
Started Jun 30 05:18:58 PM PDT 24
Finished Jun 30 05:19:16 PM PDT 24
Peak memory 249188 kb
Host smart-abf2688c-7af6-45d5-8074-a577f63e720e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2356313747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2356313747
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.688089078
Short name T503
Test name
Test status
Simulation time 2317471765 ps
CPU time 96.32 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:20:43 PM PDT 24
Peak memory 257016 kb
Host smart-31ba6562-eb97-4cba-a5b7-f7f8deb09b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68808
9078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.688089078
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.531222016
Short name T633
Test name
Test status
Simulation time 226404922 ps
CPU time 12.91 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:20 PM PDT 24
Peak memory 249296 kb
Host smart-609f2234-92f0-4bd0-b5c2-5ecbed826ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53122
2016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.531222016
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.143413685
Short name T329
Test name
Test status
Simulation time 105711724609 ps
CPU time 1281.79 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:40:32 PM PDT 24
Peak memory 273864 kb
Host smart-1ea89086-9699-4ddd-9e71-40ffdf278cda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143413685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.143413685
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3049659768
Short name T521
Test name
Test status
Simulation time 284915092620 ps
CPU time 1381.65 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:42:08 PM PDT 24
Peak memory 288388 kb
Host smart-abd001dc-7d93-40bb-afa8-d83e98091a40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049659768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3049659768
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3563345872
Short name T369
Test name
Test status
Simulation time 1503208791 ps
CPU time 21.6 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:19:24 PM PDT 24
Peak memory 256780 kb
Host smart-5bec8620-c61f-411e-8739-88c150623bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
45872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3563345872
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4162670534
Short name T441
Test name
Test status
Simulation time 1235260224 ps
CPU time 40.11 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:45 PM PDT 24
Peak memory 257256 kb
Host smart-628bfb36-3cd5-43a1-8581-7025ea6233d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41626
70534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4162670534
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1562732453
Short name T42
Test name
Test status
Simulation time 347325377 ps
CPU time 22.19 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:19:32 PM PDT 24
Peak memory 271512 kb
Host smart-62a75b58-be27-4963-a899-11467b423951
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1562732453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1562732453
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.348632966
Short name T592
Test name
Test status
Simulation time 260158273 ps
CPU time 9.65 seconds
Started Jun 30 05:18:56 PM PDT 24
Finished Jun 30 05:19:06 PM PDT 24
Peak memory 249176 kb
Host smart-8e124315-b7c6-4e2f-9e43-2cc4a76b8762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863
2966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.348632966
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3703928073
Short name T440
Test name
Test status
Simulation time 912172218 ps
CPU time 14.03 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:19:24 PM PDT 24
Peak memory 253980 kb
Host smart-f75fa410-b10e-4f59-b58e-5a130b9337dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37039
28073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3703928073
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.384927799
Short name T361
Test name
Test status
Simulation time 9309890333 ps
CPU time 1067.95 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:36:58 PM PDT 24
Peak memory 273676 kb
Host smart-b8726308-1334-40d3-b073-075142f2e0d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384927799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.384927799
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1727307438
Short name T226
Test name
Test status
Simulation time 6452560260 ps
CPU time 28.53 seconds
Started Jun 30 05:18:59 PM PDT 24
Finished Jun 30 05:19:29 PM PDT 24
Peak memory 249320 kb
Host smart-86713bda-db57-4ff1-975a-62eec52e17ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1727307438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1727307438
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.765980284
Short name T355
Test name
Test status
Simulation time 21270252812 ps
CPU time 156.91 seconds
Started Jun 30 05:18:54 PM PDT 24
Finished Jun 30 05:21:32 PM PDT 24
Peak memory 257036 kb
Host smart-36778a85-1ba1-40e7-8ffc-5f0a6bb302e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76598
0284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.765980284
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2980715412
Short name T641
Test name
Test status
Simulation time 509352199 ps
CPU time 31.92 seconds
Started Jun 30 05:18:56 PM PDT 24
Finished Jun 30 05:19:29 PM PDT 24
Peak memory 249172 kb
Host smart-46cb2bba-43a7-4b0e-9650-41dc98b5f5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807
15412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2980715412
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4209380445
Short name T224
Test name
Test status
Simulation time 19458036932 ps
CPU time 899.58 seconds
Started Jun 30 05:18:56 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 273844 kb
Host smart-57d6f80e-41e2-4e8c-85fb-07fae469d562
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209380445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4209380445
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4118761518
Short name T399
Test name
Test status
Simulation time 30770190560 ps
CPU time 817.19 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:32:48 PM PDT 24
Peak memory 273888 kb
Host smart-1532a3d1-ef82-4683-abe1-6b05a170b033
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118761518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4118761518
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1410884450
Short name T697
Test name
Test status
Simulation time 30183458298 ps
CPU time 307.09 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:24:09 PM PDT 24
Peak memory 256044 kb
Host smart-db9f580d-de6a-4a37-96a7-74e4ae197567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410884450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1410884450
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.181388967
Short name T101
Test name
Test status
Simulation time 2088811596 ps
CPU time 63.15 seconds
Started Jun 30 05:19:04 PM PDT 24
Finished Jun 30 05:20:12 PM PDT 24
Peak memory 248692 kb
Host smart-987b95f7-641d-474d-a1b8-1bec17de8d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18138
8967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.181388967
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4020547837
Short name T481
Test name
Test status
Simulation time 3771490346 ps
CPU time 45.44 seconds
Started Jun 30 05:19:04 PM PDT 24
Finished Jun 30 05:19:54 PM PDT 24
Peak memory 248660 kb
Host smart-a309b761-8253-42c3-94d7-49ca059a0811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40205
47837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4020547837
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1111039312
Short name T678
Test name
Test status
Simulation time 33502871270 ps
CPU time 709.76 seconds
Started Jun 30 05:19:15 PM PDT 24
Finished Jun 30 05:31:05 PM PDT 24
Peak memory 273452 kb
Host smart-49d6fd49-33a1-4c1f-aca7-eb803aa0034e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111039312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1111039312
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1598017897
Short name T457
Test name
Test status
Simulation time 2542062630 ps
CPU time 17.65 seconds
Started Jun 30 05:19:13 PM PDT 24
Finished Jun 30 05:19:31 PM PDT 24
Peak memory 249332 kb
Host smart-22a4f7d7-38e2-4030-bad8-e2c6da7362e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1598017897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1598017897
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2810745376
Short name T686
Test name
Test status
Simulation time 363060499 ps
CPU time 20.85 seconds
Started Jun 30 05:19:32 PM PDT 24
Finished Jun 30 05:19:53 PM PDT 24
Peak memory 257424 kb
Host smart-c54018b2-08fe-45a4-9c60-8a9510ced48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28107
45376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2810745376
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2107227488
Short name T698
Test name
Test status
Simulation time 1525480148 ps
CPU time 47.24 seconds
Started Jun 30 05:19:17 PM PDT 24
Finished Jun 30 05:20:04 PM PDT 24
Peak memory 249300 kb
Host smart-9647c48f-639a-4868-8b40-f28ef1daad5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21072
27488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2107227488
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3153167761
Short name T665
Test name
Test status
Simulation time 9252756281 ps
CPU time 766.9 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:32:00 PM PDT 24
Peak memory 273976 kb
Host smart-43e345ac-128f-4c32-aa3b-2b8a9eef9c8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153167761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3153167761
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3456994360
Short name T85
Test name
Test status
Simulation time 1632087397 ps
CPU time 42.99 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:19:56 PM PDT 24
Peak memory 249260 kb
Host smart-bc3c9d1d-236a-43f3-9597-8d2737230ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456994360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3456994360
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1783557066
Short name T567
Test name
Test status
Simulation time 240008657 ps
CPU time 11.17 seconds
Started Jun 30 05:19:17 PM PDT 24
Finished Jun 30 05:19:28 PM PDT 24
Peak memory 249296 kb
Host smart-c4156ec3-bd65-44ee-9cf9-872480263178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17835
57066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1783557066
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2202876821
Short name T466
Test name
Test status
Simulation time 586888494 ps
CPU time 27.4 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:19:40 PM PDT 24
Peak memory 249260 kb
Host smart-00422743-2f4b-43e0-8630-4d5e4c05bb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028
76821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2202876821
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.140876344
Short name T396
Test name
Test status
Simulation time 1115573010 ps
CPU time 36.57 seconds
Started Jun 30 05:19:11 PM PDT 24
Finished Jun 30 05:19:49 PM PDT 24
Peak memory 249116 kb
Host smart-cf464789-2038-4d47-ac89-325c59b67dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
6344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.140876344
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3936352683
Short name T371
Test name
Test status
Simulation time 1503080533 ps
CPU time 50.39 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:20:02 PM PDT 24
Peak memory 257392 kb
Host smart-7e0dde88-f94e-4412-b1d1-33cc9fe922e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39363
52683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3936352683
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.326620209
Short name T195
Test name
Test status
Simulation time 23489177 ps
CPU time 2.51 seconds
Started Jun 30 05:19:19 PM PDT 24
Finished Jun 30 05:19:22 PM PDT 24
Peak memory 249516 kb
Host smart-13904dd6-d167-4efd-973d-36032d25d788
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=326620209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.326620209
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2916715361
Short name T504
Test name
Test status
Simulation time 10657964170 ps
CPU time 1518.1 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:44:54 PM PDT 24
Peak memory 290096 kb
Host smart-d147a7c9-c5da-4b58-a044-bd38e435de10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916715361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2916715361
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.341849254
Short name T384
Test name
Test status
Simulation time 797813173 ps
CPU time 39.17 seconds
Started Jun 30 05:19:31 PM PDT 24
Finished Jun 30 05:20:11 PM PDT 24
Peak memory 249308 kb
Host smart-79304f13-fdeb-4a3d-bf1e-f45e91de6c83
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=341849254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.341849254
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.569623251
Short name T354
Test name
Test status
Simulation time 470248509 ps
CPU time 23.83 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:20:02 PM PDT 24
Peak memory 256284 kb
Host smart-279e35f4-b234-4136-aa16-854b6fa40092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56962
3251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.569623251
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2163203558
Short name T433
Test name
Test status
Simulation time 137040571 ps
CPU time 8.97 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:19:21 PM PDT 24
Peak memory 249216 kb
Host smart-4df0e211-3086-4c4e-8010-39e248329e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
03558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2163203558
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1796483010
Short name T322
Test name
Test status
Simulation time 300929432687 ps
CPU time 2698.72 seconds
Started Jun 30 05:19:30 PM PDT 24
Finished Jun 30 06:04:29 PM PDT 24
Peak memory 286536 kb
Host smart-e0b535ae-7e30-47d5-8d55-a8cb711fdc70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796483010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1796483010
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3807053019
Short name T489
Test name
Test status
Simulation time 26070728602 ps
CPU time 1604.89 seconds
Started Jun 30 05:19:24 PM PDT 24
Finished Jun 30 05:46:09 PM PDT 24
Peak memory 273976 kb
Host smart-318d9598-d7c6-463c-ad14-d04c81b0adf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807053019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3807053019
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1274626381
Short name T309
Test name
Test status
Simulation time 3126924127 ps
CPU time 132.7 seconds
Started Jun 30 05:19:22 PM PDT 24
Finished Jun 30 05:21:35 PM PDT 24
Peak memory 256416 kb
Host smart-284afbe0-2ff8-4533-b3a8-23bff4368fd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274626381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1274626381
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3049186137
Short name T624
Test name
Test status
Simulation time 3941182714 ps
CPU time 55.9 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:20:08 PM PDT 24
Peak memory 256512 kb
Host smart-181cc1d4-87af-4b77-9643-a9c7738a7b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30491
86137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3049186137
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4185938213
Short name T411
Test name
Test status
Simulation time 615169668 ps
CPU time 44.02 seconds
Started Jun 30 05:19:21 PM PDT 24
Finished Jun 30 05:20:05 PM PDT 24
Peak memory 249284 kb
Host smart-2a2811f3-b28a-475c-b110-4329f6ac6e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41859
38213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4185938213
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.47550023
Short name T14
Test name
Test status
Simulation time 860470587 ps
CPU time 48.01 seconds
Started Jun 30 05:19:20 PM PDT 24
Finished Jun 30 05:20:09 PM PDT 24
Peak memory 256108 kb
Host smart-44d2ac14-d4f8-47c2-a032-e924e50c5f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47550
023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.47550023
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1926659442
Short name T662
Test name
Test status
Simulation time 1973706062 ps
CPU time 33.88 seconds
Started Jun 30 05:19:24 PM PDT 24
Finished Jun 30 05:19:58 PM PDT 24
Peak memory 257448 kb
Host smart-99a53eb4-0da2-4212-85d2-80127304b80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19266
59442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1926659442
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.4110923315
Short name T566
Test name
Test status
Simulation time 60656673961 ps
CPU time 1685.42 seconds
Started Jun 30 05:19:20 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 282132 kb
Host smart-99ad013c-eb94-43f0-bb68-ea7d2dd71a5e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110923315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.4110923315
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1481792925
Short name T43
Test name
Test status
Simulation time 16077897 ps
CPU time 2.65 seconds
Started Jun 30 05:19:21 PM PDT 24
Finished Jun 30 05:19:24 PM PDT 24
Peak memory 249560 kb
Host smart-a05a45f7-7017-4569-b387-46c6c98ce9f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1481792925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1481792925
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.147472387
Short name T546
Test name
Test status
Simulation time 161606957045 ps
CPU time 2382.96 seconds
Started Jun 30 05:19:20 PM PDT 24
Finished Jun 30 05:59:04 PM PDT 24
Peak memory 283180 kb
Host smart-2c7c5d50-e787-406b-8bfd-74bb99c01960
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147472387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.147472387
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3602568410
Short name T476
Test name
Test status
Simulation time 149678038 ps
CPU time 8.95 seconds
Started Jun 30 05:19:31 PM PDT 24
Finished Jun 30 05:19:40 PM PDT 24
Peak memory 249216 kb
Host smart-9b27903e-1f84-4d50-b363-f272361c20ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3602568410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3602568410
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2449769677
Short name T608
Test name
Test status
Simulation time 1345452427 ps
CPU time 72.75 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:20:49 PM PDT 24
Peak memory 257008 kb
Host smart-085ffc99-ab6e-44b9-b39e-38d9405a027b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
69677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2449769677
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3091208553
Short name T216
Test name
Test status
Simulation time 304410606 ps
CPU time 18.04 seconds
Started Jun 30 05:19:34 PM PDT 24
Finished Jun 30 05:19:52 PM PDT 24
Peak memory 256060 kb
Host smart-7492f912-1bfa-4be2-9b7b-dc6a0e89d566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30912
08553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3091208553
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3383514022
Short name T17
Test name
Test status
Simulation time 320522766565 ps
CPU time 1159.97 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:38:58 PM PDT 24
Peak memory 273012 kb
Host smart-927bffab-12e4-44a8-87b7-9586e5a5d3a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383514022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3383514022
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3948799710
Short name T18
Test name
Test status
Simulation time 41328104896 ps
CPU time 1071.71 seconds
Started Jun 30 05:19:35 PM PDT 24
Finished Jun 30 05:37:27 PM PDT 24
Peak memory 284536 kb
Host smart-de87caf1-16e9-492c-ab27-ac07acd3d087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948799710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3948799710
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2532837215
Short name T558
Test name
Test status
Simulation time 10327298867 ps
CPU time 116.57 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:21:35 PM PDT 24
Peak memory 249284 kb
Host smart-4188beb5-566e-479c-b4ff-7f0124e8700b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532837215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2532837215
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2248404435
Short name T531
Test name
Test status
Simulation time 4494482035 ps
CPU time 67.07 seconds
Started Jun 30 05:19:18 PM PDT 24
Finished Jun 30 05:20:26 PM PDT 24
Peak memory 257056 kb
Host smart-a7ec5620-4f88-4e17-938e-00875dbc82ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22484
04435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2248404435
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4210397923
Short name T681
Test name
Test status
Simulation time 249721278 ps
CPU time 27.74 seconds
Started Jun 30 05:19:23 PM PDT 24
Finished Jun 30 05:19:51 PM PDT 24
Peak memory 256960 kb
Host smart-f03a03f5-3bdc-4a92-8932-a1fd8d37d271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42103
97923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4210397923
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1441863930
Short name T48
Test name
Test status
Simulation time 239921035 ps
CPU time 16.85 seconds
Started Jun 30 05:19:24 PM PDT 24
Finished Jun 30 05:19:41 PM PDT 24
Peak memory 256048 kb
Host smart-2a1eed18-4349-474f-b611-efc68dea4c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14418
63930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1441863930
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1673433056
Short name T526
Test name
Test status
Simulation time 1051718686 ps
CPU time 16.66 seconds
Started Jun 30 05:19:22 PM PDT 24
Finished Jun 30 05:19:39 PM PDT 24
Peak memory 257436 kb
Host smart-d2f2a809-b424-497f-bd03-3645be1c4cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
33056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1673433056
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3872335539
Short name T207
Test name
Test status
Simulation time 14741807 ps
CPU time 2.27 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:19:39 PM PDT 24
Peak memory 249544 kb
Host smart-90a22eba-3194-45ff-b375-a01bc95e8af2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3872335539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3872335539
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3889819588
Short name T629
Test name
Test status
Simulation time 34812664735 ps
CPU time 2093.47 seconds
Started Jun 30 05:19:31 PM PDT 24
Finished Jun 30 05:54:25 PM PDT 24
Peak memory 273720 kb
Host smart-f38ec663-35fa-4472-8f95-9620ae3df6d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889819588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3889819588
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2103048074
Short name T387
Test name
Test status
Simulation time 379884002 ps
CPU time 12.24 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:19:52 PM PDT 24
Peak memory 249184 kb
Host smart-bb3342e6-015a-43e8-b9a4-e0c1f3e61318
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2103048074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2103048074
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1376304174
Short name T359
Test name
Test status
Simulation time 9141303764 ps
CPU time 97.09 seconds
Started Jun 30 05:19:24 PM PDT 24
Finished Jun 30 05:21:02 PM PDT 24
Peak memory 257576 kb
Host smart-2fd830a6-941e-405f-a2b4-33863cd9c57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13763
04174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1376304174
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.499621800
Short name T692
Test name
Test status
Simulation time 263803770 ps
CPU time 14.67 seconds
Started Jun 30 05:19:18 PM PDT 24
Finished Jun 30 05:19:33 PM PDT 24
Peak memory 248844 kb
Host smart-067f26ba-3c43-45a7-8e21-6e93fe3aad3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49962
1800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.499621800
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1837957747
Short name T304
Test name
Test status
Simulation time 12195590110 ps
CPU time 1036.8 seconds
Started Jun 30 05:19:18 PM PDT 24
Finished Jun 30 05:36:36 PM PDT 24
Peak memory 289360 kb
Host smart-cb7a393b-a88a-403c-a54d-c6363d8c32e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837957747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1837957747
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2545457520
Short name T533
Test name
Test status
Simulation time 65306055100 ps
CPU time 1611.95 seconds
Started Jun 30 05:19:24 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 289444 kb
Host smart-4d1f8659-27ad-4718-b3cc-bd51cf8c991c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545457520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2545457520
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2995364739
Short name T314
Test name
Test status
Simulation time 190534411116 ps
CPU time 674.73 seconds
Started Jun 30 05:19:21 PM PDT 24
Finished Jun 30 05:30:37 PM PDT 24
Peak memory 249364 kb
Host smart-2d8e376b-c595-4bf5-8798-b558f3c196d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995364739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2995364739
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3809350514
Short name T560
Test name
Test status
Simulation time 286554226 ps
CPU time 27.5 seconds
Started Jun 30 05:19:22 PM PDT 24
Finished Jun 30 05:19:50 PM PDT 24
Peak memory 256776 kb
Host smart-f3eaf54d-251e-42ea-9ff4-c9957d99c3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38093
50514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3809350514
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2608163768
Short name T643
Test name
Test status
Simulation time 3380394661 ps
CPU time 56.55 seconds
Started Jun 30 05:19:32 PM PDT 24
Finished Jun 30 05:20:29 PM PDT 24
Peak memory 249216 kb
Host smart-d5e2eb07-fa45-470e-aa4c-332ea8c4d0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26081
63768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2608163768
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.266399240
Short name T548
Test name
Test status
Simulation time 184894420 ps
CPU time 12.98 seconds
Started Jun 30 05:19:18 PM PDT 24
Finished Jun 30 05:19:31 PM PDT 24
Peak memory 249284 kb
Host smart-021f5350-9438-495f-bfa9-8f382a73f203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639
9240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.266399240
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.818862032
Short name T483
Test name
Test status
Simulation time 191065146965 ps
CPU time 4879.28 seconds
Started Jun 30 05:19:33 PM PDT 24
Finished Jun 30 06:40:53 PM PDT 24
Peak memory 330952 kb
Host smart-89d465c0-0c78-4c55-a1a1-2da5cb68023a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818862032 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.818862032
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2270007825
Short name T208
Test name
Test status
Simulation time 22976901 ps
CPU time 2.81 seconds
Started Jun 30 05:19:27 PM PDT 24
Finished Jun 30 05:19:30 PM PDT 24
Peak memory 249540 kb
Host smart-af8f932e-a297-4a85-ab29-68fdc9fd6b90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2270007825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2270007825
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3656646865
Short name T424
Test name
Test status
Simulation time 135946836116 ps
CPU time 1507.4 seconds
Started Jun 30 05:19:33 PM PDT 24
Finished Jun 30 05:44:41 PM PDT 24
Peak memory 273980 kb
Host smart-b8b9516a-8e05-4e84-ab2d-16f08a11b0ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656646865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3656646865
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.858024020
Short name T372
Test name
Test status
Simulation time 361633356 ps
CPU time 10.96 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:19:48 PM PDT 24
Peak memory 249292 kb
Host smart-d9d1650c-82da-4a93-8e6a-baf816a949e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=858024020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.858024020
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.341837110
Short name T601
Test name
Test status
Simulation time 7631575707 ps
CPU time 154.24 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:22:13 PM PDT 24
Peak memory 256828 kb
Host smart-46de0769-ee80-40e5-9791-69113cd460f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
7110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.341837110
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2731546233
Short name T221
Test name
Test status
Simulation time 138922161 ps
CPU time 10.86 seconds
Started Jun 30 05:19:35 PM PDT 24
Finished Jun 30 05:19:46 PM PDT 24
Peak memory 255472 kb
Host smart-0677aea7-58f6-4e2d-bfc3-a239259e443b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
46233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2731546233
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3817612927
Short name T220
Test name
Test status
Simulation time 56834859474 ps
CPU time 1544.82 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:45:22 PM PDT 24
Peak memory 273280 kb
Host smart-b836f21b-d4a7-426c-a365-829c31ffba18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817612927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3817612927
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.904693777
Short name T110
Test name
Test status
Simulation time 31823223607 ps
CPU time 1702.05 seconds
Started Jun 30 05:19:35 PM PDT 24
Finished Jun 30 05:47:58 PM PDT 24
Peak memory 273844 kb
Host smart-2bfd83ba-6b94-45e9-ad8d-a6381f0d9087
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904693777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.904693777
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2800793393
Short name T420
Test name
Test status
Simulation time 1218477600 ps
CPU time 45.54 seconds
Started Jun 30 05:19:29 PM PDT 24
Finished Jun 30 05:20:15 PM PDT 24
Peak memory 256740 kb
Host smart-acffe4dd-4e3e-49ec-977d-442acb6dfb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28007
93393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2800793393
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3942953538
Short name T367
Test name
Test status
Simulation time 410904325 ps
CPU time 6.53 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:19:44 PM PDT 24
Peak memory 249292 kb
Host smart-ed79e0ae-ef80-49b7-893c-5a5b1fceae6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39429
53538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3942953538
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.820024265
Short name T248
Test name
Test status
Simulation time 392633430 ps
CPU time 24.31 seconds
Started Jun 30 05:19:28 PM PDT 24
Finished Jun 30 05:19:53 PM PDT 24
Peak memory 249188 kb
Host smart-068f306d-426e-4008-841d-9d275596ae0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82002
4265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.820024265
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.507560095
Short name T708
Test name
Test status
Simulation time 3581136387 ps
CPU time 56.09 seconds
Started Jun 30 05:19:25 PM PDT 24
Finished Jun 30 05:20:22 PM PDT 24
Peak memory 257552 kb
Host smart-6262e3f9-690c-44d7-b35a-4f99f2f51401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50756
0095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.507560095
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.603205808
Short name T51
Test name
Test status
Simulation time 14698201122 ps
CPU time 199.44 seconds
Started Jun 30 05:19:39 PM PDT 24
Finished Jun 30 05:22:59 PM PDT 24
Peak memory 257520 kb
Host smart-e85102de-62f5-468f-98bd-084b8691c515
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603205808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.603205808
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2418662463
Short name T62
Test name
Test status
Simulation time 62860842454 ps
CPU time 6156.17 seconds
Started Jun 30 05:19:26 PM PDT 24
Finished Jun 30 07:02:03 PM PDT 24
Peak memory 355568 kb
Host smart-090381db-971a-4b9f-af8c-a790c81bd29e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418662463 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2418662463
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1943355325
Short name T490
Test name
Test status
Simulation time 1307578718 ps
CPU time 16.51 seconds
Started Jun 30 05:19:41 PM PDT 24
Finished Jun 30 05:19:58 PM PDT 24
Peak memory 249224 kb
Host smart-5ad7fd78-e204-4d12-98b0-c88aaf1cb47f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1943355325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1943355325
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1270126448
Short name T468
Test name
Test status
Simulation time 2361473187 ps
CPU time 43.81 seconds
Started Jun 30 05:19:27 PM PDT 24
Finished Jun 30 05:20:11 PM PDT 24
Peak memory 257468 kb
Host smart-926691a7-ba26-48bf-bae5-37d4af1b9400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12701
26448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1270126448
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.66711516
Short name T527
Test name
Test status
Simulation time 137549439 ps
CPU time 5.56 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:19:45 PM PDT 24
Peak memory 248888 kb
Host smart-e909ad1d-7b3b-4de3-a243-820a1f183658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66711
516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.66711516
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2621836909
Short name T477
Test name
Test status
Simulation time 25370881753 ps
CPU time 1750.9 seconds
Started Jun 30 05:19:26 PM PDT 24
Finished Jun 30 05:48:38 PM PDT 24
Peak memory 283916 kb
Host smart-cd93da72-ae79-4018-824f-ef1db6abb5b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621836909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2621836909
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.889614193
Short name T313
Test name
Test status
Simulation time 184965481398 ps
CPU time 585.94 seconds
Started Jun 30 05:19:28 PM PDT 24
Finished Jun 30 05:29:15 PM PDT 24
Peak memory 249336 kb
Host smart-acec88eb-20a1-4389-b29c-3119b767035c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889614193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.889614193
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1367082512
Short name T401
Test name
Test status
Simulation time 4063837795 ps
CPU time 69.94 seconds
Started Jun 30 05:19:35 PM PDT 24
Finished Jun 30 05:20:45 PM PDT 24
Peak memory 257740 kb
Host smart-723e38ea-ec09-4e75-98a1-35488c78c17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13670
82512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1367082512
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3327662310
Short name T53
Test name
Test status
Simulation time 296776160 ps
CPU time 11.58 seconds
Started Jun 30 05:19:40 PM PDT 24
Finished Jun 30 05:19:52 PM PDT 24
Peak memory 253796 kb
Host smart-5cba4b11-53fd-4950-9a95-a2e69627edbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33276
62310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3327662310
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3735538360
Short name T191
Test name
Test status
Simulation time 708535007 ps
CPU time 53.66 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:20:32 PM PDT 24
Peak memory 256904 kb
Host smart-008f8a87-c2dd-4b83-8ee3-21f5dae562cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37355
38360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3735538360
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2507509576
Short name T598
Test name
Test status
Simulation time 16710294 ps
CPU time 3.18 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:19:41 PM PDT 24
Peak memory 249216 kb
Host smart-9a878084-7c89-4847-960f-1699e5fbefbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075
09576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2507509576
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.873372648
Short name T422
Test name
Test status
Simulation time 33227622023 ps
CPU time 1913.82 seconds
Started Jun 30 05:19:27 PM PDT 24
Finished Jun 30 05:51:22 PM PDT 24
Peak memory 289788 kb
Host smart-026541de-6670-4e25-ab76-36711716ddc5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873372648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.873372648
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1285305542
Short name T197
Test name
Test status
Simulation time 44594417 ps
CPU time 4.27 seconds
Started Jun 30 05:19:35 PM PDT 24
Finished Jun 30 05:19:39 PM PDT 24
Peak memory 249540 kb
Host smart-e853dc93-df43-44f9-a2e8-6cce7e779233
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1285305542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1285305542
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.438666740
Short name T647
Test name
Test status
Simulation time 38569824685 ps
CPU time 1412.52 seconds
Started Jun 30 05:19:39 PM PDT 24
Finished Jun 30 05:43:13 PM PDT 24
Peak memory 289772 kb
Host smart-b3937d76-25b1-4a4a-aead-f64d2996da8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438666740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.438666740
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1231427243
Short name T496
Test name
Test status
Simulation time 307597931 ps
CPU time 15.88 seconds
Started Jun 30 05:19:45 PM PDT 24
Finished Jun 30 05:20:02 PM PDT 24
Peak memory 249184 kb
Host smart-73188e7c-826c-4e84-9553-981f6aa45d16
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1231427243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1231427243
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3513389836
Short name T104
Test name
Test status
Simulation time 14246587705 ps
CPU time 229.41 seconds
Started Jun 30 05:19:34 PM PDT 24
Finished Jun 30 05:23:24 PM PDT 24
Peak memory 257760 kb
Host smart-fe27ac91-5023-46ec-beb3-72d75e86989e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35133
89836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3513389836
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2093242635
Short name T518
Test name
Test status
Simulation time 132533046 ps
CPU time 10.03 seconds
Started Jun 30 05:19:45 PM PDT 24
Finished Jun 30 05:19:55 PM PDT 24
Peak memory 257340 kb
Host smart-1a90032d-67fe-447f-bc4a-ae88a20b023d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20932
42635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2093242635
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1993919989
Short name T320
Test name
Test status
Simulation time 38757009813 ps
CPU time 2273.22 seconds
Started Jun 30 05:19:34 PM PDT 24
Finished Jun 30 05:57:28 PM PDT 24
Peak memory 289912 kb
Host smart-60cff18c-8f58-443b-bedf-de1e48ae27c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993919989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1993919989
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.440180268
Short name T19
Test name
Test status
Simulation time 43134362031 ps
CPU time 2697.51 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 06:04:34 PM PDT 24
Peak memory 290132 kb
Host smart-7ae84e84-5fcc-44ad-9b53-cb49d7b392a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440180268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.440180268
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1783210874
Short name T638
Test name
Test status
Simulation time 21316262023 ps
CPU time 217.39 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:23:16 PM PDT 24
Peak memory 249344 kb
Host smart-69eaefb1-8eb4-4ae6-a25a-cd514dd41c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783210874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1783210874
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1994989405
Short name T55
Test name
Test status
Simulation time 465758872 ps
CPU time 21.54 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 05:20:08 PM PDT 24
Peak memory 257368 kb
Host smart-982ec3df-ae6c-48d6-9dc7-7803da8df5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19949
89405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1994989405
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2062212069
Short name T423
Test name
Test status
Simulation time 175324729 ps
CPU time 7.3 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:19:56 PM PDT 24
Peak memory 248804 kb
Host smart-fd2a474f-5e65-4638-9982-8d89a184fcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
12069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2062212069
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2009442400
Short name T238
Test name
Test status
Simulation time 268917783 ps
CPU time 15.85 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:19:58 PM PDT 24
Peak memory 256972 kb
Host smart-d9ba393a-65b5-418b-b4a8-4a8717edb9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20094
42400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2009442400
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.428805067
Short name T511
Test name
Test status
Simulation time 198775931 ps
CPU time 11.31 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:19:54 PM PDT 24
Peak memory 257132 kb
Host smart-d2e13a2f-efaa-455d-956b-fe920ff2d022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880
5067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.428805067
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1753642046
Short name T451
Test name
Test status
Simulation time 154522761030 ps
CPU time 2166.2 seconds
Started Jun 30 05:19:44 PM PDT 24
Finished Jun 30 05:55:51 PM PDT 24
Peak memory 284104 kb
Host smart-4f030268-474b-46dd-bfcf-68a24ee83240
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753642046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1753642046
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2844575273
Short name T204
Test name
Test status
Simulation time 42181566 ps
CPU time 2.41 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:19:41 PM PDT 24
Peak memory 249516 kb
Host smart-ec0fd735-6a1f-411d-b2f5-55bd08f179c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2844575273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2844575273
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2919664056
Short name T459
Test name
Test status
Simulation time 152052722778 ps
CPU time 1904.42 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:51:21 PM PDT 24
Peak memory 282124 kb
Host smart-d43aba6b-396f-44f4-9b13-066bec95c2c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919664056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2919664056
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3394574739
Short name T581
Test name
Test status
Simulation time 1392323480 ps
CPU time 99.01 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:21:18 PM PDT 24
Peak memory 257440 kb
Host smart-938df919-ddfc-4b88-8ece-5580f2faf136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33945
74739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3394574739
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4087319489
Short name T615
Test name
Test status
Simulation time 408670748 ps
CPU time 22.02 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:20:01 PM PDT 24
Peak memory 257628 kb
Host smart-ca6b9af6-1f2b-45d2-adef-b5fc59a01a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873
19489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4087319489
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.702694229
Short name T105
Test name
Test status
Simulation time 92673808043 ps
CPU time 2808.93 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 06:06:28 PM PDT 24
Peak memory 289736 kb
Host smart-4eecf551-026e-48e2-8b0a-f9461aca2ff7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702694229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.702694229
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.916295308
Short name T311
Test name
Test status
Simulation time 5675324310 ps
CPU time 226.39 seconds
Started Jun 30 05:19:41 PM PDT 24
Finished Jun 30 05:23:28 PM PDT 24
Peak memory 249384 kb
Host smart-01692f66-5c60-4fe6-9b77-8d81795b7600
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916295308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.916295308
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1859853912
Short name T453
Test name
Test status
Simulation time 273162733 ps
CPU time 26.24 seconds
Started Jun 30 05:19:39 PM PDT 24
Finished Jun 30 05:20:06 PM PDT 24
Peak memory 256556 kb
Host smart-1ef2724f-099d-4a80-ad21-46f819d96238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18598
53912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1859853912
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2828054782
Short name T614
Test name
Test status
Simulation time 873750684 ps
CPU time 49.45 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 05:20:36 PM PDT 24
Peak memory 256896 kb
Host smart-004c3481-5b94-45b0-8592-2d1d1b8dc59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28280
54782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2828054782
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3554051102
Short name T474
Test name
Test status
Simulation time 854321086 ps
CPU time 50.83 seconds
Started Jun 30 05:19:41 PM PDT 24
Finished Jun 30 05:20:33 PM PDT 24
Peak memory 257004 kb
Host smart-8c92c941-24ee-48c9-b43d-af292aa5edb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35540
51102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3554051102
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4266874103
Short name T353
Test name
Test status
Simulation time 356918211 ps
CPU time 36.32 seconds
Started Jun 30 05:19:40 PM PDT 24
Finished Jun 30 05:20:16 PM PDT 24
Peak memory 249236 kb
Host smart-401a5983-f321-476c-be62-a33e1e496888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
74103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4266874103
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.436706536
Short name T266
Test name
Test status
Simulation time 24795458407 ps
CPU time 1075.71 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 05:37:43 PM PDT 24
Peak memory 289500 kb
Host smart-dca3fd56-f34f-4089-87be-c5090c3c8e81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436706536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.436706536
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2556290539
Short name T419
Test name
Test status
Simulation time 13915848330 ps
CPU time 1633.5 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:46:56 PM PDT 24
Peak memory 298592 kb
Host smart-b8fab50a-3ba5-4b5e-9062-d551ca3d5552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556290539 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2556290539
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4264139022
Short name T198
Test name
Test status
Simulation time 37523127 ps
CPU time 2.35 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:19:41 PM PDT 24
Peak memory 249548 kb
Host smart-34bd7374-53aa-424d-9af3-d8d52374cd9e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4264139022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4264139022
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2864362487
Short name T219
Test name
Test status
Simulation time 20220971846 ps
CPU time 882.37 seconds
Started Jun 30 05:19:36 PM PDT 24
Finished Jun 30 05:34:19 PM PDT 24
Peak memory 273344 kb
Host smart-cdfae230-55f4-47e4-b12b-ddfb24ea5133
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864362487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2864362487
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1315696591
Short name T358
Test name
Test status
Simulation time 88489684 ps
CPU time 5.34 seconds
Started Jun 30 05:19:43 PM PDT 24
Finished Jun 30 05:19:48 PM PDT 24
Peak memory 249136 kb
Host smart-0ccc9839-7fea-482b-afd0-6ae82a93ad64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1315696591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1315696591
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2499191212
Short name T365
Test name
Test status
Simulation time 2746234286 ps
CPU time 76.47 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:20:59 PM PDT 24
Peak memory 257416 kb
Host smart-3022a4d4-57d2-45ec-bdbb-2e1cbb8b80cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24991
91212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2499191212
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3735174947
Short name T392
Test name
Test status
Simulation time 224161247 ps
CPU time 16.05 seconds
Started Jun 30 05:19:40 PM PDT 24
Finished Jun 30 05:19:57 PM PDT 24
Peak memory 249196 kb
Host smart-f79f3f6d-5e20-455d-9d84-42bae9af26ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37351
74947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3735174947
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.125815781
Short name T278
Test name
Test status
Simulation time 54236058621 ps
CPU time 993.47 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:36:22 PM PDT 24
Peak memory 282104 kb
Host smart-451df45c-d8d1-45f8-a359-a0b12bdd66b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125815781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.125815781
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1242805361
Short name T188
Test name
Test status
Simulation time 12385684849 ps
CPU time 1084.38 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:37:43 PM PDT 24
Peak memory 290200 kb
Host smart-0f56555f-277a-4462-8287-f81406192da1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242805361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1242805361
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1842714249
Short name T283
Test name
Test status
Simulation time 25514195801 ps
CPU time 529.5 seconds
Started Jun 30 05:19:43 PM PDT 24
Finished Jun 30 05:28:33 PM PDT 24
Peak memory 248248 kb
Host smart-5f454510-557e-4fca-aa83-527942c1f873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842714249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1842714249
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4000473261
Short name T385
Test name
Test status
Simulation time 155962194 ps
CPU time 18.82 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:19:57 PM PDT 24
Peak memory 256768 kb
Host smart-cef8e9bd-a44a-4e95-adb0-d3cdb6482b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40004
73261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4000473261
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.481059617
Short name T535
Test name
Test status
Simulation time 2371858901 ps
CPU time 72.19 seconds
Started Jun 30 05:19:43 PM PDT 24
Finished Jun 30 05:20:56 PM PDT 24
Peak memory 250372 kb
Host smart-eda39988-b9ac-4bdf-90c8-023c1a3d64ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48105
9617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.481059617
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.4238781562
Short name T98
Test name
Test status
Simulation time 2504351429 ps
CPU time 37.49 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:20:20 PM PDT 24
Peak memory 248848 kb
Host smart-c6ea3055-2986-47d0-ba7a-a63cf10a3a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42387
81562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.4238781562
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3413565071
Short name T178
Test name
Test status
Simulation time 510412272 ps
CPU time 32.44 seconds
Started Jun 30 05:19:44 PM PDT 24
Finished Jun 30 05:20:17 PM PDT 24
Peak memory 256536 kb
Host smart-e7e311da-74d2-4d12-bc19-8e1fb0963813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34135
65071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3413565071
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3203334437
Short name T524
Test name
Test status
Simulation time 18610681169 ps
CPU time 1579.53 seconds
Started Jun 30 05:19:44 PM PDT 24
Finished Jun 30 05:46:04 PM PDT 24
Peak memory 288884 kb
Host smart-c2d69492-10d6-4e49-be05-89533c3eba5d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203334437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3203334437
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1424720359
Short name T196
Test name
Test status
Simulation time 46880430 ps
CPU time 3.63 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:19:46 PM PDT 24
Peak memory 249548 kb
Host smart-32380d3a-ee47-4563-a3c3-b1d7b4570a7f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1424720359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1424720359
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2116765053
Short name T491
Test name
Test status
Simulation time 31751421447 ps
CPU time 1515.8 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:44:58 PM PDT 24
Peak memory 289648 kb
Host smart-d8be38dd-ad1d-42a7-bd27-aa9f2295f613
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116765053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2116765053
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3229773670
Short name T623
Test name
Test status
Simulation time 1204768624 ps
CPU time 26.8 seconds
Started Jun 30 05:19:41 PM PDT 24
Finished Jun 30 05:20:08 PM PDT 24
Peak memory 249236 kb
Host smart-fb4a62f1-51f5-40c1-9e9a-0bceea82860c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3229773670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3229773670
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2641454842
Short name T544
Test name
Test status
Simulation time 11255096662 ps
CPU time 103.1 seconds
Started Jun 30 05:19:40 PM PDT 24
Finished Jun 30 05:21:24 PM PDT 24
Peak memory 256884 kb
Host smart-df490c23-b8bf-4a3b-9014-85e894f9afe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26414
54842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2641454842
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.788849117
Short name T455
Test name
Test status
Simulation time 81904797 ps
CPU time 3.93 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:19:47 PM PDT 24
Peak memory 240596 kb
Host smart-292e1a77-0783-4935-830c-c6f943e59a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78884
9117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.788849117
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.4258191707
Short name T331
Test name
Test status
Simulation time 9871701211 ps
CPU time 909.23 seconds
Started Jun 30 05:19:39 PM PDT 24
Finished Jun 30 05:34:49 PM PDT 24
Peak memory 273932 kb
Host smart-7bccac0b-c5b2-43f4-be74-8e18cc231f3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258191707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.4258191707
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1725538350
Short name T464
Test name
Test status
Simulation time 35429101028 ps
CPU time 2268.34 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 05:57:36 PM PDT 24
Peak memory 290296 kb
Host smart-7a908bf0-3a48-46fe-b471-ff86530bd03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725538350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1725538350
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2942632212
Short name T84
Test name
Test status
Simulation time 32991572379 ps
CPU time 335.44 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:25:14 PM PDT 24
Peak memory 249160 kb
Host smart-478b4b55-1f23-425e-96ee-da01c0a871b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942632212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2942632212
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4222884119
Short name T348
Test name
Test status
Simulation time 703494341 ps
CPU time 22.74 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 05:20:01 PM PDT 24
Peak memory 249268 kb
Host smart-60c940d0-a7d6-4349-9230-595ebbc8f200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228
84119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4222884119
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2410191218
Short name T498
Test name
Test status
Simulation time 904654266 ps
CPU time 24.87 seconds
Started Jun 30 05:19:43 PM PDT 24
Finished Jun 30 05:20:09 PM PDT 24
Peak memory 248392 kb
Host smart-bffd8c5a-ab66-4c2e-bfba-6b2ebc85ab94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24101
91218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2410191218
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1178638750
Short name T255
Test name
Test status
Simulation time 451359839 ps
CPU time 28.48 seconds
Started Jun 30 05:19:39 PM PDT 24
Finished Jun 30 05:20:08 PM PDT 24
Peak memory 249272 kb
Host smart-3eef6bc3-426e-4bfb-970d-295d90372cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11786
38750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1178638750
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2849670711
Short name T404
Test name
Test status
Simulation time 6186200670 ps
CPU time 46.67 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:20:26 PM PDT 24
Peak memory 256624 kb
Host smart-8f1c6cb4-e29b-4fd6-838f-84d3e311b59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28496
70711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2849670711
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3996179129
Short name T234
Test name
Test status
Simulation time 44514496238 ps
CPU time 5238.9 seconds
Started Jun 30 05:19:45 PM PDT 24
Finished Jun 30 06:47:05 PM PDT 24
Peak memory 364244 kb
Host smart-0d5030ed-5673-4143-95e2-dd121be02662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996179129 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3996179129
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3564285148
Short name T199
Test name
Test status
Simulation time 197845541 ps
CPU time 4.64 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:11 PM PDT 24
Peak memory 249564 kb
Host smart-39a65b75-c8d6-470b-ba4c-c2885df10b37
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3564285148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3564285148
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2157647602
Short name T15
Test name
Test status
Simulation time 198099036035 ps
CPU time 2792.39 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 06:05:40 PM PDT 24
Peak memory 289616 kb
Host smart-b5ed7e08-8c47-41c3-9d93-081868c115ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157647602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2157647602
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1804623070
Short name T594
Test name
Test status
Simulation time 1756942075 ps
CPU time 37.83 seconds
Started Jun 30 05:18:59 PM PDT 24
Finished Jun 30 05:19:38 PM PDT 24
Peak memory 249204 kb
Host smart-4b2d1c3e-6d1e-4ddb-b730-bc7a915a4f91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1804623070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1804623070
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1638008566
Short name T378
Test name
Test status
Simulation time 43388691500 ps
CPU time 224.15 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:22:46 PM PDT 24
Peak memory 256768 kb
Host smart-ff7054f5-a169-4192-bce7-123076ae0289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16380
08566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1638008566
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.218884351
Short name T102
Test name
Test status
Simulation time 3406580142 ps
CPU time 63.61 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:20:10 PM PDT 24
Peak memory 256240 kb
Host smart-dce9af8f-5660-411f-b8b5-6b3b4f4719c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21888
4351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.218884351
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3597850393
Short name T669
Test name
Test status
Simulation time 53543933905 ps
CPU time 3422.13 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 06:16:07 PM PDT 24
Peak memory 290276 kb
Host smart-bb96da5a-d6b4-4eb1-853a-44391701f784
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597850393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3597850393
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.148118919
Short name T394
Test name
Test status
Simulation time 603762608379 ps
CPU time 3366.08 seconds
Started Jun 30 05:18:58 PM PDT 24
Finished Jun 30 06:15:05 PM PDT 24
Peak memory 289404 kb
Host smart-76c6ecab-05d7-4023-964c-423987e6b1f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148118919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.148118919
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.657763388
Short name T637
Test name
Test status
Simulation time 12767451164 ps
CPU time 513.66 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:27:44 PM PDT 24
Peak memory 249332 kb
Host smart-626d0063-5a36-4853-84dd-5145fa5ea92d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657763388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.657763388
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.4181010143
Short name T374
Test name
Test status
Simulation time 536720148 ps
CPU time 4.48 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:19:12 PM PDT 24
Peak memory 241080 kb
Host smart-e1d43302-62c4-4d7d-ab2d-a8c66a8d0495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41810
10143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.4181010143
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2676698843
Short name T57
Test name
Test status
Simulation time 557360245 ps
CPU time 15.18 seconds
Started Jun 30 05:18:57 PM PDT 24
Finished Jun 30 05:19:13 PM PDT 24
Peak memory 248820 kb
Host smart-1041d6e3-0942-488d-9bee-a8c8e9d7b56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26766
98843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2676698843
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3264530152
Short name T11
Test name
Test status
Simulation time 1932371540 ps
CPU time 29.51 seconds
Started Jun 30 05:18:59 PM PDT 24
Finished Jun 30 05:19:30 PM PDT 24
Peak memory 270540 kb
Host smart-f8dcfa78-db5d-4682-82fb-06b05266d8f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3264530152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3264530152
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1127976596
Short name T543
Test name
Test status
Simulation time 490585170 ps
CPU time 30.92 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:19:39 PM PDT 24
Peak memory 249212 kb
Host smart-458eda49-dafe-4cfd-8a0f-174027568e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11279
76596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1127976596
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.93292271
Short name T434
Test name
Test status
Simulation time 876075403 ps
CPU time 25.5 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:19:36 PM PDT 24
Peak memory 249736 kb
Host smart-8df2f87e-c6e6-4f44-a155-200e31ce368b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93292
271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.93292271
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3022651918
Short name T258
Test name
Test status
Simulation time 244201941843 ps
CPU time 3462.32 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 06:16:52 PM PDT 24
Peak memory 301212 kb
Host smart-db02b340-4ec5-42ee-8121-9c092fc61144
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022651918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3022651918
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2652616789
Short name T16
Test name
Test status
Simulation time 76261880212 ps
CPU time 2244.31 seconds
Started Jun 30 05:19:45 PM PDT 24
Finished Jun 30 05:57:10 PM PDT 24
Peak memory 283984 kb
Host smart-42ec7714-9567-400c-9995-b1bd66c4d71c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652616789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2652616789
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3155371892
Short name T366
Test name
Test status
Simulation time 6344231912 ps
CPU time 189.5 seconds
Started Jun 30 05:19:43 PM PDT 24
Finished Jun 30 05:22:54 PM PDT 24
Peak memory 257176 kb
Host smart-e1ee1188-2166-4f1b-b172-e7333be2bec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31553
71892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3155371892
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.648502888
Short name T214
Test name
Test status
Simulation time 69973524 ps
CPU time 5.41 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:19:56 PM PDT 24
Peak memory 241012 kb
Host smart-52aeb880-50d0-4e1f-9e77-e4178547123e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64850
2888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.648502888
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1100729105
Short name T330
Test name
Test status
Simulation time 89005707409 ps
CPU time 1284.11 seconds
Started Jun 30 05:19:34 PM PDT 24
Finished Jun 30 05:40:59 PM PDT 24
Peak memory 272952 kb
Host smart-5f7f348f-3a5f-45e1-a2af-7b3c74650298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100729105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1100729105
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1426255976
Short name T431
Test name
Test status
Simulation time 293660049501 ps
CPU time 2945.69 seconds
Started Jun 30 05:19:37 PM PDT 24
Finished Jun 30 06:08:44 PM PDT 24
Peak memory 285804 kb
Host smart-6713eee1-4c75-4088-9549-6a71166d2b5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426255976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1426255976
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.191369643
Short name T373
Test name
Test status
Simulation time 292314178 ps
CPU time 22.91 seconds
Started Jun 30 05:19:41 PM PDT 24
Finished Jun 30 05:20:04 PM PDT 24
Peak memory 249280 kb
Host smart-7d399215-b170-4ef7-a677-a5bbb749710f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19136
9643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.191369643
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2462519088
Short name T603
Test name
Test status
Simulation time 1190135132 ps
CPU time 68.82 seconds
Started Jun 30 05:19:45 PM PDT 24
Finished Jun 30 05:20:55 PM PDT 24
Peak memory 248840 kb
Host smart-67169160-ee55-40b7-85a3-c9b44edcbafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24625
19088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2462519088
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1459655381
Short name T618
Test name
Test status
Simulation time 1081683462 ps
CPU time 19.68 seconds
Started Jun 30 05:19:44 PM PDT 24
Finished Jun 30 05:20:04 PM PDT 24
Peak memory 256016 kb
Host smart-fd938904-7c29-4a09-8744-ba363d48e9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14596
55381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1459655381
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2524902248
Short name T438
Test name
Test status
Simulation time 174752232116 ps
CPU time 2714.03 seconds
Started Jun 30 05:19:50 PM PDT 24
Finished Jun 30 06:05:05 PM PDT 24
Peak memory 285972 kb
Host smart-89c41be7-b4c3-4449-8491-cf1aad6efc13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524902248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2524902248
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2967198241
Short name T403
Test name
Test status
Simulation time 2494516428 ps
CPU time 182.45 seconds
Started Jun 30 05:19:38 PM PDT 24
Finished Jun 30 05:22:42 PM PDT 24
Peak memory 257580 kb
Host smart-45a553e6-b734-430b-9bd1-c224950b5135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29671
98241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2967198241
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3398717926
Short name T390
Test name
Test status
Simulation time 336046469 ps
CPU time 18.03 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:20:00 PM PDT 24
Peak memory 255704 kb
Host smart-b8ed83fe-11aa-4675-9728-a6cdf7a0a883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
17926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3398717926
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1606195702
Short name T312
Test name
Test status
Simulation time 136255272054 ps
CPU time 2153.85 seconds
Started Jun 30 05:19:45 PM PDT 24
Finished Jun 30 05:55:39 PM PDT 24
Peak memory 287780 kb
Host smart-ee97616e-6b07-4839-9896-c0010128ce6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606195702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1606195702
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.863734245
Short name T425
Test name
Test status
Simulation time 71422073328 ps
CPU time 1601.61 seconds
Started Jun 30 05:19:44 PM PDT 24
Finished Jun 30 05:46:27 PM PDT 24
Peak memory 273924 kb
Host smart-77f4c9df-6079-4a31-8329-a332a0c08a34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863734245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.863734245
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2071424798
Short name T696
Test name
Test status
Simulation time 1574635165 ps
CPU time 27.75 seconds
Started Jun 30 05:19:44 PM PDT 24
Finished Jun 30 05:20:12 PM PDT 24
Peak memory 256796 kb
Host smart-8532d66b-bc6c-4296-906d-25b271a8c7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20714
24798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2071424798
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1640375702
Short name T541
Test name
Test status
Simulation time 245758162 ps
CPU time 14.87 seconds
Started Jun 30 05:19:41 PM PDT 24
Finished Jun 30 05:19:56 PM PDT 24
Peak memory 248704 kb
Host smart-5320e90b-e502-4437-86eb-cafc241e7462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16403
75702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1640375702
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3666599375
Short name T237
Test name
Test status
Simulation time 369223108 ps
CPU time 22.57 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 05:20:09 PM PDT 24
Peak memory 256464 kb
Host smart-054c3b43-558e-4431-8a94-294efe040125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36665
99375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3666599375
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2320893252
Short name T364
Test name
Test status
Simulation time 2500609129 ps
CPU time 40.7 seconds
Started Jun 30 05:19:42 PM PDT 24
Finished Jun 30 05:20:23 PM PDT 24
Peak memory 249520 kb
Host smart-045faa75-dcea-4968-b6d5-c415944d8e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
93252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2320893252
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3157897147
Short name T627
Test name
Test status
Simulation time 1701343964 ps
CPU time 144.89 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 05:22:12 PM PDT 24
Peak memory 257304 kb
Host smart-eb29b346-583d-42c4-8c08-049f8f8f3b48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157897147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3157897147
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2052569579
Short name T69
Test name
Test status
Simulation time 32374900331 ps
CPU time 3582.95 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 06:19:30 PM PDT 24
Peak memory 315064 kb
Host smart-16f771c2-13e1-4e18-ba92-5bef468f8943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052569579 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2052569579
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3652413043
Short name T482
Test name
Test status
Simulation time 30244272976 ps
CPU time 1691.36 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 05:47:59 PM PDT 24
Peak memory 273420 kb
Host smart-39e06f6b-e48c-4fe7-97bd-62736acf4ee0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652413043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3652413043
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3398768741
Short name T590
Test name
Test status
Simulation time 4609508321 ps
CPU time 105.56 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 05:21:32 PM PDT 24
Peak memory 256884 kb
Host smart-13b99142-67c3-4357-86f7-1477c6528649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
68741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3398768741
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3430414461
Short name T635
Test name
Test status
Simulation time 177869570 ps
CPU time 11.04 seconds
Started Jun 30 05:19:44 PM PDT 24
Finished Jun 30 05:19:56 PM PDT 24
Peak memory 248732 kb
Host smart-ec4a95c1-ebed-4517-bd41-0d1c44e05509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34304
14461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3430414461
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.487759651
Short name T334
Test name
Test status
Simulation time 40799274052 ps
CPU time 1182.13 seconds
Started Jun 30 05:19:45 PM PDT 24
Finished Jun 30 05:39:28 PM PDT 24
Peak memory 289448 kb
Host smart-6a23c65b-50ed-483d-bbf0-0269b6b097a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487759651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.487759651
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4246842224
Short name T447
Test name
Test status
Simulation time 251759995183 ps
CPU time 1407.14 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 05:43:15 PM PDT 24
Peak memory 286804 kb
Host smart-8068ba3b-d782-4855-8473-0625c024665a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246842224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4246842224
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1701007689
Short name T303
Test name
Test status
Simulation time 27328424725 ps
CPU time 295.36 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 05:24:43 PM PDT 24
Peak memory 255888 kb
Host smart-3fa79dec-7c6d-400f-ae40-b06d1563b4b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701007689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1701007689
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1066816556
Short name T22
Test name
Test status
Simulation time 4877681916 ps
CPU time 27.24 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:20:16 PM PDT 24
Peak memory 256012 kb
Host smart-4d13fd2c-1d20-47fb-9b8c-b00d308b6b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10668
16556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1066816556
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.4168791327
Short name T639
Test name
Test status
Simulation time 315986972 ps
CPU time 10.64 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:00 PM PDT 24
Peak memory 255688 kb
Host smart-f9a64340-1210-435d-83c3-3fc6fa069cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
91327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4168791327
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.447571128
Short name T407
Test name
Test status
Simulation time 690542429 ps
CPU time 20.2 seconds
Started Jun 30 05:19:40 PM PDT 24
Finished Jun 30 05:20:00 PM PDT 24
Peak memory 248636 kb
Host smart-2837ef6b-73b8-4a57-b429-f3067d772712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44757
1128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.447571128
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4231486790
Short name T595
Test name
Test status
Simulation time 167235533 ps
CPU time 10.55 seconds
Started Jun 30 05:19:41 PM PDT 24
Finished Jun 30 05:19:52 PM PDT 24
Peak memory 255956 kb
Host smart-6ca05a0b-bbc0-45ac-8da1-3d8dac689c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42314
86790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4231486790
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1457057395
Short name T108
Test name
Test status
Simulation time 41791116505 ps
CPU time 476.59 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:27:45 PM PDT 24
Peak memory 257584 kb
Host smart-7c9f3faf-106e-45cc-ab0c-667cf6a1fafc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457057395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1457057395
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.886861628
Short name T616
Test name
Test status
Simulation time 27737402082 ps
CPU time 1252.47 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:40:41 PM PDT 24
Peak memory 289396 kb
Host smart-da0bf380-98c6-4925-997d-558d13d39100
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886861628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.886861628
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.911427440
Short name T610
Test name
Test status
Simulation time 11084544025 ps
CPU time 248.73 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:23:58 PM PDT 24
Peak memory 257116 kb
Host smart-2014b4eb-77aa-4034-9b59-1b2f958edbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91142
7440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.911427440
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2395092059
Short name T244
Test name
Test status
Simulation time 3400110717 ps
CPU time 30.53 seconds
Started Jun 30 05:19:50 PM PDT 24
Finished Jun 30 05:20:21 PM PDT 24
Peak memory 248936 kb
Host smart-ba4022ff-121c-40a9-816a-4a6402f8e54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
92059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2395092059
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.481383541
Short name T333
Test name
Test status
Simulation time 14967220263 ps
CPU time 817.93 seconds
Started Jun 30 05:19:52 PM PDT 24
Finished Jun 30 05:33:31 PM PDT 24
Peak memory 273880 kb
Host smart-406b953e-fa1e-4124-813a-467b36189e69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481383541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.481383541
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.976882402
Short name T579
Test name
Test status
Simulation time 104430065048 ps
CPU time 1499.95 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:44:51 PM PDT 24
Peak memory 273436 kb
Host smart-f373f692-9982-4baa-9c0a-b3c857ae488c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976882402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.976882402
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2949891747
Short name T295
Test name
Test status
Simulation time 8279451705 ps
CPU time 169.07 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:22:37 PM PDT 24
Peak memory 249320 kb
Host smart-07fdbec5-460a-4036-8083-eae635c21826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949891747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2949891747
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.979133415
Short name T674
Test name
Test status
Simulation time 1593306387 ps
CPU time 33.37 seconds
Started Jun 30 05:19:46 PM PDT 24
Finished Jun 30 05:20:20 PM PDT 24
Peak memory 257364 kb
Host smart-d3c340b1-4f20-44f2-819a-3d814b191452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97913
3415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.979133415
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.4215555938
Short name T412
Test name
Test status
Simulation time 403726405 ps
CPU time 33.75 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:24 PM PDT 24
Peak memory 249200 kb
Host smart-9b80fb3d-1c50-422a-ac5a-9987742da86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42155
55938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4215555938
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1974046603
Short name T253
Test name
Test status
Simulation time 1705830952 ps
CPU time 33.05 seconds
Started Jun 30 05:19:55 PM PDT 24
Finished Jun 30 05:20:28 PM PDT 24
Peak memory 249296 kb
Host smart-58c6e4b3-5881-45b8-966f-574b652ff4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19740
46603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1974046603
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1715056148
Short name T437
Test name
Test status
Simulation time 465917310 ps
CPU time 16.51 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:06 PM PDT 24
Peak memory 249108 kb
Host smart-5614cb12-6a39-4e42-b084-0fac03e1edc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
56148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1715056148
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1065942373
Short name T430
Test name
Test status
Simulation time 48969345621 ps
CPU time 2541.17 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 06:02:11 PM PDT 24
Peak memory 289896 kb
Host smart-0b680996-efb4-4efa-9fde-3c8a688ca7d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065942373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1065942373
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3863640942
Short name T236
Test name
Test status
Simulation time 16578205969 ps
CPU time 1613.69 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:46:44 PM PDT 24
Peak memory 303032 kb
Host smart-628b1323-0941-4e82-b047-befc48c29e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863640942 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3863640942
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1684581609
Short name T660
Test name
Test status
Simulation time 43390779138 ps
CPU time 880.34 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:34:35 PM PDT 24
Peak memory 273864 kb
Host smart-5fadda57-b16e-4bf6-a6e1-1f1aac13b629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684581609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1684581609
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1046571607
Short name T700
Test name
Test status
Simulation time 8649383061 ps
CPU time 123.89 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 05:21:52 PM PDT 24
Peak memory 256688 kb
Host smart-7d7fc456-3646-4243-8197-8d0069affcd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
71607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1046571607
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2520274984
Short name T243
Test name
Test status
Simulation time 3297570493 ps
CPU time 67.15 seconds
Started Jun 30 05:19:55 PM PDT 24
Finished Jun 30 05:21:03 PM PDT 24
Peak memory 257600 kb
Host smart-e3c9bc90-6b0f-48d4-84c9-5a55cc316a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25202
74984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2520274984
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.70824120
Short name T473
Test name
Test status
Simulation time 12825830128 ps
CPU time 963.62 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:35:59 PM PDT 24
Peak memory 273904 kb
Host smart-5fd0864b-ba7e-4df4-ab12-94db0409bb8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70824120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.70824120
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1526643944
Short name T421
Test name
Test status
Simulation time 202238783648 ps
CPU time 2890.21 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 06:08:00 PM PDT 24
Peak memory 288444 kb
Host smart-4ef667d5-5957-41d5-9217-b9be3103f8e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526643944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1526643944
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1922361768
Short name T553
Test name
Test status
Simulation time 18586796563 ps
CPU time 367.23 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:25:57 PM PDT 24
Peak memory 256152 kb
Host smart-c512521e-5845-4d6c-b581-a9ddee8c10bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922361768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1922361768
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2072802614
Short name T642
Test name
Test status
Simulation time 3883076539 ps
CPU time 37.66 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:28 PM PDT 24
Peak memory 256748 kb
Host smart-e9a2f9c3-9cf8-4e84-bf43-57d396a214b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20728
02614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2072802614
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.494573748
Short name T580
Test name
Test status
Simulation time 1756106119 ps
CPU time 62.36 seconds
Started Jun 30 05:19:55 PM PDT 24
Finished Jun 30 05:20:58 PM PDT 24
Peak memory 248824 kb
Host smart-d90407bb-645a-48cf-bd95-94d036f129f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49457
3748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.494573748
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1252300512
Short name T256
Test name
Test status
Simulation time 121821733 ps
CPU time 20.14 seconds
Started Jun 30 05:19:52 PM PDT 24
Finished Jun 30 05:20:13 PM PDT 24
Peak memory 248796 kb
Host smart-6c55215e-9df8-49e5-810e-07751d99a11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523
00512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1252300512
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3939812630
Short name T410
Test name
Test status
Simulation time 2508204003 ps
CPU time 37.95 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:28 PM PDT 24
Peak memory 257552 kb
Host smart-ed5143d3-7430-46d6-b3d4-ac907864ecac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39398
12630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3939812630
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.4045855167
Short name T249
Test name
Test status
Simulation time 343886618403 ps
CPU time 1797.44 seconds
Started Jun 30 05:19:47 PM PDT 24
Finished Jun 30 05:49:45 PM PDT 24
Peak memory 285588 kb
Host smart-be1d3d99-e9c8-408d-ad3a-945363ab00cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045855167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.4045855167
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.827384122
Short name T228
Test name
Test status
Simulation time 56503921202 ps
CPU time 1982.53 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:52:51 PM PDT 24
Peak memory 286936 kb
Host smart-f63e3d59-882d-4d7f-8417-c0c721673789
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827384122 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.827384122
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.294661481
Short name T622
Test name
Test status
Simulation time 74791825449 ps
CPU time 940.65 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:35:35 PM PDT 24
Peak memory 273816 kb
Host smart-ef861d35-9940-4962-8122-1cedc87b81fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294661481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.294661481
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3913472130
Short name T694
Test name
Test status
Simulation time 1515473280 ps
CPU time 52.37 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:43 PM PDT 24
Peak memory 257456 kb
Host smart-33746e9f-0dea-4dfc-be15-38f686b037e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134
72130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3913472130
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4274274755
Short name T542
Test name
Test status
Simulation time 436395215 ps
CPU time 23.26 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:13 PM PDT 24
Peak memory 249196 kb
Host smart-2af48bdd-b18b-47e0-921c-0be9ad0e79c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42742
74755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4274274755
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3757257380
Short name T332
Test name
Test status
Simulation time 37427174788 ps
CPU time 1325.4 seconds
Started Jun 30 05:19:55 PM PDT 24
Finished Jun 30 05:42:01 PM PDT 24
Peak memory 289228 kb
Host smart-d4a27a09-5a4e-4a6a-85d8-6227cf62534e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757257380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3757257380
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1345671290
Short name T442
Test name
Test status
Simulation time 46442999490 ps
CPU time 1034.78 seconds
Started Jun 30 05:19:55 PM PDT 24
Finished Jun 30 05:37:10 PM PDT 24
Peak memory 289072 kb
Host smart-0fb8c5ae-ed60-4f7e-92a2-3e3ef004662d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345671290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1345671290
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3397999691
Short name T45
Test name
Test status
Simulation time 1233015931 ps
CPU time 29.71 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:20:18 PM PDT 24
Peak memory 256692 kb
Host smart-4accfb6d-5b3e-48f2-9184-0fbbd22abc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33979
99691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3397999691
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4294637458
Short name T500
Test name
Test status
Simulation time 54373216 ps
CPU time 4.56 seconds
Started Jun 30 05:19:50 PM PDT 24
Finished Jun 30 05:19:56 PM PDT 24
Peak memory 241044 kb
Host smart-09ecbafa-4fba-4acb-a3a6-ffc1d6adca07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42946
37458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4294637458
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2004814935
Short name T497
Test name
Test status
Simulation time 470943268 ps
CPU time 35.29 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:20:26 PM PDT 24
Peak memory 256688 kb
Host smart-e9ce7b8a-29a6-4ce0-983c-04df8c564087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20048
14935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2004814935
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3260700648
Short name T475
Test name
Test status
Simulation time 3262479359 ps
CPU time 74.36 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:21:09 PM PDT 24
Peak memory 257516 kb
Host smart-03f8bf87-12ea-477f-90a8-9ef7ce0c11c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32607
00648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3260700648
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3666386419
Short name T24
Test name
Test status
Simulation time 9363365509 ps
CPU time 177.59 seconds
Started Jun 30 05:19:48 PM PDT 24
Finished Jun 30 05:22:46 PM PDT 24
Peak memory 257500 kb
Host smart-19abe68f-377a-4d11-9887-6643be680409
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666386419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3666386419
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3106465216
Short name T276
Test name
Test status
Simulation time 273076998288 ps
CPU time 2843.39 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 06:07:18 PM PDT 24
Peak memory 290108 kb
Host smart-631f1bab-24d6-4049-a4dc-94a9b6de23d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106465216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3106465216
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3398818378
Short name T488
Test name
Test status
Simulation time 7936040977 ps
CPU time 267.15 seconds
Started Jun 30 05:19:55 PM PDT 24
Finished Jun 30 05:24:22 PM PDT 24
Peak memory 257536 kb
Host smart-8ff3e0de-2678-4bc3-bf63-099a2aa8ba28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33988
18378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3398818378
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.335898478
Short name T439
Test name
Test status
Simulation time 470309232 ps
CPU time 36.4 seconds
Started Jun 30 05:19:57 PM PDT 24
Finished Jun 30 05:20:34 PM PDT 24
Peak memory 249816 kb
Host smart-8c184531-a2f8-4bd6-9f86-d2aac103f9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589
8478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.335898478
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2538629754
Short name T280
Test name
Test status
Simulation time 22153385621 ps
CPU time 1520.73 seconds
Started Jun 30 05:19:58 PM PDT 24
Finished Jun 30 05:45:19 PM PDT 24
Peak memory 289424 kb
Host smart-37afaf04-be6d-4a7d-a9c2-741f337c2138
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538629754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2538629754
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.881838888
Short name T94
Test name
Test status
Simulation time 8891110182 ps
CPU time 800.04 seconds
Started Jun 30 05:19:53 PM PDT 24
Finished Jun 30 05:33:14 PM PDT 24
Peak memory 269812 kb
Host smart-c9c18cdd-9b3a-4e9a-b6f4-daa73263ed62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881838888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.881838888
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1398573146
Short name T302
Test name
Test status
Simulation time 4486251599 ps
CPU time 95.01 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:21:29 PM PDT 24
Peak memory 255528 kb
Host smart-f20ff03b-32a6-4747-b20c-ed38eb3d970b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398573146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1398573146
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.30339536
Short name T463
Test name
Test status
Simulation time 646902896 ps
CPU time 39.64 seconds
Started Jun 30 05:19:50 PM PDT 24
Finished Jun 30 05:20:31 PM PDT 24
Peak memory 257008 kb
Host smart-1c162c44-99b3-4d7e-ab49-316df47e6517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30339
536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.30339536
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2182378525
Short name T582
Test name
Test status
Simulation time 491914325 ps
CPU time 8.92 seconds
Started Jun 30 05:19:49 PM PDT 24
Finished Jun 30 05:19:59 PM PDT 24
Peak memory 248584 kb
Host smart-261397e1-8f4f-4807-8ed4-084cf5ceb7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21823
78525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2182378525
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3460207187
Short name T52
Test name
Test status
Simulation time 999461752 ps
CPU time 73.08 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:21:08 PM PDT 24
Peak memory 249336 kb
Host smart-7f1fca66-fe6d-4c34-a64e-c619c511e322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34602
07187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3460207187
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2112398132
Short name T408
Test name
Test status
Simulation time 919989001 ps
CPU time 36.25 seconds
Started Jun 30 05:19:50 PM PDT 24
Finished Jun 30 05:20:27 PM PDT 24
Peak memory 257416 kb
Host smart-935fe405-9a63-477e-ba81-d2ce0d62ac0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21123
98132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2112398132
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3510011529
Short name T534
Test name
Test status
Simulation time 3653556298 ps
CPU time 55.25 seconds
Started Jun 30 05:19:53 PM PDT 24
Finished Jun 30 05:20:48 PM PDT 24
Peak memory 256800 kb
Host smart-f0a34b03-6325-4cb2-a9f6-af2b14d9abd3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510011529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3510011529
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3893055478
Short name T485
Test name
Test status
Simulation time 97707998936 ps
CPU time 1670.04 seconds
Started Jun 30 05:19:56 PM PDT 24
Finished Jun 30 05:47:46 PM PDT 24
Peak memory 273408 kb
Host smart-0328d6d9-a222-4fb5-92eb-8357ed176279
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893055478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3893055478
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1536601262
Short name T1
Test name
Test status
Simulation time 1535051345 ps
CPU time 17.21 seconds
Started Jun 30 05:19:53 PM PDT 24
Finished Jun 30 05:20:10 PM PDT 24
Peak memory 248632 kb
Host smart-27ed6fed-6ea4-4b29-9d0c-aae3a054712f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366
01262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1536601262
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2407583560
Short name T3
Test name
Test status
Simulation time 540732600 ps
CPU time 33.28 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:20:28 PM PDT 24
Peak memory 249212 kb
Host smart-ff351748-7969-45e3-886a-96f16cdcfe52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24075
83560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2407583560
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1500942119
Short name T325
Test name
Test status
Simulation time 45293823185 ps
CPU time 1089.04 seconds
Started Jun 30 05:20:03 PM PDT 24
Finished Jun 30 05:38:13 PM PDT 24
Peak memory 282128 kb
Host smart-928a5708-93cd-4bff-937d-c9db5b696f3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500942119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1500942119
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3659594314
Short name T620
Test name
Test status
Simulation time 28633054829 ps
CPU time 1347.27 seconds
Started Jun 30 05:20:04 PM PDT 24
Finished Jun 30 05:42:32 PM PDT 24
Peak memory 289964 kb
Host smart-801dc36f-e80f-40f0-884c-a206e3f5fb24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659594314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3659594314
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2821424708
Short name T294
Test name
Test status
Simulation time 2617028803 ps
CPU time 109.53 seconds
Started Jun 30 05:19:56 PM PDT 24
Finished Jun 30 05:21:46 PM PDT 24
Peak memory 249328 kb
Host smart-fe89fc12-4d39-4dcf-b60f-263737c2df1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821424708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2821424708
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3470851295
Short name T688
Test name
Test status
Simulation time 837851907 ps
CPU time 14.2 seconds
Started Jun 30 05:19:58 PM PDT 24
Finished Jun 30 05:20:12 PM PDT 24
Peak memory 249244 kb
Host smart-8acfbaf8-4604-45ec-938f-562bc9e477df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34708
51295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3470851295
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1158319298
Short name T664
Test name
Test status
Simulation time 1068507915 ps
CPU time 64.16 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:20:59 PM PDT 24
Peak memory 256584 kb
Host smart-b13d1ff0-0f43-4be7-8290-71b3188e4151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11583
19298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1158319298
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.902149788
Short name T597
Test name
Test status
Simulation time 387995432 ps
CPU time 21.24 seconds
Started Jun 30 05:19:54 PM PDT 24
Finished Jun 30 05:20:16 PM PDT 24
Peak memory 257028 kb
Host smart-60dc9d85-fb21-479a-bcf7-11bfaa2f2fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90214
9788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.902149788
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1597089551
Short name T517
Test name
Test status
Simulation time 621849400 ps
CPU time 39.87 seconds
Started Jun 30 05:20:03 PM PDT 24
Finished Jun 30 05:20:43 PM PDT 24
Peak memory 256876 kb
Host smart-a37e00e9-052d-4545-adbe-dc238dac42fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597089551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1597089551
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1883310777
Short name T235
Test name
Test status
Simulation time 50611034259 ps
CPU time 4646.32 seconds
Started Jun 30 05:20:02 PM PDT 24
Finished Jun 30 06:37:30 PM PDT 24
Peak memory 338064 kb
Host smart-e41259be-01e5-4a20-b8a1-3b0c5a52394b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883310777 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1883310777
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1220216204
Short name T40
Test name
Test status
Simulation time 42287339433 ps
CPU time 1340.59 seconds
Started Jun 30 05:20:07 PM PDT 24
Finished Jun 30 05:42:28 PM PDT 24
Peak memory 289388 kb
Host smart-1d792558-6052-4319-866e-1b18d6f89fb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220216204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1220216204
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2109197610
Short name T528
Test name
Test status
Simulation time 9778560355 ps
CPU time 112.67 seconds
Started Jun 30 05:20:05 PM PDT 24
Finished Jun 30 05:21:58 PM PDT 24
Peak memory 257512 kb
Host smart-7e298c91-156f-4c99-bbef-09326a62bb7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21091
97610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2109197610
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2152286218
Short name T406
Test name
Test status
Simulation time 1806283890 ps
CPU time 58.77 seconds
Started Jun 30 05:20:03 PM PDT 24
Finished Jun 30 05:21:02 PM PDT 24
Peak memory 249012 kb
Host smart-ff2ca0f8-78c7-422e-b3f4-3fd507bf604c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21522
86218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2152286218
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.529821235
Short name T321
Test name
Test status
Simulation time 78728295716 ps
CPU time 1351.14 seconds
Started Jun 30 05:20:02 PM PDT 24
Finished Jun 30 05:42:33 PM PDT 24
Peak memory 289096 kb
Host smart-85850698-dda1-4c71-93e8-8e2337cee028
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529821235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.529821235
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2879345186
Short name T388
Test name
Test status
Simulation time 13665306261 ps
CPU time 1118.57 seconds
Started Jun 30 05:20:00 PM PDT 24
Finished Jun 30 05:38:39 PM PDT 24
Peak memory 282120 kb
Host smart-b6bd265b-a7dc-4c28-a3a8-17cdd46ea14f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879345186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2879345186
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2435324380
Short name T20
Test name
Test status
Simulation time 4507611043 ps
CPU time 72.2 seconds
Started Jun 30 05:20:03 PM PDT 24
Finished Jun 30 05:21:15 PM PDT 24
Peak memory 257356 kb
Host smart-1391e10a-8f59-4bfd-9b5c-636a58d9eb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353
24380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2435324380
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.751449212
Short name T58
Test name
Test status
Simulation time 185437290 ps
CPU time 16.48 seconds
Started Jun 30 05:20:01 PM PDT 24
Finished Jun 30 05:20:17 PM PDT 24
Peak memory 249276 kb
Host smart-4becddfa-ed1c-4395-b83a-9f2e336e5618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75144
9212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.751449212
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.715192889
Short name T619
Test name
Test status
Simulation time 702866876 ps
CPU time 32.05 seconds
Started Jun 30 05:20:01 PM PDT 24
Finished Jun 30 05:20:34 PM PDT 24
Peak memory 257428 kb
Host smart-8e7a5608-bf03-40bc-8439-6cd3fcafa22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71519
2889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.715192889
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1324876266
Short name T77
Test name
Test status
Simulation time 170636963134 ps
CPU time 2880.67 seconds
Started Jun 30 05:20:03 PM PDT 24
Finished Jun 30 06:08:04 PM PDT 24
Peak memory 297940 kb
Host smart-9d2e7338-3bc5-42ce-a1a2-485c1dbe240a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324876266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1324876266
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3242166629
Short name T86
Test name
Test status
Simulation time 43959989270 ps
CPU time 1099.14 seconds
Started Jun 30 05:20:03 PM PDT 24
Finished Jun 30 05:38:23 PM PDT 24
Peak memory 273948 kb
Host smart-8401aac4-216d-4b04-b97a-f49d507b378b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242166629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3242166629
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.210052176
Short name T461
Test name
Test status
Simulation time 20716594708 ps
CPU time 273.26 seconds
Started Jun 30 05:20:02 PM PDT 24
Finished Jun 30 05:24:36 PM PDT 24
Peak memory 257580 kb
Host smart-fe59dd66-cef2-49c7-bb74-d41d0910a79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21005
2176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.210052176
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1147519978
Short name T613
Test name
Test status
Simulation time 2375305849 ps
CPU time 44.37 seconds
Started Jun 30 05:20:06 PM PDT 24
Finished Jun 30 05:20:51 PM PDT 24
Peak memory 257140 kb
Host smart-ec2cc229-df92-4f19-a019-70f72a587273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11475
19978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1147519978
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2020843225
Short name T632
Test name
Test status
Simulation time 44312795305 ps
CPU time 1641.47 seconds
Started Jun 30 05:20:02 PM PDT 24
Finished Jun 30 05:47:24 PM PDT 24
Peak memory 273960 kb
Host smart-885b8561-c66d-4fa5-8fba-119e1178596a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020843225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2020843225
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3322366194
Short name T659
Test name
Test status
Simulation time 82426212332 ps
CPU time 1338.31 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:42:41 PM PDT 24
Peak memory 272828 kb
Host smart-863f8050-114d-4b93-aff2-16a2d6b4750f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322366194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3322366194
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3999620408
Short name T621
Test name
Test status
Simulation time 7875259547 ps
CPU time 315.52 seconds
Started Jun 30 05:20:02 PM PDT 24
Finished Jun 30 05:25:18 PM PDT 24
Peak memory 249188 kb
Host smart-da914b04-327b-48e0-8580-01ec83b678fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999620408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3999620408
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.941656507
Short name T702
Test name
Test status
Simulation time 304385929 ps
CPU time 6.72 seconds
Started Jun 30 05:20:02 PM PDT 24
Finished Jun 30 05:20:09 PM PDT 24
Peak memory 249224 kb
Host smart-607a0496-ba25-4d60-9067-0c16d880f357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94165
6507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.941656507
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.398653862
Short name T538
Test name
Test status
Simulation time 1074748009 ps
CPU time 26.87 seconds
Started Jun 30 05:20:05 PM PDT 24
Finished Jun 30 05:20:32 PM PDT 24
Peak memory 249292 kb
Host smart-df14df9e-1417-4aae-beb3-ee5a33adaaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39865
3862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.398653862
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4031787193
Short name T460
Test name
Test status
Simulation time 238116066 ps
CPU time 26.76 seconds
Started Jun 30 05:20:01 PM PDT 24
Finished Jun 30 05:20:29 PM PDT 24
Peak memory 256708 kb
Host smart-5a7e3408-6adf-483b-a8c4-0d62c7a9e0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40317
87193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4031787193
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.503333148
Short name T684
Test name
Test status
Simulation time 1135097120 ps
CPU time 8.68 seconds
Started Jun 30 05:20:00 PM PDT 24
Finished Jun 30 05:20:09 PM PDT 24
Peak memory 249252 kb
Host smart-50136b4c-53b8-44b4-8f84-211d97ac842c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50333
3148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.503333148
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4177997011
Short name T210
Test name
Test status
Simulation time 62363751 ps
CPU time 3.58 seconds
Started Jun 30 05:19:09 PM PDT 24
Finished Jun 30 05:19:15 PM PDT 24
Peak memory 249512 kb
Host smart-da53dc91-c48a-497d-8e68-caac204d2a56
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4177997011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4177997011
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1509497095
Short name T679
Test name
Test status
Simulation time 34365127191 ps
CPU time 1170.14 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:38:32 PM PDT 24
Peak memory 283488 kb
Host smart-ee6a6d12-a9c3-44ed-b51c-9b41bcabb582
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509497095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1509497095
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1781653479
Short name T699
Test name
Test status
Simulation time 10829739856 ps
CPU time 77.72 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:20:26 PM PDT 24
Peak memory 249300 kb
Host smart-93fa8c80-ffb6-4d78-a189-a80e7b1f6777
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1781653479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1781653479
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.4068238147
Short name T233
Test name
Test status
Simulation time 984408947 ps
CPU time 83.7 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:20:34 PM PDT 24
Peak memory 256720 kb
Host smart-9f028aa9-6701-4063-9406-56b69393a299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40682
38147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.4068238147
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3745344989
Short name T550
Test name
Test status
Simulation time 368781910 ps
CPU time 34.15 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:40 PM PDT 24
Peak memory 256828 kb
Host smart-65170b5b-3576-4aac-af1b-77f91e1e686b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37453
44989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3745344989
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1367759699
Short name T324
Test name
Test status
Simulation time 49767775256 ps
CPU time 1652.5 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:46:39 PM PDT 24
Peak memory 273028 kb
Host smart-a51a65a5-d022-4b83-9da2-20fc9db3e28b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367759699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1367759699
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3815847310
Short name T584
Test name
Test status
Simulation time 17541558203 ps
CPU time 1336.9 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:41:24 PM PDT 24
Peak memory 289964 kb
Host smart-8dadda6c-fd62-467b-963c-2239244823fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815847310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3815847310
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1738037883
Short name T298
Test name
Test status
Simulation time 23353255270 ps
CPU time 240.87 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:23:11 PM PDT 24
Peak memory 249364 kb
Host smart-aaf234d6-c9bd-408c-91d6-09fc39491752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738037883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1738037883
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1967941577
Short name T260
Test name
Test status
Simulation time 478220529 ps
CPU time 11.8 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:18 PM PDT 24
Peak memory 249256 kb
Host smart-c72fe742-9c47-49db-b948-2a808c65001a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19679
41577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1967941577
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4110380386
Short name T87
Test name
Test status
Simulation time 1222281784 ps
CPU time 26.99 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:33 PM PDT 24
Peak memory 257000 kb
Host smart-a0136c9d-2795-4903-ac0c-c6530b6e8075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41103
80386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4110380386
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3348897747
Short name T41
Test name
Test status
Simulation time 424069275 ps
CPU time 24.56 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:19:35 PM PDT 24
Peak memory 272484 kb
Host smart-a5ae5a4d-cba9-44cd-ad84-cc4d87a136b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3348897747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3348897747
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.4096036636
Short name T246
Test name
Test status
Simulation time 283256948 ps
CPU time 33.71 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:40 PM PDT 24
Peak memory 256528 kb
Host smart-d2f170ab-1557-467b-b604-07a9182a0ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40960
36636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.4096036636
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1400423705
Short name T458
Test name
Test status
Simulation time 794513059 ps
CPU time 55.76 seconds
Started Jun 30 05:19:05 PM PDT 24
Finished Jun 30 05:20:05 PM PDT 24
Peak memory 257408 kb
Host smart-e40c65f5-6d37-4874-9d33-bad4bb9d7c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14004
23705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1400423705
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4137167097
Short name T75
Test name
Test status
Simulation time 291209141741 ps
CPU time 4265.14 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 06:30:13 PM PDT 24
Peak memory 306252 kb
Host smart-2a8847fd-26e5-4fb1-a698-60a540445ee6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137167097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4137167097
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1318626295
Short name T418
Test name
Test status
Simulation time 30472499751 ps
CPU time 1700.09 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:48:42 PM PDT 24
Peak memory 284196 kb
Host smart-edef5b20-585d-463d-ab68-891e9d8cdade
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318626295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1318626295
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.803911389
Short name T687
Test name
Test status
Simulation time 2809793702 ps
CPU time 46.33 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:21:07 PM PDT 24
Peak memory 257380 kb
Host smart-5ad3680c-579f-430e-897b-4aa9c76c917d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80391
1389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.803911389
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.992863320
Short name T81
Test name
Test status
Simulation time 933805113 ps
CPU time 32.83 seconds
Started Jun 30 05:20:18 PM PDT 24
Finished Jun 30 05:20:51 PM PDT 24
Peak memory 249660 kb
Host smart-39cdedf1-884c-42ba-b712-437343c8771d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99286
3320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.992863320
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1582121179
Short name T336
Test name
Test status
Simulation time 76352380972 ps
CPU time 2171.4 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:56:34 PM PDT 24
Peak memory 273836 kb
Host smart-5733e85d-04c7-456d-824a-0b3bca406cbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582121179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1582121179
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3796662475
Short name T450
Test name
Test status
Simulation time 178321707887 ps
CPU time 1720.42 seconds
Started Jun 30 05:20:19 PM PDT 24
Finished Jun 30 05:49:00 PM PDT 24
Peak memory 273932 kb
Host smart-d92382c6-4a7f-466b-b870-9614ff367a93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796662475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3796662475
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1241932182
Short name T529
Test name
Test status
Simulation time 39598453565 ps
CPU time 456.22 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:27:58 PM PDT 24
Peak memory 249376 kb
Host smart-972fee19-839c-48f6-ab30-8fa21618a9ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241932182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1241932182
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3483032906
Short name T436
Test name
Test status
Simulation time 1528847157 ps
CPU time 41.34 seconds
Started Jun 30 05:20:25 PM PDT 24
Finished Jun 30 05:21:06 PM PDT 24
Peak memory 256592 kb
Host smart-0e26a9ef-d163-4efd-b94e-75d21d6df642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34830
32906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3483032906
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3857278473
Short name T655
Test name
Test status
Simulation time 118903342 ps
CPU time 4.37 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:20:27 PM PDT 24
Peak memory 240416 kb
Host smart-10eeada4-4d01-4a03-aaa0-d48f736f4229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38572
78473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3857278473
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1685482321
Short name T536
Test name
Test status
Simulation time 3357680661 ps
CPU time 49.18 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:21:12 PM PDT 24
Peak memory 257348 kb
Host smart-7f3008d1-3dc3-4ca8-b155-204c9807c78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16854
82321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1685482321
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4221086097
Short name T59
Test name
Test status
Simulation time 41258534849 ps
CPU time 1632.62 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:47:35 PM PDT 24
Peak memory 306792 kb
Host smart-2cc7b89b-1070-446e-89f0-f353bcff01ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221086097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4221086097
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2882140098
Short name T649
Test name
Test status
Simulation time 17451147378 ps
CPU time 1120.48 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:39:03 PM PDT 24
Peak memory 282100 kb
Host smart-e62345d4-5fd4-4125-ad40-3d80cb51d59f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882140098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2882140098
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.713459351
Short name T27
Test name
Test status
Simulation time 2012666644 ps
CPU time 176.97 seconds
Started Jun 30 05:20:19 PM PDT 24
Finished Jun 30 05:23:16 PM PDT 24
Peak memory 256972 kb
Host smart-319bbe37-e481-4bf2-b20b-53c5a3f99a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71345
9351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.713459351
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1554514955
Short name T215
Test name
Test status
Simulation time 148827297 ps
CPU time 10.59 seconds
Started Jun 30 05:20:23 PM PDT 24
Finished Jun 30 05:20:34 PM PDT 24
Peak memory 249240 kb
Host smart-cff2eb47-0095-4192-b9d7-3152c3397a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15545
14955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1554514955
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.4171138964
Short name T525
Test name
Test status
Simulation time 10004330795 ps
CPU time 913.02 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:35:34 PM PDT 24
Peak memory 273240 kb
Host smart-298129bb-0b69-4461-b0da-8531432b23cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171138964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.4171138964
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1487779227
Short name T565
Test name
Test status
Simulation time 8426672457 ps
CPU time 933.59 seconds
Started Jun 30 05:20:23 PM PDT 24
Finished Jun 30 05:35:57 PM PDT 24
Peak memory 271888 kb
Host smart-4a2d3219-f6a4-4b9f-9617-24141e17dc20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487779227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1487779227
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3096737117
Short name T706
Test name
Test status
Simulation time 4661374843 ps
CPU time 189.7 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:23:33 PM PDT 24
Peak memory 249452 kb
Host smart-7ff1a7cc-7881-4d68-924b-c00cfde41bd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096737117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3096737117
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2623413731
Short name T349
Test name
Test status
Simulation time 1180361813 ps
CPU time 35.11 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:20:57 PM PDT 24
Peak memory 256604 kb
Host smart-797b9593-328c-49c4-87a1-1270fbc157ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26234
13731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2623413731
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1217152443
Short name T564
Test name
Test status
Simulation time 320727664 ps
CPU time 27.71 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:20:50 PM PDT 24
Peak memory 249288 kb
Host smart-f4708ad0-9af2-4250-8a0a-6da8c9985e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12171
52443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1217152443
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1033812255
Short name T435
Test name
Test status
Simulation time 471618697 ps
CPU time 5.18 seconds
Started Jun 30 05:20:29 PM PDT 24
Finished Jun 30 05:20:35 PM PDT 24
Peak memory 240344 kb
Host smart-4b905e25-23fb-459e-8b15-fe3a6bbaa212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
12255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1033812255
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1589110909
Short name T357
Test name
Test status
Simulation time 1476839514 ps
CPU time 32.46 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:20:53 PM PDT 24
Peak memory 256400 kb
Host smart-60ae9d8f-8971-4884-af83-8c36b7e9a32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15891
10909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1589110909
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2461271328
Short name T561
Test name
Test status
Simulation time 11037572439 ps
CPU time 1268.47 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:41:31 PM PDT 24
Peak memory 282160 kb
Host smart-73d72415-a7b1-4070-b1fe-6904745ad21e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461271328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2461271328
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1862433029
Short name T173
Test name
Test status
Simulation time 40681587629 ps
CPU time 1600.03 seconds
Started Jun 30 05:20:25 PM PDT 24
Finished Jun 30 05:47:05 PM PDT 24
Peak memory 288088 kb
Host smart-82e97bec-1775-486c-8eda-989606a2fa5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862433029 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1862433029
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4042609581
Short name T515
Test name
Test status
Simulation time 32947448245 ps
CPU time 1434.24 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:44:16 PM PDT 24
Peak memory 289092 kb
Host smart-f3bdf74f-3e11-4ce3-a7f6-3afb01916ac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042609581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4042609581
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2228423726
Short name T189
Test name
Test status
Simulation time 13545341409 ps
CPU time 229.14 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:24:09 PM PDT 24
Peak memory 257028 kb
Host smart-f76aaa9f-b536-4a3c-bad2-7c5eda964376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22284
23726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2228423726
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3219694671
Short name T70
Test name
Test status
Simulation time 136081498 ps
CPU time 16.99 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:20:40 PM PDT 24
Peak memory 256968 kb
Host smart-bf8cb4c8-e70e-4892-b8a3-d4445f955570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32196
94671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3219694671
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3702817040
Short name T281
Test name
Test status
Simulation time 58548316850 ps
CPU time 1470.72 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:44:52 PM PDT 24
Peak memory 290212 kb
Host smart-1e929346-a43b-4e12-9ce2-adeab632583a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702817040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3702817040
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4198193565
Short name T591
Test name
Test status
Simulation time 12048398799 ps
CPU time 1119.1 seconds
Started Jun 30 05:20:23 PM PDT 24
Finished Jun 30 05:39:02 PM PDT 24
Peak memory 273836 kb
Host smart-65e7e789-ad8c-4c75-85ef-c7ebb98e08d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198193565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4198193565
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2629909980
Short name T285
Test name
Test status
Simulation time 67918423679 ps
CPU time 664.51 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:31:27 PM PDT 24
Peak memory 249380 kb
Host smart-3e20431e-7587-4e2f-accf-7bdaacb8df09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629909980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2629909980
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1490502059
Short name T707
Test name
Test status
Simulation time 521344925 ps
CPU time 12.19 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:20:33 PM PDT 24
Peak memory 249164 kb
Host smart-ef899075-b3ee-4995-afab-fc95cebe4f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14905
02059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1490502059
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3797419532
Short name T494
Test name
Test status
Simulation time 228983945 ps
CPU time 20.93 seconds
Started Jun 30 05:20:28 PM PDT 24
Finished Jun 30 05:20:50 PM PDT 24
Peak memory 249308 kb
Host smart-168055d9-6aeb-473a-894b-4a625ec0599d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37974
19532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3797419532
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1949570506
Short name T469
Test name
Test status
Simulation time 60745669 ps
CPU time 2.82 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:20:24 PM PDT 24
Peak memory 240408 kb
Host smart-1e7a270b-9149-47d5-86e2-2aa1091dd3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
70506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1949570506
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.111268185
Short name T187
Test name
Test status
Simulation time 507244910 ps
CPU time 25.3 seconds
Started Jun 30 05:20:24 PM PDT 24
Finished Jun 30 05:20:50 PM PDT 24
Peak memory 249216 kb
Host smart-f8cc8cba-0745-49ee-b2b8-15dfe00e5dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11126
8185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.111268185
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.4251852092
Short name T549
Test name
Test status
Simulation time 81377455225 ps
CPU time 2261.89 seconds
Started Jun 30 05:20:22 PM PDT 24
Finished Jun 30 05:58:05 PM PDT 24
Peak memory 282168 kb
Host smart-56ab08e7-457c-4ec0-9714-2ddff29a4128
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251852092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.4251852092
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.796485226
Short name T44
Test name
Test status
Simulation time 39300131293 ps
CPU time 4297.23 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 06:31:59 PM PDT 24
Peak memory 339492 kb
Host smart-0a6c9c68-244e-459b-a479-7234f7bc62a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796485226 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.796485226
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.947997254
Short name T574
Test name
Test status
Simulation time 37605902813 ps
CPU time 2545.17 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 06:02:47 PM PDT 24
Peak memory 289952 kb
Host smart-4879cd75-43f0-4840-affb-bac9935bb364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947997254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.947997254
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2955529887
Short name T510
Test name
Test status
Simulation time 1180633497 ps
CPU time 71.63 seconds
Started Jun 30 05:20:23 PM PDT 24
Finished Jun 30 05:21:35 PM PDT 24
Peak memory 256556 kb
Host smart-adf234fe-3e1f-4087-8a3c-041bb6cd6c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
29887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2955529887
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.294547786
Short name T573
Test name
Test status
Simulation time 334509635 ps
CPU time 42.87 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:21:03 PM PDT 24
Peak memory 249256 kb
Host smart-1174bd3d-e90b-4187-a105-d3ba883bdc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29454
7786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.294547786
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1198628652
Short name T179
Test name
Test status
Simulation time 28002829686 ps
CPU time 843.53 seconds
Started Jun 30 05:20:29 PM PDT 24
Finished Jun 30 05:34:33 PM PDT 24
Peak memory 273952 kb
Host smart-e927f5f0-0bba-4dab-9df2-08be6bc0da16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198628652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1198628652
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3893690575
Short name T288
Test name
Test status
Simulation time 90902267429 ps
CPU time 417.91 seconds
Started Jun 30 05:20:24 PM PDT 24
Finished Jun 30 05:27:22 PM PDT 24
Peak memory 248948 kb
Host smart-67bc17aa-1f7c-4c13-8bce-4c6b3733d46d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893690575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3893690575
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1780255175
Short name T540
Test name
Test status
Simulation time 537625633 ps
CPU time 43.17 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:21:05 PM PDT 24
Peak memory 249264 kb
Host smart-41c4c771-fef8-4410-a55e-1866b065696b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17802
55175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1780255175
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1041700528
Short name T586
Test name
Test status
Simulation time 3556707672 ps
CPU time 33.12 seconds
Started Jun 30 05:20:20 PM PDT 24
Finished Jun 30 05:20:54 PM PDT 24
Peak memory 248688 kb
Host smart-6200fa56-4643-44d0-bded-424048e7d27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10417
00528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1041700528
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2341329668
Short name T417
Test name
Test status
Simulation time 134942200 ps
CPU time 7.5 seconds
Started Jun 30 05:20:24 PM PDT 24
Finished Jun 30 05:20:32 PM PDT 24
Peak memory 249564 kb
Host smart-6e4ff1cd-a38f-43fe-a6bf-c52f11b6a5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
29668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2341329668
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2616378781
Short name T556
Test name
Test status
Simulation time 3709314401 ps
CPU time 42.84 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:21:05 PM PDT 24
Peak memory 249852 kb
Host smart-9e7dc340-c1bd-4295-a625-cb280f1f6d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26163
78781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2616378781
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.545093880
Short name T673
Test name
Test status
Simulation time 36365571524 ps
CPU time 1476.36 seconds
Started Jun 30 05:20:21 PM PDT 24
Finished Jun 30 05:44:59 PM PDT 24
Peak memory 289676 kb
Host smart-fa6de859-cac1-46b8-a43c-0a9cc3b19b67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545093880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.545093880
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1604658386
Short name T516
Test name
Test status
Simulation time 73682493429 ps
CPU time 712.88 seconds
Started Jun 30 05:20:24 PM PDT 24
Finished Jun 30 05:32:17 PM PDT 24
Peak memory 268832 kb
Host smart-f1f67738-c710-43d7-9f39-475bc162e74d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604658386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1604658386
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2077280762
Short name T671
Test name
Test status
Simulation time 6948904865 ps
CPU time 95.26 seconds
Started Jun 30 05:20:24 PM PDT 24
Finished Jun 30 05:21:59 PM PDT 24
Peak memory 257048 kb
Host smart-d396c6f1-8c10-4c04-820c-a87270254b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
80762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2077280762
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3326195682
Short name T537
Test name
Test status
Simulation time 2908103370 ps
CPU time 49.97 seconds
Started Jun 30 05:20:24 PM PDT 24
Finished Jun 30 05:21:15 PM PDT 24
Peak memory 256864 kb
Host smart-d154639f-6e95-4ab6-97bd-b82a5ca7c0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33261
95682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3326195682
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1856159822
Short name T5
Test name
Test status
Simulation time 84429785718 ps
CPU time 1542.37 seconds
Started Jun 30 05:20:30 PM PDT 24
Finished Jun 30 05:46:13 PM PDT 24
Peak memory 273876 kb
Host smart-d110315e-623f-4694-84a6-1aec49b5f061
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856159822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1856159822
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.735508838
Short name T291
Test name
Test status
Simulation time 12526182140 ps
CPU time 284.54 seconds
Started Jun 30 05:20:25 PM PDT 24
Finished Jun 30 05:25:10 PM PDT 24
Peak memory 255916 kb
Host smart-f1d9398f-87fd-45e7-a2ea-71d1f4f740a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735508838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.735508838
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2821141009
Short name T177
Test name
Test status
Simulation time 539010011 ps
CPU time 42.63 seconds
Started Jun 30 05:20:24 PM PDT 24
Finished Jun 30 05:21:08 PM PDT 24
Peak memory 256432 kb
Host smart-f68b5ea6-baba-411b-97c3-8626f11840ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28211
41009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2821141009
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3434129600
Short name T552
Test name
Test status
Simulation time 227216053 ps
CPU time 24.2 seconds
Started Jun 30 05:20:30 PM PDT 24
Finished Jun 30 05:20:55 PM PDT 24
Peak memory 249280 kb
Host smart-9f238281-eaf2-4a86-b74f-8065b015e81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34341
29600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3434129600
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.4272897184
Short name T625
Test name
Test status
Simulation time 231913138 ps
CPU time 16.9 seconds
Started Jun 30 05:20:26 PM PDT 24
Finished Jun 30 05:20:44 PM PDT 24
Peak memory 255692 kb
Host smart-15258f77-99e7-48e7-9330-0cf52f93fd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42728
97184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.4272897184
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2118655669
Short name T704
Test name
Test status
Simulation time 960148261 ps
CPU time 34.46 seconds
Started Jun 30 05:20:26 PM PDT 24
Finished Jun 30 05:21:01 PM PDT 24
Peak memory 256444 kb
Host smart-38244b08-4f1b-48d0-83f4-7da5b2397e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21186
55669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2118655669
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.581299671
Short name T350
Test name
Test status
Simulation time 414175709836 ps
CPU time 2462.56 seconds
Started Jun 30 05:20:29 PM PDT 24
Finished Jun 30 06:01:32 PM PDT 24
Peak memory 289532 kb
Host smart-ea471f4a-ae56-4b8f-89ca-03ea0d8d7de6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581299671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.581299671
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1555883902
Short name T600
Test name
Test status
Simulation time 167582102810 ps
CPU time 3975.32 seconds
Started Jun 30 05:20:26 PM PDT 24
Finished Jun 30 06:26:42 PM PDT 24
Peak memory 334532 kb
Host smart-e59a7734-7c60-4f60-bca6-d32f53437be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555883902 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1555883902
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3791938594
Short name T264
Test name
Test status
Simulation time 15195875111 ps
CPU time 1443.02 seconds
Started Jun 30 05:20:30 PM PDT 24
Finished Jun 30 05:44:34 PM PDT 24
Peak memory 289296 kb
Host smart-0951221b-cfc6-47ab-9eee-0eb8da73ff6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791938594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3791938594
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1893090875
Short name T471
Test name
Test status
Simulation time 6093541919 ps
CPU time 94.87 seconds
Started Jun 30 05:20:28 PM PDT 24
Finished Jun 30 05:22:03 PM PDT 24
Peak memory 257200 kb
Host smart-951ad79e-97a6-4d3f-b8a1-6443567c9a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18930
90875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1893090875
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.402717410
Short name T532
Test name
Test status
Simulation time 354476050 ps
CPU time 29.75 seconds
Started Jun 30 05:20:28 PM PDT 24
Finished Jun 30 05:20:58 PM PDT 24
Peak memory 257332 kb
Host smart-0d5914c8-2874-4a77-a91e-9fe7a90ff4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40271
7410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.402717410
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3838882505
Short name T326
Test name
Test status
Simulation time 39906985302 ps
CPU time 1116.9 seconds
Started Jun 30 05:20:31 PM PDT 24
Finished Jun 30 05:39:08 PM PDT 24
Peak memory 273964 kb
Host smart-87ffe186-3862-4027-be3b-55b9afc1d2e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838882505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3838882505
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3570571026
Short name T612
Test name
Test status
Simulation time 17051981019 ps
CPU time 974.7 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:36:48 PM PDT 24
Peak memory 290056 kb
Host smart-2d127303-5e55-4c21-a70f-7ba16942d136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570571026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3570571026
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.255605927
Short name T301
Test name
Test status
Simulation time 12071591394 ps
CPU time 497.62 seconds
Started Jun 30 05:20:32 PM PDT 24
Finished Jun 30 05:28:50 PM PDT 24
Peak memory 249332 kb
Host smart-a35a2a82-1997-4707-8c9b-9cf447d5f2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255605927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.255605927
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1278492548
Short name T634
Test name
Test status
Simulation time 652401606 ps
CPU time 36.62 seconds
Started Jun 30 05:20:23 PM PDT 24
Finished Jun 30 05:21:00 PM PDT 24
Peak memory 256464 kb
Host smart-99ebaf0e-9264-4e29-a268-ccd38f5f4b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12784
92548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1278492548
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2896459225
Short name T35
Test name
Test status
Simulation time 1623255706 ps
CPU time 58.4 seconds
Started Jun 30 05:20:28 PM PDT 24
Finished Jun 30 05:21:27 PM PDT 24
Peak memory 249568 kb
Host smart-1dab2f7a-daa5-403b-a2bc-32fd630fe1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28964
59225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2896459225
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.464377847
Short name T631
Test name
Test status
Simulation time 630122659 ps
CPU time 38.1 seconds
Started Jun 30 05:20:29 PM PDT 24
Finished Jun 30 05:21:07 PM PDT 24
Peak memory 257312 kb
Host smart-b9901d8e-5759-41fe-a294-262424f72410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46437
7847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.464377847
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2367940533
Short name T37
Test name
Test status
Simulation time 101451545505 ps
CPU time 1812.12 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:50:46 PM PDT 24
Peak memory 282488 kb
Host smart-94468bbb-7c3f-4614-bce1-e27fa129c60d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367940533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2367940533
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.267132740
Short name T554
Test name
Test status
Simulation time 32604773347 ps
CPU time 1795.87 seconds
Started Jun 30 05:20:35 PM PDT 24
Finished Jun 30 05:50:31 PM PDT 24
Peak memory 290220 kb
Host smart-ceeee4cf-c3e3-4c97-a324-83d63897a5e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267132740 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.267132740
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.512037063
Short name T572
Test name
Test status
Simulation time 179535378099 ps
CPU time 1074.17 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:38:28 PM PDT 24
Peak memory 265796 kb
Host smart-1b4ead41-b096-4034-baa1-dff1c4948dd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512037063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.512037063
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.92825946
Short name T190
Test name
Test status
Simulation time 489548618 ps
CPU time 9.92 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:20:44 PM PDT 24
Peak memory 255156 kb
Host smart-49616e1c-24a4-4a32-8864-2157d8baa1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92825
946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.92825946
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1167309507
Short name T703
Test name
Test status
Simulation time 1353442227 ps
CPU time 64.23 seconds
Started Jun 30 05:20:32 PM PDT 24
Finished Jun 30 05:21:36 PM PDT 24
Peak memory 248720 kb
Host smart-14a7024c-31a0-4846-a01f-578f41861cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11673
09507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1167309507
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3996191427
Short name T7
Test name
Test status
Simulation time 8502927119 ps
CPU time 731.16 seconds
Started Jun 30 05:20:32 PM PDT 24
Finished Jun 30 05:32:44 PM PDT 24
Peak memory 272004 kb
Host smart-a56ecef1-ba55-4356-9684-41e2d44ce4b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996191427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3996191427
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3714128873
Short name T296
Test name
Test status
Simulation time 93740720266 ps
CPU time 180.79 seconds
Started Jun 30 05:20:34 PM PDT 24
Finished Jun 30 05:23:35 PM PDT 24
Peak memory 249088 kb
Host smart-a49e319a-46f3-472c-a593-671535e43498
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714128873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3714128873
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3788916362
Short name T658
Test name
Test status
Simulation time 142579000 ps
CPU time 3.94 seconds
Started Jun 30 05:20:34 PM PDT 24
Finished Jun 30 05:20:38 PM PDT 24
Peak memory 241016 kb
Host smart-6affcc61-7c1f-43c1-8ef2-166a944f438e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
16362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3788916362
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1209102484
Short name T562
Test name
Test status
Simulation time 522948926 ps
CPU time 22.94 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:20:56 PM PDT 24
Peak memory 257004 kb
Host smart-a0e44c58-5df1-4fec-ad98-39975d280edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12091
02484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1209102484
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.42518574
Short name T577
Test name
Test status
Simulation time 574659565 ps
CPU time 37.51 seconds
Started Jun 30 05:20:32 PM PDT 24
Finished Jun 30 05:21:10 PM PDT 24
Peak memory 249228 kb
Host smart-5cd27122-aba4-41f2-8877-7de96c561e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42518
574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.42518574
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3088204828
Short name T398
Test name
Test status
Simulation time 321705647 ps
CPU time 23.5 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:20:57 PM PDT 24
Peak memory 257416 kb
Host smart-d85ba42a-aeb0-4ab4-8624-93fd6a0faaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30882
04828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3088204828
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2976037981
Short name T628
Test name
Test status
Simulation time 153957843476 ps
CPU time 2444.48 seconds
Started Jun 30 05:20:32 PM PDT 24
Finished Jun 30 06:01:17 PM PDT 24
Peak memory 282136 kb
Host smart-55e16d91-3482-4929-b712-b1bc0dfe0fe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976037981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2976037981
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2806169278
Short name T648
Test name
Test status
Simulation time 3987543305 ps
CPU time 232.53 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:24:27 PM PDT 24
Peak memory 257588 kb
Host smart-3370ccfc-3cfa-4f7b-b09f-9f2468143660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28061
69278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2806169278
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3894801081
Short name T583
Test name
Test status
Simulation time 4759424091 ps
CPU time 73.85 seconds
Started Jun 30 05:20:34 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 257356 kb
Host smart-8276e891-1643-4cb4-ad93-81b2cd9a0d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38948
01081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3894801081
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.52954286
Short name T646
Test name
Test status
Simulation time 17604675723 ps
CPU time 1417.49 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:44:12 PM PDT 24
Peak memory 286372 kb
Host smart-48580d01-69de-4471-82f2-be4f67455468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52954286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.52954286
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1201492981
Short name T651
Test name
Test status
Simulation time 35930046088 ps
CPU time 1689.52 seconds
Started Jun 30 05:20:35 PM PDT 24
Finished Jun 30 05:48:45 PM PDT 24
Peak memory 282900 kb
Host smart-d312828f-a66c-4de2-9ab2-d069cf567f27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201492981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1201492981
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2763009743
Short name T316
Test name
Test status
Simulation time 17944363670 ps
CPU time 392.1 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:27:05 PM PDT 24
Peak memory 249628 kb
Host smart-3c9c5a38-ee25-4d55-873b-ac604402882e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763009743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2763009743
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.321782906
Short name T380
Test name
Test status
Simulation time 21481774244 ps
CPU time 72.92 seconds
Started Jun 30 05:20:34 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 257548 kb
Host smart-fe52859a-e782-44d6-9e69-c60751c62e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32178
2906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.321782906
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1715773871
Short name T585
Test name
Test status
Simulation time 170109376 ps
CPU time 8.44 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:20:42 PM PDT 24
Peak memory 252328 kb
Host smart-ab1fad05-cedc-4e79-9eb5-782e32980ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17157
73871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1715773871
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2526660128
Short name T661
Test name
Test status
Simulation time 1455224051 ps
CPU time 24.94 seconds
Started Jun 30 05:20:33 PM PDT 24
Finished Jun 30 05:20:58 PM PDT 24
Peak memory 256356 kb
Host smart-033890ca-8aeb-4e9d-8c93-5c0bc098cc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25266
60128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2526660128
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.4155416817
Short name T29
Test name
Test status
Simulation time 5736381268 ps
CPU time 80.35 seconds
Started Jun 30 05:20:34 PM PDT 24
Finished Jun 30 05:21:55 PM PDT 24
Peak memory 249340 kb
Host smart-8651aa33-4518-4cd4-8494-41e8522c05e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41554
16817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.4155416817
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1699580423
Short name T97
Test name
Test status
Simulation time 79369544699 ps
CPU time 2313.4 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:59:13 PM PDT 24
Peak memory 284752 kb
Host smart-c06fca95-b220-4dcc-8ffc-ff72fba09e3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699580423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1699580423
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2579070357
Short name T480
Test name
Test status
Simulation time 39426968402 ps
CPU time 2150.71 seconds
Started Jun 30 05:20:45 PM PDT 24
Finished Jun 30 05:56:36 PM PDT 24
Peak memory 280788 kb
Host smart-7cd7323a-aedd-4f26-8ab3-555daf0df9a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579070357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2579070357
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4106680254
Short name T479
Test name
Test status
Simulation time 3271286667 ps
CPU time 48.31 seconds
Started Jun 30 05:20:44 PM PDT 24
Finished Jun 30 05:21:33 PM PDT 24
Peak memory 257400 kb
Host smart-438502b7-8452-4761-b6d0-935a84b648ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41066
80254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4106680254
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1678212087
Short name T493
Test name
Test status
Simulation time 260919295 ps
CPU time 10.51 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:20:50 PM PDT 24
Peak memory 249644 kb
Host smart-0023ca36-9f60-4c9f-b787-cbd9d60fbfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
12087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1678212087
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2320144100
Short name T547
Test name
Test status
Simulation time 16863950155 ps
CPU time 1319.53 seconds
Started Jun 30 05:20:41 PM PDT 24
Finished Jun 30 05:42:41 PM PDT 24
Peak memory 285132 kb
Host smart-d18f68a0-c1a6-4827-b9dd-b1c509ef1b92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320144100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2320144100
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.140379169
Short name T644
Test name
Test status
Simulation time 48132676473 ps
CPU time 1281.57 seconds
Started Jun 30 05:20:45 PM PDT 24
Finished Jun 30 05:42:07 PM PDT 24
Peak memory 289244 kb
Host smart-6d859ffe-2766-487a-a2b0-b91830432504
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140379169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.140379169
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1604228416
Short name T217
Test name
Test status
Simulation time 5273849450 ps
CPU time 59.91 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:21:40 PM PDT 24
Peak memory 249628 kb
Host smart-f49fb1ca-e0ce-4b1b-82d4-988d1eed1fca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604228416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1604228416
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3473600550
Short name T368
Test name
Test status
Simulation time 457886885 ps
CPU time 27.07 seconds
Started Jun 30 05:20:40 PM PDT 24
Finished Jun 30 05:21:07 PM PDT 24
Peak memory 257172 kb
Host smart-babf0807-8210-4b54-b66c-044625bf9a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34736
00550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3473600550
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1059255383
Short name T617
Test name
Test status
Simulation time 2362499934 ps
CPU time 66.97 seconds
Started Jun 30 05:20:40 PM PDT 24
Finished Jun 30 05:21:48 PM PDT 24
Peak memory 257096 kb
Host smart-366b3c58-ddbe-4441-a045-af08af7289a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10592
55383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1059255383
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2800537386
Short name T636
Test name
Test status
Simulation time 1409014190 ps
CPU time 40.2 seconds
Started Jun 30 05:20:40 PM PDT 24
Finished Jun 30 05:21:20 PM PDT 24
Peak memory 256220 kb
Host smart-c2a8d725-4ead-4cae-97d7-3b048581337c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28005
37386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2800537386
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2189836648
Short name T63
Test name
Test status
Simulation time 406054815 ps
CPU time 10.32 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:20:50 PM PDT 24
Peak memory 255476 kb
Host smart-2e2359ac-1f7a-4108-9f4a-2b7b95f6ecf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21898
36648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2189836648
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.872576096
Short name T38
Test name
Test status
Simulation time 63890988466 ps
CPU time 1524.82 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:46:05 PM PDT 24
Peak memory 298024 kb
Host smart-cb6ba4fe-caf5-46e1-ac40-6ba0c90bab08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872576096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.872576096
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4001042427
Short name T701
Test name
Test status
Simulation time 182116205891 ps
CPU time 1159.42 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:40:07 PM PDT 24
Peak memory 289852 kb
Host smart-0ef832d3-0b86-4c4b-b4d5-08895e966ab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001042427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4001042427
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3581675601
Short name T232
Test name
Test status
Simulation time 1115912119 ps
CPU time 93.19 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:22:21 PM PDT 24
Peak memory 257008 kb
Host smart-549adebc-6bd4-49b9-b58e-f66ef625b175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35816
75601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3581675601
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1273986583
Short name T506
Test name
Test status
Simulation time 256534435 ps
CPU time 30.69 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:21:11 PM PDT 24
Peak memory 249804 kb
Host smart-0ee4fc82-928e-4433-93e9-02cd35dc8b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12739
86583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1273986583
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3301735314
Short name T306
Test name
Test status
Simulation time 145323122093 ps
CPU time 1965.22 seconds
Started Jun 30 05:20:46 PM PDT 24
Finished Jun 30 05:53:32 PM PDT 24
Peak memory 273788 kb
Host smart-f7fa0797-c04b-4974-bfa7-8ee1c5c6e635
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301735314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3301735314
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.289041651
Short name T593
Test name
Test status
Simulation time 23834314739 ps
CPU time 1599.44 seconds
Started Jun 30 05:20:48 PM PDT 24
Finished Jun 30 05:47:29 PM PDT 24
Peak memory 272728 kb
Host smart-98e826d8-40ed-461c-994c-c20389df58f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289041651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.289041651
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3600104232
Short name T654
Test name
Test status
Simulation time 24907468186 ps
CPU time 251.22 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:24:59 PM PDT 24
Peak memory 249360 kb
Host smart-9babf132-08e4-4f2e-b195-e484b793ac40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600104232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3600104232
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1423519054
Short name T499
Test name
Test status
Simulation time 2312485692 ps
CPU time 21.09 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:21:01 PM PDT 24
Peak memory 249380 kb
Host smart-90472a7e-3cfc-433d-9912-8b67d9b4c274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14235
19054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1423519054
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1709240616
Short name T78
Test name
Test status
Simulation time 2309554608 ps
CPU time 65.12 seconds
Started Jun 30 05:20:39 PM PDT 24
Finished Jun 30 05:21:45 PM PDT 24
Peak memory 257200 kb
Host smart-8fdc1ad7-169e-41d9-84b1-a4012c5546ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
40616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1709240616
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.130371180
Short name T225
Test name
Test status
Simulation time 70099494 ps
CPU time 3.62 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:20:52 PM PDT 24
Peak memory 249304 kb
Host smart-efdb58f3-d6e4-43d8-ba86-077f78d6f557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13037
1180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.130371180
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4140486526
Short name T261
Test name
Test status
Simulation time 3089849493 ps
CPU time 37.94 seconds
Started Jun 30 05:20:40 PM PDT 24
Finished Jun 30 05:21:18 PM PDT 24
Peak memory 256648 kb
Host smart-14b0000e-6969-4d16-b2f6-5c013f03ac73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41404
86526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4140486526
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3132634694
Short name T611
Test name
Test status
Simulation time 14044199008 ps
CPU time 570.28 seconds
Started Jun 30 05:20:46 PM PDT 24
Finished Jun 30 05:30:17 PM PDT 24
Peak memory 265792 kb
Host smart-586eea93-1a74-4e5d-b155-8861505ba7b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132634694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3132634694
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2021491776
Short name T61
Test name
Test status
Simulation time 14361116889 ps
CPU time 974.25 seconds
Started Jun 30 05:20:49 PM PDT 24
Finished Jun 30 05:37:04 PM PDT 24
Peak memory 274064 kb
Host smart-72b05321-7f6f-4bf2-8c40-2bc13c9fcc44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021491776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2021491776
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2276042959
Short name T209
Test name
Test status
Simulation time 25517647 ps
CPU time 2.45 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:19:11 PM PDT 24
Peak memory 249496 kb
Host smart-9677f0b5-105d-493f-b5e9-009d15579878
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2276042959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2276042959
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.878836743
Short name T689
Test name
Test status
Simulation time 136914224937 ps
CPU time 2111.61 seconds
Started Jun 30 05:19:04 PM PDT 24
Finished Jun 30 05:54:20 PM PDT 24
Peak memory 284624 kb
Host smart-6dfd0bbd-4c3a-4d22-aef5-a3d487368742
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878836743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.878836743
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1838206736
Short name T391
Test name
Test status
Simulation time 189737332 ps
CPU time 9.98 seconds
Started Jun 30 05:18:57 PM PDT 24
Finished Jun 30 05:19:08 PM PDT 24
Peak memory 249204 kb
Host smart-a65567a7-e138-4521-8141-c7e4724f1c31
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1838206736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1838206736
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1543660692
Short name T186
Test name
Test status
Simulation time 1423597165 ps
CPU time 94.36 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:20:38 PM PDT 24
Peak memory 256904 kb
Host smart-351e3fd6-2f1b-49bd-9ca9-0af374cef96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
60692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1543660692
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2532145451
Short name T486
Test name
Test status
Simulation time 221386497 ps
CPU time 17.93 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:19:22 PM PDT 24
Peak memory 257376 kb
Host smart-8e1cb171-26b8-4b8d-9835-23e53ccdd5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
45451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2532145451
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.781191260
Short name T308
Test name
Test status
Simulation time 93283692651 ps
CPU time 1381.98 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:42:08 PM PDT 24
Peak memory 273180 kb
Host smart-b94dd308-452b-4e71-8300-eb88f2efbc32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781191260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.781191260
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4009964237
Short name T630
Test name
Test status
Simulation time 303251032524 ps
CPU time 1413.46 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:42:47 PM PDT 24
Peak memory 273924 kb
Host smart-36d1c55a-d6fc-4ca5-9067-e4adca4c5184
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009964237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4009964237
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.656648768
Short name T292
Test name
Test status
Simulation time 7847216816 ps
CPU time 329.28 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:24:33 PM PDT 24
Peak memory 249368 kb
Host smart-5ff4cb98-5604-4ada-9d09-3a81500a2735
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656648768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.656648768
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3452690906
Short name T270
Test name
Test status
Simulation time 886757690 ps
CPU time 23.86 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:19:36 PM PDT 24
Peak memory 256800 kb
Host smart-ab23eaa9-00ad-45fd-9e4f-8c7227562c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34526
90906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3452690906
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4177017552
Short name T89
Test name
Test status
Simulation time 1518929558 ps
CPU time 32.24 seconds
Started Jun 30 05:19:05 PM PDT 24
Finished Jun 30 05:19:42 PM PDT 24
Peak memory 256460 kb
Host smart-a75829e6-f22f-4797-9275-0474d979c567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41770
17552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4177017552
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.708093026
Short name T13
Test name
Test status
Simulation time 970667919 ps
CPU time 15.53 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:19:25 PM PDT 24
Peak memory 269708 kb
Host smart-9002a170-e76f-4123-9722-e97b1103a2bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=708093026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.708093026
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.766643933
Short name T100
Test name
Test status
Simulation time 247253336 ps
CPU time 13.96 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:19:22 PM PDT 24
Peak memory 249220 kb
Host smart-c26c483b-51af-4b8a-a89a-c030a4dc8191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76664
3933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.766643933
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2116060164
Short name T65
Test name
Test status
Simulation time 4841343150 ps
CPU time 25.99 seconds
Started Jun 30 05:19:05 PM PDT 24
Finished Jun 30 05:19:36 PM PDT 24
Peak memory 257424 kb
Host smart-40bbba7d-bc4c-4e73-9639-6d96e1597c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
60164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2116060164
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.54557913
Short name T607
Test name
Test status
Simulation time 101121560733 ps
CPU time 3030.6 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 06:09:38 PM PDT 24
Peak memory 289976 kb
Host smart-9782c7f5-8835-4a47-bc72-529daa838465
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54557913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handl
er_stress_all.54557913
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1942967630
Short name T395
Test name
Test status
Simulation time 59750619858 ps
CPU time 1386.34 seconds
Started Jun 30 05:20:48 PM PDT 24
Finished Jun 30 05:43:55 PM PDT 24
Peak memory 286000 kb
Host smart-89a29527-1809-4a95-b5d2-a7085e484bfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942967630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1942967630
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3777784890
Short name T505
Test name
Test status
Simulation time 3774333932 ps
CPU time 44.21 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:21:32 PM PDT 24
Peak memory 256696 kb
Host smart-8e25f408-337e-4dd4-b609-e3fbf6317789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
84890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3777784890
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3441805992
Short name T487
Test name
Test status
Simulation time 472914341 ps
CPU time 12.59 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:21:00 PM PDT 24
Peak memory 249704 kb
Host smart-6b636822-0202-4891-9b9e-7bb36e5d7a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
05992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3441805992
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4290914824
Short name T335
Test name
Test status
Simulation time 13823525064 ps
CPU time 1099.24 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:39:07 PM PDT 24
Peak memory 283104 kb
Host smart-2590b545-c135-42e6-b360-16df5b0f36e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290914824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4290914824
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1591751736
Short name T604
Test name
Test status
Simulation time 141015500882 ps
CPU time 2275.8 seconds
Started Jun 30 05:20:46 PM PDT 24
Finished Jun 30 05:58:43 PM PDT 24
Peak memory 273952 kb
Host smart-cdd8386a-e0c9-4d20-b50c-8c62784b5aec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591751736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1591751736
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.218918430
Short name T9
Test name
Test status
Simulation time 49826624914 ps
CPU time 407.73 seconds
Started Jun 30 05:20:46 PM PDT 24
Finished Jun 30 05:27:34 PM PDT 24
Peak memory 249220 kb
Host smart-780d2162-a088-4846-9739-cc18cbd84c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218918430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.218918430
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4030574300
Short name T492
Test name
Test status
Simulation time 760927001 ps
CPU time 23.28 seconds
Started Jun 30 05:20:50 PM PDT 24
Finished Jun 30 05:21:13 PM PDT 24
Peak memory 249312 kb
Host smart-53ccef5b-6c5d-4dd0-bebf-46f5d1fb38d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40305
74300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4030574300
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3346413980
Short name T690
Test name
Test status
Simulation time 4185796543 ps
CPU time 25.56 seconds
Started Jun 30 05:20:48 PM PDT 24
Finished Jun 30 05:21:14 PM PDT 24
Peak memory 249316 kb
Host smart-b7ef3eb6-eb91-40ad-abb5-b49d7f21accc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33464
13980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3346413980
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3919311681
Short name T409
Test name
Test status
Simulation time 872885662 ps
CPU time 21.81 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:21:10 PM PDT 24
Peak memory 257468 kb
Host smart-4a2ff2cc-68a0-4952-9ac5-d27381ec2567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39193
11681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3919311681
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.939997531
Short name T259
Test name
Test status
Simulation time 48888996749 ps
CPU time 3037.64 seconds
Started Jun 30 05:20:49 PM PDT 24
Finished Jun 30 06:11:27 PM PDT 24
Peak memory 298544 kb
Host smart-2f3a1ad7-4c0f-4c05-a854-5aaeb9c84ef6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939997531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.939997531
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1317055577
Short name T99
Test name
Test status
Simulation time 55126144534 ps
CPU time 1195.96 seconds
Started Jun 30 05:20:54 PM PDT 24
Finished Jun 30 05:40:51 PM PDT 24
Peak memory 286620 kb
Host smart-9fd1304a-b9c7-404f-a83d-23d3d9c9ecc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317055577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1317055577
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2561357032
Short name T680
Test name
Test status
Simulation time 2930973766 ps
CPU time 189.19 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:23:57 PM PDT 24
Peak memory 257532 kb
Host smart-8456e8ca-be5d-4da6-83af-072ce65837b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25613
57032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2561357032
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2240749069
Short name T415
Test name
Test status
Simulation time 1060351820 ps
CPU time 59.66 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 256600 kb
Host smart-ffb26cd9-1524-4bbe-ae26-1d813b9b9115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
49069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2240749069
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2310352978
Short name T568
Test name
Test status
Simulation time 38724878236 ps
CPU time 1842.18 seconds
Started Jun 30 05:20:54 PM PDT 24
Finished Jun 30 05:51:37 PM PDT 24
Peak memory 273372 kb
Host smart-2eefa6bb-ffe2-4e4b-a203-3e58a75b652c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310352978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2310352978
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.887307639
Short name T32
Test name
Test status
Simulation time 42656103095 ps
CPU time 2379.16 seconds
Started Jun 30 05:20:56 PM PDT 24
Finished Jun 30 06:00:36 PM PDT 24
Peak memory 288504 kb
Host smart-9a2feee0-0178-4bdf-b57f-9c9e539c3f5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887307639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.887307639
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1510299015
Short name T299
Test name
Test status
Simulation time 43031532693 ps
CPU time 406.59 seconds
Started Jun 30 05:20:53 PM PDT 24
Finished Jun 30 05:27:41 PM PDT 24
Peak memory 255820 kb
Host smart-ca7572e2-ecb7-4860-975a-c0492f2429b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510299015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1510299015
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3189366918
Short name T685
Test name
Test status
Simulation time 357466492 ps
CPU time 21.05 seconds
Started Jun 30 05:20:48 PM PDT 24
Finished Jun 30 05:21:10 PM PDT 24
Peak memory 249288 kb
Host smart-4cf9ecbb-4e5f-4e05-b261-af35a40f6a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
66918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3189366918
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2505777917
Short name T606
Test name
Test status
Simulation time 290500315 ps
CPU time 28.15 seconds
Started Jun 30 05:20:48 PM PDT 24
Finished Jun 30 05:21:17 PM PDT 24
Peak memory 249220 kb
Host smart-72887d8e-fefd-4f66-902b-935213753876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25057
77917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2505777917
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3339474296
Short name T508
Test name
Test status
Simulation time 33977391 ps
CPU time 2.98 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:20:51 PM PDT 24
Peak memory 241048 kb
Host smart-4d5f0057-cafe-4ff2-ad57-fa35169d342d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33394
74296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3339474296
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1393825185
Short name T545
Test name
Test status
Simulation time 2434357965 ps
CPU time 42.41 seconds
Started Jun 30 05:20:47 PM PDT 24
Finished Jun 30 05:21:30 PM PDT 24
Peak memory 257448 kb
Host smart-f39e14e8-53cf-4c21-82da-6823917570af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13938
25185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1393825185
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.611822481
Short name T576
Test name
Test status
Simulation time 162882104581 ps
CPU time 2540.52 seconds
Started Jun 30 05:20:55 PM PDT 24
Finished Jun 30 06:03:16 PM PDT 24
Peak memory 290300 kb
Host smart-9f199c09-2c5a-4e3e-9c7c-e8d642a05d39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611822481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.611822481
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.655042525
Short name T509
Test name
Test status
Simulation time 197757479956 ps
CPU time 3574.19 seconds
Started Jun 30 05:20:55 PM PDT 24
Finished Jun 30 06:20:30 PM PDT 24
Peak memory 298604 kb
Host smart-58964990-1ebb-4fd9-8d1c-541fe862aee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655042525 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.655042525
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3767421490
Short name T693
Test name
Test status
Simulation time 35187519433 ps
CPU time 1486.59 seconds
Started Jun 30 05:20:53 PM PDT 24
Finished Jun 30 05:45:40 PM PDT 24
Peak memory 273452 kb
Host smart-312beb75-4240-4a41-85d8-222a7724351d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767421490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3767421490
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4054795671
Short name T375
Test name
Test status
Simulation time 3321305159 ps
CPU time 140.98 seconds
Started Jun 30 05:20:56 PM PDT 24
Finished Jun 30 05:23:18 PM PDT 24
Peak memory 257616 kb
Host smart-120d85f4-183b-4045-b1ce-a33ef0c52b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40547
95671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4054795671
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1766948780
Short name T555
Test name
Test status
Simulation time 93326900 ps
CPU time 7.62 seconds
Started Jun 30 05:20:54 PM PDT 24
Finished Jun 30 05:21:02 PM PDT 24
Peak memory 249132 kb
Host smart-d3d9307f-f12a-4cf3-b910-768e0745abda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17669
48780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1766948780
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.835809064
Short name T657
Test name
Test status
Simulation time 48676944245 ps
CPU time 971.03 seconds
Started Jun 30 05:20:56 PM PDT 24
Finished Jun 30 05:37:07 PM PDT 24
Peak memory 273780 kb
Host smart-e5a44690-bedc-47e4-9038-430dfb8237c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835809064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.835809064
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.761001274
Short name T397
Test name
Test status
Simulation time 7314520429 ps
CPU time 854.18 seconds
Started Jun 30 05:20:55 PM PDT 24
Finished Jun 30 05:35:10 PM PDT 24
Peak memory 273944 kb
Host smart-b1134f38-b827-4d55-95d8-d1c53cde4572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761001274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.761001274
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2332081931
Short name T297
Test name
Test status
Simulation time 45209505195 ps
CPU time 310.61 seconds
Started Jun 30 05:20:54 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 255728 kb
Host smart-f6162b52-11a5-4f57-87e6-f0b1b1186f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332081931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2332081931
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3611556009
Short name T413
Test name
Test status
Simulation time 782816244 ps
CPU time 28 seconds
Started Jun 30 05:20:55 PM PDT 24
Finished Jun 30 05:21:23 PM PDT 24
Peak memory 249236 kb
Host smart-c052aa4e-8279-4343-a762-55a393e96dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36115
56009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3611556009
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1038709338
Short name T379
Test name
Test status
Simulation time 824184199 ps
CPU time 25.24 seconds
Started Jun 30 05:20:56 PM PDT 24
Finished Jun 30 05:21:21 PM PDT 24
Peak memory 256376 kb
Host smart-785bfe75-9e62-4a0c-9366-21289c6fb470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10387
09338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1038709338
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.288486040
Short name T50
Test name
Test status
Simulation time 96888613 ps
CPU time 8.84 seconds
Started Jun 30 05:20:55 PM PDT 24
Finished Jun 30 05:21:04 PM PDT 24
Peak memory 248804 kb
Host smart-6f2ef55c-cc4a-4b93-bba1-c1988bb68c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28848
6040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.288486040
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1680096223
Short name T513
Test name
Test status
Simulation time 49157467 ps
CPU time 2.74 seconds
Started Jun 30 05:20:56 PM PDT 24
Finished Jun 30 05:20:59 PM PDT 24
Peak memory 249596 kb
Host smart-607af693-b264-4134-9963-b80ec84e1dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16800
96223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1680096223
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.568122945
Short name T95
Test name
Test status
Simulation time 112313728246 ps
CPU time 1716.56 seconds
Started Jun 30 05:20:53 PM PDT 24
Finished Jun 30 05:49:30 PM PDT 24
Peak memory 283088 kb
Host smart-9faa45f5-5862-4d10-af5e-200be7a6651d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568122945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.568122945
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3959737905
Short name T174
Test name
Test status
Simulation time 575081145723 ps
CPU time 10217.8 seconds
Started Jun 30 05:21:02 PM PDT 24
Finished Jun 30 08:11:21 PM PDT 24
Peak memory 372328 kb
Host smart-0eec51c4-6292-45f1-be96-1ce404601528
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959737905 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3959737905
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.4125804752
Short name T626
Test name
Test status
Simulation time 66551972764 ps
CPU time 1324.09 seconds
Started Jun 30 05:21:00 PM PDT 24
Finished Jun 30 05:43:05 PM PDT 24
Peak memory 288888 kb
Host smart-b6c0dde3-6608-434b-91d2-b469b0763bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125804752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.4125804752
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2751829774
Short name T456
Test name
Test status
Simulation time 4403132360 ps
CPU time 259.79 seconds
Started Jun 30 05:21:00 PM PDT 24
Finished Jun 30 05:25:21 PM PDT 24
Peak memory 257584 kb
Host smart-fd90766d-e73b-4cd6-8eeb-5eff5911dbe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27518
29774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2751829774
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3978472580
Short name T416
Test name
Test status
Simulation time 22975657 ps
CPU time 3.25 seconds
Started Jun 30 05:21:03 PM PDT 24
Finished Jun 30 05:21:06 PM PDT 24
Peak memory 240312 kb
Host smart-e0b5b675-15a2-4a24-8e4a-a9c346a43e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39784
72580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3978472580
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3873355214
Short name T605
Test name
Test status
Simulation time 6991520865 ps
CPU time 847.4 seconds
Started Jun 30 05:21:15 PM PDT 24
Finished Jun 30 05:35:22 PM PDT 24
Peak memory 273776 kb
Host smart-7ce72fed-af9a-4027-a870-b2e842e027d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873355214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3873355214
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.525979545
Short name T290
Test name
Test status
Simulation time 62617388451 ps
CPU time 670.01 seconds
Started Jun 30 05:21:03 PM PDT 24
Finished Jun 30 05:32:13 PM PDT 24
Peak memory 248304 kb
Host smart-4f10ba3a-4e2d-4c92-a634-806bdc5f8ce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525979545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.525979545
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2272091910
Short name T682
Test name
Test status
Simulation time 2136538299 ps
CPU time 36.7 seconds
Started Jun 30 05:21:01 PM PDT 24
Finished Jun 30 05:21:39 PM PDT 24
Peak memory 249280 kb
Host smart-588f0cf9-dff2-4ed7-84d8-6f48165776c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
91910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2272091910
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2845604382
Short name T36
Test name
Test status
Simulation time 2228417693 ps
CPU time 14.64 seconds
Started Jun 30 05:21:02 PM PDT 24
Finished Jun 30 05:21:17 PM PDT 24
Peak memory 248700 kb
Host smart-f06d4c27-6fc1-4e05-be08-8d47f1b3cf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456
04382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2845604382
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2699825890
Short name T400
Test name
Test status
Simulation time 86936386 ps
CPU time 8.2 seconds
Started Jun 30 05:21:01 PM PDT 24
Finished Jun 30 05:21:10 PM PDT 24
Peak memory 248788 kb
Host smart-dab1f381-07d8-4600-9370-65b94c1f9144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26998
25890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2699825890
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2100439072
Short name T263
Test name
Test status
Simulation time 991972332 ps
CPU time 24.05 seconds
Started Jun 30 05:21:02 PM PDT 24
Finished Jun 30 05:21:26 PM PDT 24
Peak memory 257416 kb
Host smart-0f367b12-0e66-4eb6-b863-ce5abdebf2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21004
39072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2100439072
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1861792750
Short name T405
Test name
Test status
Simulation time 1096693243 ps
CPU time 71.04 seconds
Started Jun 30 05:21:12 PM PDT 24
Finished Jun 30 05:22:24 PM PDT 24
Peak memory 257368 kb
Host smart-cb848f3a-ef4e-4f71-a315-fd77a642dffb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861792750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1861792750
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1205542035
Short name T171
Test name
Test status
Simulation time 91493382726 ps
CPU time 1503.7 seconds
Started Jun 30 05:21:13 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 290340 kb
Host smart-d2988e83-263a-421b-b479-15a17efaf309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205542035 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1205542035
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1592013794
Short name T563
Test name
Test status
Simulation time 151342673954 ps
CPU time 2325.25 seconds
Started Jun 30 05:21:10 PM PDT 24
Finished Jun 30 05:59:56 PM PDT 24
Peak memory 282068 kb
Host smart-1d568a84-60ac-411d-b114-f7f3a3e25f98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592013794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1592013794
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.4116488219
Short name T653
Test name
Test status
Simulation time 3574406648 ps
CPU time 106.05 seconds
Started Jun 30 05:21:15 PM PDT 24
Finished Jun 30 05:23:01 PM PDT 24
Peak memory 257572 kb
Host smart-99119514-aed5-4cea-8149-8f73f171dfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
88219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4116488219
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1280520241
Short name T444
Test name
Test status
Simulation time 335866844 ps
CPU time 30.9 seconds
Started Jun 30 05:21:12 PM PDT 24
Finished Jun 30 05:21:43 PM PDT 24
Peak memory 249208 kb
Host smart-a21140c0-e2f4-4496-9edc-b47b92faa8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
20241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1280520241
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.192478109
Short name T327
Test name
Test status
Simulation time 23239154592 ps
CPU time 1390.54 seconds
Started Jun 30 05:21:12 PM PDT 24
Finished Jun 30 05:44:24 PM PDT 24
Peak memory 273320 kb
Host smart-8060c180-f634-48b6-a936-d01937d23e01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192478109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.192478109
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3275106598
Short name T484
Test name
Test status
Simulation time 20441123763 ps
CPU time 1346.65 seconds
Started Jun 30 05:21:13 PM PDT 24
Finished Jun 30 05:43:40 PM PDT 24
Peak memory 273412 kb
Host smart-c7fc2c23-06b5-4913-8d08-7f401eedb4ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275106598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3275106598
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3624093789
Short name T530
Test name
Test status
Simulation time 8571855512 ps
CPU time 377.41 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 05:27:29 PM PDT 24
Peak memory 249368 kb
Host smart-1a963e36-f584-4a28-9aa2-9ce33f13afb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624093789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3624093789
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.267539217
Short name T376
Test name
Test status
Simulation time 2429054052 ps
CPU time 36.44 seconds
Started Jun 30 05:21:13 PM PDT 24
Finished Jun 30 05:21:50 PM PDT 24
Peak memory 256940 kb
Host smart-f48d5609-6697-4369-b1f5-bf0bde8eea0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26753
9217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.267539217
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2680676510
Short name T25
Test name
Test status
Simulation time 458863805 ps
CPU time 33.87 seconds
Started Jun 30 05:21:12 PM PDT 24
Finished Jun 30 05:21:47 PM PDT 24
Peak memory 256564 kb
Host smart-75bf0005-8724-4d3f-aeac-c655588634db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806
76510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2680676510
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3106128167
Short name T73
Test name
Test status
Simulation time 34347948 ps
CPU time 4.89 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 05:21:16 PM PDT 24
Peak memory 248400 kb
Host smart-2d0572a3-0d67-4931-9d4e-f0b3875d516c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31061
28167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3106128167
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.4077628983
Short name T502
Test name
Test status
Simulation time 1548016548 ps
CPU time 34.09 seconds
Started Jun 30 05:21:10 PM PDT 24
Finished Jun 30 05:21:45 PM PDT 24
Peak memory 257464 kb
Host smart-92e0c00e-d384-43cb-8f66-d0ae350cc4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
28983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.4077628983
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.930738889
Short name T578
Test name
Test status
Simulation time 12663609845 ps
CPU time 1153.96 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 05:40:25 PM PDT 24
Peak memory 289684 kb
Host smart-0bf95f09-21a3-4fcc-9cb7-fb6a7f615903
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930738889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.930738889
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2589038216
Short name T666
Test name
Test status
Simulation time 480114843132 ps
CPU time 3855.37 seconds
Started Jun 30 05:21:13 PM PDT 24
Finished Jun 30 06:25:29 PM PDT 24
Peak memory 298660 kb
Host smart-c8c42ee8-a430-4be1-a699-b3f0bb12d43a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589038216 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2589038216
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1803536148
Short name T60
Test name
Test status
Simulation time 130031944540 ps
CPU time 1665.67 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 05:48:58 PM PDT 24
Peak memory 273868 kb
Host smart-21d5af9f-ea83-4a3f-add9-c87c5b8f21bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803536148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1803536148
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2274510479
Short name T47
Test name
Test status
Simulation time 1163432745 ps
CPU time 112.53 seconds
Started Jun 30 05:21:12 PM PDT 24
Finished Jun 30 05:23:05 PM PDT 24
Peak memory 257476 kb
Host smart-d31723c4-2fde-4d12-82fd-62a8b5be5ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
10479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2274510479
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1631951435
Short name T588
Test name
Test status
Simulation time 182454101 ps
CPU time 18.19 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 05:21:30 PM PDT 24
Peak memory 249128 kb
Host smart-8b6b9ebb-d489-4659-a23d-92768f1b92b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319
51435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1631951435
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.204415910
Short name T427
Test name
Test status
Simulation time 365111964166 ps
CPU time 1387.69 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 05:44:19 PM PDT 24
Peak memory 273628 kb
Host smart-011c30d9-5bd0-434e-b8bf-698f3d4cbdb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204415910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.204415910
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1440852599
Short name T289
Test name
Test status
Simulation time 9651254964 ps
CPU time 195.98 seconds
Started Jun 30 05:21:10 PM PDT 24
Finished Jun 30 05:24:27 PM PDT 24
Peak memory 249376 kb
Host smart-21dcd89e-f5cd-48ae-bb6b-5d81c2465eb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440852599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1440852599
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.42009475
Short name T523
Test name
Test status
Simulation time 2126572576 ps
CPU time 25.05 seconds
Started Jun 30 05:21:12 PM PDT 24
Finished Jun 30 05:21:38 PM PDT 24
Peak memory 249288 kb
Host smart-30522900-658e-4715-a1cd-5187b0c6c2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42009
475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.42009475
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1963592710
Short name T91
Test name
Test status
Simulation time 393794913 ps
CPU time 24.85 seconds
Started Jun 30 05:21:12 PM PDT 24
Finished Jun 30 05:21:38 PM PDT 24
Peak memory 256708 kb
Host smart-a0216e6c-7f46-4aa9-9c08-c9a257e25e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19635
92710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1963592710
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.808684858
Short name T180
Test name
Test status
Simulation time 1751987060 ps
CPU time 26.71 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 05:21:38 PM PDT 24
Peak memory 256788 kb
Host smart-0f6544f5-d818-4f81-ad16-cc2fc9a8ac13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80868
4858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.808684858
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1989910425
Short name T347
Test name
Test status
Simulation time 180525702 ps
CPU time 10.73 seconds
Started Jun 30 05:21:13 PM PDT 24
Finished Jun 30 05:21:25 PM PDT 24
Peak memory 249276 kb
Host smart-4f048307-1fa7-4d92-aab6-84ccaa117b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899
10425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1989910425
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.336920298
Short name T273
Test name
Test status
Simulation time 16735516159 ps
CPU time 1864.34 seconds
Started Jun 30 05:21:13 PM PDT 24
Finished Jun 30 05:52:18 PM PDT 24
Peak memory 290344 kb
Host smart-e394b768-39cb-4cbc-9a5c-2bd67b0e91d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336920298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.336920298
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1558485654
Short name T193
Test name
Test status
Simulation time 79112188034 ps
CPU time 4708.16 seconds
Started Jun 30 05:21:11 PM PDT 24
Finished Jun 30 06:39:40 PM PDT 24
Peak memory 306040 kb
Host smart-558ac752-6830-4c9e-9693-afd586efd9ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558485654 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1558485654
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3046993516
Short name T652
Test name
Test status
Simulation time 17786599465 ps
CPU time 859.48 seconds
Started Jun 30 05:21:18 PM PDT 24
Finished Jun 30 05:35:38 PM PDT 24
Peak memory 273916 kb
Host smart-f4ab66f8-03b3-4ea7-991d-14e5903a586f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046993516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3046993516
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3022431234
Short name T66
Test name
Test status
Simulation time 3179017456 ps
CPU time 85.6 seconds
Started Jun 30 05:21:19 PM PDT 24
Finished Jun 30 05:22:45 PM PDT 24
Peak memory 256832 kb
Host smart-cbde2905-1779-4241-bd42-b03fe3de76f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30224
31234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3022431234
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1738393387
Short name T575
Test name
Test status
Simulation time 3066306979 ps
CPU time 57.38 seconds
Started Jun 30 05:21:17 PM PDT 24
Finished Jun 30 05:22:15 PM PDT 24
Peak memory 249376 kb
Host smart-7faf66f3-910b-4fe6-8ad2-e39f06c30e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17383
93387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1738393387
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3847718429
Short name T602
Test name
Test status
Simulation time 32721593484 ps
CPU time 1842.99 seconds
Started Jun 30 05:21:20 PM PDT 24
Finished Jun 30 05:52:03 PM PDT 24
Peak memory 289464 kb
Host smart-74746102-e13f-4a3d-a806-8caf707542ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847718429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3847718429
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3790387090
Short name T495
Test name
Test status
Simulation time 1546571223 ps
CPU time 21.24 seconds
Started Jun 30 05:21:22 PM PDT 24
Finished Jun 30 05:21:43 PM PDT 24
Peak memory 249276 kb
Host smart-d45f0f2c-b57b-4f4e-953e-08e341ba66b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37903
87090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3790387090
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1143750463
Short name T467
Test name
Test status
Simulation time 623927736 ps
CPU time 7.75 seconds
Started Jun 30 05:21:18 PM PDT 24
Finished Jun 30 05:21:26 PM PDT 24
Peak memory 253164 kb
Host smart-592a47ce-d270-4454-b8e9-c4c9adbe3b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
50463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1143750463
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3392436814
Short name T443
Test name
Test status
Simulation time 288325221 ps
CPU time 11.14 seconds
Started Jun 30 05:21:20 PM PDT 24
Finished Jun 30 05:21:31 PM PDT 24
Peak memory 248452 kb
Host smart-7eb1d1bb-4e7b-462d-9fb2-437b5924b5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33924
36814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3392436814
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1420527185
Short name T176
Test name
Test status
Simulation time 4925132308 ps
CPU time 74.14 seconds
Started Jun 30 05:21:24 PM PDT 24
Finished Jun 30 05:22:38 PM PDT 24
Peak memory 249380 kb
Host smart-f6705bff-0932-49a4-ae0d-d231616e0185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14205
27185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1420527185
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3643550149
Short name T670
Test name
Test status
Simulation time 902546426 ps
CPU time 25.41 seconds
Started Jun 30 05:21:18 PM PDT 24
Finished Jun 30 05:21:44 PM PDT 24
Peak memory 257444 kb
Host smart-33771046-9ea1-41c1-a1a3-9c28e87c97f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643550149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3643550149
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2339597337
Short name T227
Test name
Test status
Simulation time 407443971078 ps
CPU time 7685.43 seconds
Started Jun 30 05:21:18 PM PDT 24
Finished Jun 30 07:29:25 PM PDT 24
Peak memory 323120 kb
Host smart-6e7bce26-70b8-491b-aaa8-39cbd91d8d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339597337 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2339597337
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.242535000
Short name T432
Test name
Test status
Simulation time 20072694095 ps
CPU time 1157.91 seconds
Started Jun 30 05:21:22 PM PDT 24
Finished Jun 30 05:40:40 PM PDT 24
Peak memory 290164 kb
Host smart-0c63a0f4-d0bc-4d9d-b435-8b5c90754261
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242535000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.242535000
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3636416742
Short name T363
Test name
Test status
Simulation time 2516009838 ps
CPU time 115.77 seconds
Started Jun 30 05:21:19 PM PDT 24
Finished Jun 30 05:23:15 PM PDT 24
Peak memory 257580 kb
Host smart-069d4c57-fc97-4e35-9ff7-834d6ba20f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36364
16742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3636416742
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3425059137
Short name T212
Test name
Test status
Simulation time 198801460 ps
CPU time 17.78 seconds
Started Jun 30 05:21:24 PM PDT 24
Finished Jun 30 05:21:42 PM PDT 24
Peak memory 257456 kb
Host smart-afb7c544-8516-48ea-a8aa-a1d6bdef5b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250
59137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3425059137
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3328441044
Short name T218
Test name
Test status
Simulation time 227841816007 ps
CPU time 1375.8 seconds
Started Jun 30 05:21:28 PM PDT 24
Finished Jun 30 05:44:24 PM PDT 24
Peak memory 273228 kb
Host smart-ed97739a-4aab-4c2c-8b9d-bce6bab24f65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328441044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3328441044
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.319111585
Short name T522
Test name
Test status
Simulation time 7554337360 ps
CPU time 809.67 seconds
Started Jun 30 05:21:24 PM PDT 24
Finished Jun 30 05:34:55 PM PDT 24
Peak memory 272756 kb
Host smart-d4303094-4de6-4b8a-90b1-3b6f2f759065
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319111585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.319111585
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3254048737
Short name T645
Test name
Test status
Simulation time 8220375670 ps
CPU time 316.73 seconds
Started Jun 30 05:21:19 PM PDT 24
Finished Jun 30 05:26:36 PM PDT 24
Peak memory 256276 kb
Host smart-3900c678-851d-4c5b-91eb-f9a5e8105338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254048737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3254048737
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3939576532
Short name T452
Test name
Test status
Simulation time 1408696473 ps
CPU time 41.93 seconds
Started Jun 30 05:21:18 PM PDT 24
Finished Jun 30 05:22:01 PM PDT 24
Peak memory 249288 kb
Host smart-9862e49c-d62e-4f28-bae9-d7ee81a3adc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39395
76532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3939576532
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1168946299
Short name T262
Test name
Test status
Simulation time 77687088 ps
CPU time 6.12 seconds
Started Jun 30 05:21:22 PM PDT 24
Finished Jun 30 05:21:29 PM PDT 24
Peak memory 253584 kb
Host smart-04ee5164-4ffb-4d99-8390-5e9a45f9238d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11689
46299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1168946299
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2057031509
Short name T257
Test name
Test status
Simulation time 291276061 ps
CPU time 16.86 seconds
Started Jun 30 05:21:17 PM PDT 24
Finished Jun 30 05:21:34 PM PDT 24
Peak memory 256640 kb
Host smart-0c74ca7c-6f11-400e-afd0-6b4869dc8333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20570
31509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2057031509
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.258494341
Short name T559
Test name
Test status
Simulation time 3438081738 ps
CPU time 62.28 seconds
Started Jun 30 05:21:23 PM PDT 24
Finished Jun 30 05:22:26 PM PDT 24
Peak memory 249312 kb
Host smart-985ebc35-9249-4720-bea9-205303a78147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25849
4341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.258494341
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2203918972
Short name T92
Test name
Test status
Simulation time 55750756146 ps
CPU time 3316.33 seconds
Started Jun 30 05:21:26 PM PDT 24
Finished Jun 30 06:16:43 PM PDT 24
Peak memory 289544 kb
Host smart-b317183f-6ac6-4724-89da-2a15c8bf0eb9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203918972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2203918972
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2007594519
Short name T676
Test name
Test status
Simulation time 41630196623 ps
CPU time 4199.5 seconds
Started Jun 30 05:21:27 PM PDT 24
Finished Jun 30 06:31:28 PM PDT 24
Peak memory 339128 kb
Host smart-43df5f3a-fa49-494f-9424-7e07fa95f7cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007594519 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2007594519
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.665702981
Short name T501
Test name
Test status
Simulation time 972920895566 ps
CPU time 3003.05 seconds
Started Jun 30 05:21:29 PM PDT 24
Finished Jun 30 06:11:32 PM PDT 24
Peak memory 289524 kb
Host smart-6c3c003c-c362-44e4-a84a-5174e813f835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665702981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.665702981
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3128705299
Short name T360
Test name
Test status
Simulation time 4088709082 ps
CPU time 31.1 seconds
Started Jun 30 05:21:25 PM PDT 24
Finished Jun 30 05:21:57 PM PDT 24
Peak memory 248836 kb
Host smart-ef43ac3d-de2b-4058-aeb7-ab77cd6edf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31287
05299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3128705299
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.436987330
Short name T76
Test name
Test status
Simulation time 279502247 ps
CPU time 6.07 seconds
Started Jun 30 05:21:27 PM PDT 24
Finished Jun 30 05:21:33 PM PDT 24
Peak memory 240624 kb
Host smart-ea9468d9-377d-44e3-b6ba-27c0a75ed0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43698
7330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.436987330
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2658097153
Short name T323
Test name
Test status
Simulation time 161465886651 ps
CPU time 2401.79 seconds
Started Jun 30 05:21:26 PM PDT 24
Finished Jun 30 06:01:28 PM PDT 24
Peak memory 289756 kb
Host smart-c8f31112-d8c8-4e15-ae2f-9628a80f05ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658097153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2658097153
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4285908728
Short name T34
Test name
Test status
Simulation time 13157320403 ps
CPU time 1443.08 seconds
Started Jun 30 05:21:33 PM PDT 24
Finished Jun 30 05:45:37 PM PDT 24
Peak memory 290192 kb
Host smart-fb742b09-926b-48e4-bbb9-b5ae85a27ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285908728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4285908728
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1778536800
Short name T512
Test name
Test status
Simulation time 7294288829 ps
CPU time 287.99 seconds
Started Jun 30 05:21:26 PM PDT 24
Finished Jun 30 05:26:15 PM PDT 24
Peak memory 249156 kb
Host smart-be7b8ae3-46ab-4eb0-be71-e428f7bf94d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778536800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1778536800
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.372794852
Short name T557
Test name
Test status
Simulation time 867814835 ps
CPU time 57.18 seconds
Started Jun 30 05:21:29 PM PDT 24
Finished Jun 30 05:22:26 PM PDT 24
Peak memory 249292 kb
Host smart-98d0f573-2137-46e4-8896-e8660413ea3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37279
4852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.372794852
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3808719373
Short name T49
Test name
Test status
Simulation time 827860403 ps
CPU time 15.7 seconds
Started Jun 30 05:21:25 PM PDT 24
Finished Jun 30 05:21:41 PM PDT 24
Peak memory 248948 kb
Host smart-9d4a23b3-8b9e-48fa-87c5-43c7a87be816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38087
19373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3808719373
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1858070427
Short name T656
Test name
Test status
Simulation time 619481528 ps
CPU time 40.34 seconds
Started Jun 30 05:21:25 PM PDT 24
Finished Jun 30 05:22:05 PM PDT 24
Peak memory 248932 kb
Host smart-4718ec59-9e4c-4d84-bb11-755be18ee79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18580
70427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1858070427
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.866433989
Short name T386
Test name
Test status
Simulation time 736362154 ps
CPU time 47.21 seconds
Started Jun 30 05:21:26 PM PDT 24
Finished Jun 30 05:22:14 PM PDT 24
Peak memory 249280 kb
Host smart-67469503-5520-46e8-b7ee-3549fbba9ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86643
3989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.866433989
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2081092256
Short name T245
Test name
Test status
Simulation time 154044269878 ps
CPU time 3989.34 seconds
Started Jun 30 05:21:33 PM PDT 24
Finished Jun 30 06:28:03 PM PDT 24
Peak memory 300072 kb
Host smart-7d0dea13-890b-4a0d-80f9-8fe066f9fcae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081092256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2081092256
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.339462086
Short name T587
Test name
Test status
Simulation time 48456717140 ps
CPU time 1565.45 seconds
Started Jun 30 05:21:39 PM PDT 24
Finished Jun 30 05:47:46 PM PDT 24
Peak memory 273836 kb
Host smart-55251e28-1fa9-4924-bf15-0141574ef768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339462086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.339462086
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1977381754
Short name T691
Test name
Test status
Simulation time 1636045839 ps
CPU time 89.26 seconds
Started Jun 30 05:21:32 PM PDT 24
Finished Jun 30 05:23:02 PM PDT 24
Peak memory 256544 kb
Host smart-deafb8ad-ff66-439d-be04-e387edda2232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19773
81754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1977381754
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1006550422
Short name T247
Test name
Test status
Simulation time 2056688758 ps
CPU time 42.46 seconds
Started Jun 30 05:21:38 PM PDT 24
Finished Jun 30 05:22:21 PM PDT 24
Peak memory 257424 kb
Host smart-fa8c32e4-99a8-48a4-9ff7-497dfd2771a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10065
50422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1006550422
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2490279940
Short name T68
Test name
Test status
Simulation time 52311384419 ps
CPU time 1355.73 seconds
Started Jun 30 05:21:33 PM PDT 24
Finished Jun 30 05:44:09 PM PDT 24
Peak memory 286632 kb
Host smart-3840349d-6c28-4b83-86e4-265ee4fd7c4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490279940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2490279940
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.461837708
Short name T667
Test name
Test status
Simulation time 194830799725 ps
CPU time 1483.46 seconds
Started Jun 30 05:21:33 PM PDT 24
Finished Jun 30 05:46:17 PM PDT 24
Peak memory 289440 kb
Host smart-37dafd41-c6da-40bb-97f0-d40097bbcfd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461837708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.461837708
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1854062416
Short name T448
Test name
Test status
Simulation time 83855315 ps
CPU time 10.81 seconds
Started Jun 30 05:21:34 PM PDT 24
Finished Jun 30 05:21:45 PM PDT 24
Peak memory 249180 kb
Host smart-09d40660-a02b-454b-a917-77bbf2dd9547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18540
62416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1854062416
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3887307943
Short name T449
Test name
Test status
Simulation time 708057739 ps
CPU time 11.28 seconds
Started Jun 30 05:21:33 PM PDT 24
Finished Jun 30 05:21:45 PM PDT 24
Peak memory 249280 kb
Host smart-a6d462b6-45eb-4af1-8354-c46055fab757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873
07943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3887307943
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3184865356
Short name T382
Test name
Test status
Simulation time 224155474 ps
CPU time 16.13 seconds
Started Jun 30 05:21:33 PM PDT 24
Finished Jun 30 05:21:50 PM PDT 24
Peak memory 248580 kb
Host smart-42729528-f03e-44eb-88b5-e851d7a50559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31848
65356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3184865356
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2377250440
Short name T362
Test name
Test status
Simulation time 226501353 ps
CPU time 7.4 seconds
Started Jun 30 05:21:32 PM PDT 24
Finished Jun 30 05:21:40 PM PDT 24
Peak memory 252288 kb
Host smart-e63412f0-443e-45c3-b733-29ca8b8a30b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23772
50440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2377250440
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1201991820
Short name T589
Test name
Test status
Simulation time 56112228531 ps
CPU time 1314.01 seconds
Started Jun 30 05:21:34 PM PDT 24
Finished Jun 30 05:43:28 PM PDT 24
Peak memory 284752 kb
Host smart-a788cf8f-1899-4471-a805-ff7f4dfcf989
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201991820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1201991820
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1500196790
Short name T402
Test name
Test status
Simulation time 7265585134 ps
CPU time 626.65 seconds
Started Jun 30 05:21:33 PM PDT 24
Finished Jun 30 05:32:00 PM PDT 24
Peak memory 267488 kb
Host smart-f144e3c9-047f-40cf-8ece-222e7a918d20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500196790 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1500196790
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1670752920
Short name T211
Test name
Test status
Simulation time 46281372 ps
CPU time 3.81 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:19:08 PM PDT 24
Peak memory 249540 kb
Host smart-cbf5f086-c4c3-41d5-8aba-606ce86f4d16
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1670752920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1670752920
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.174408655
Short name T650
Test name
Test status
Simulation time 64584636975 ps
CPU time 1368.55 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:42:02 PM PDT 24
Peak memory 289996 kb
Host smart-0177debb-a60b-48d8-b34b-2995ad7bcfee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174408655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.174408655
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1209002882
Short name T465
Test name
Test status
Simulation time 1103255955 ps
CPU time 14.34 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:19:22 PM PDT 24
Peak memory 249188 kb
Host smart-b91df6f4-f9c5-4e2f-9920-e8cc514c4ee3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1209002882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1209002882
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2860067988
Short name T377
Test name
Test status
Simulation time 5819768406 ps
CPU time 99.48 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:20:50 PM PDT 24
Peak memory 257124 kb
Host smart-33edbf6f-4c17-4683-9f57-4c77b7bf0ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28600
67988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2860067988
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.282878485
Short name T381
Test name
Test status
Simulation time 4363426370 ps
CPU time 29.58 seconds
Started Jun 30 05:19:09 PM PDT 24
Finished Jun 30 05:19:41 PM PDT 24
Peak memory 256564 kb
Host smart-14623c91-50f9-464d-b525-bd383b8af27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28287
8485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.282878485
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1648486315
Short name T683
Test name
Test status
Simulation time 23031205930 ps
CPU time 1435.31 seconds
Started Jun 30 05:19:05 PM PDT 24
Finished Jun 30 05:43:05 PM PDT 24
Peak memory 273728 kb
Host smart-3b89f9ad-b812-44bb-a3e2-1f81c7f6d000
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648486315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1648486315
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3522462202
Short name T106
Test name
Test status
Simulation time 26131415385 ps
CPU time 1652.93 seconds
Started Jun 30 05:19:08 PM PDT 24
Finished Jun 30 05:46:44 PM PDT 24
Peak memory 272872 kb
Host smart-0e7d0fcf-2e97-4842-88df-9e194006ae94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522462202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3522462202
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1408887866
Short name T293
Test name
Test status
Simulation time 243658786105 ps
CPU time 588.47 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:28:53 PM PDT 24
Peak memory 249320 kb
Host smart-f903eb77-325e-4006-9a36-dfcaf9d2bb4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408887866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1408887866
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1599671394
Short name T389
Test name
Test status
Simulation time 847395909 ps
CPU time 43.07 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:19:45 PM PDT 24
Peak memory 256844 kb
Host smart-1eae7245-e185-4f10-ab7b-d0347062e217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15996
71394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1599671394
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3499535042
Short name T478
Test name
Test status
Simulation time 2904895838 ps
CPU time 41.07 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:19:43 PM PDT 24
Peak memory 249332 kb
Host smart-eb5c78df-7129-4c9a-9ba7-13e2d68debc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34995
35042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3499535042
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3530997115
Short name T520
Test name
Test status
Simulation time 333382217 ps
CPU time 21.5 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:19:26 PM PDT 24
Peak memory 256952 kb
Host smart-f73ca6ae-37ae-4cb3-9b6b-a0716152a1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35309
97115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3530997115
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4169449212
Short name T599
Test name
Test status
Simulation time 1184628485 ps
CPU time 28.48 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:19:39 PM PDT 24
Peak memory 256368 kb
Host smart-2552d3da-e96f-46bc-9c6c-307925cb4376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41694
49212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4169449212
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3165099903
Short name T445
Test name
Test status
Simulation time 2390734767 ps
CPU time 205.4 seconds
Started Jun 30 05:19:07 PM PDT 24
Finished Jun 30 05:22:36 PM PDT 24
Peak memory 256980 kb
Host smart-68833032-661d-4fe1-945b-5f7c94672c14
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165099903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3165099903
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1873544256
Short name T206
Test name
Test status
Simulation time 216406710 ps
CPU time 4.05 seconds
Started Jun 30 05:19:08 PM PDT 24
Finished Jun 30 05:19:15 PM PDT 24
Peak memory 249556 kb
Host smart-7a554e28-77ff-4694-aa96-39d71fc10f8d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1873544256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1873544256
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1377202807
Short name T675
Test name
Test status
Simulation time 249183898504 ps
CPU time 1622.99 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:46:05 PM PDT 24
Peak memory 290372 kb
Host smart-d6c3f1b2-3d0c-4d7a-a9e0-abc12360b1ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377202807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1377202807
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2939149986
Short name T470
Test name
Test status
Simulation time 1734132650 ps
CPU time 21.26 seconds
Started Jun 30 05:19:08 PM PDT 24
Finished Jun 30 05:19:33 PM PDT 24
Peak memory 249236 kb
Host smart-0658dadd-12d2-4bc1-8cd9-288be236f7f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2939149986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2939149986
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4178752170
Short name T267
Test name
Test status
Simulation time 1172942069 ps
CPU time 76.67 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:20:22 PM PDT 24
Peak memory 256984 kb
Host smart-d6763a44-b3fb-48c8-a53a-d21ae8929b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41787
52170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4178752170
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1698291767
Short name T71
Test name
Test status
Simulation time 1590329940 ps
CPU time 24.69 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:30 PM PDT 24
Peak memory 249272 kb
Host smart-7edebae1-c6ab-4986-a601-a20cf6bce622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16982
91767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1698291767
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3645845466
Short name T569
Test name
Test status
Simulation time 123438139815 ps
CPU time 2181.23 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:55:31 PM PDT 24
Peak memory 282112 kb
Host smart-27f4e3e0-e679-47fd-aabd-130a75a2e7e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645845466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3645845466
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1845874460
Short name T300
Test name
Test status
Simulation time 3155417447 ps
CPU time 127.67 seconds
Started Jun 30 05:19:09 PM PDT 24
Finished Jun 30 05:21:19 PM PDT 24
Peak memory 249384 kb
Host smart-f01b8092-412b-4d49-85e3-f6195a01ad41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845874460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1845874460
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.899367154
Short name T672
Test name
Test status
Simulation time 444133401 ps
CPU time 24.75 seconds
Started Jun 30 05:18:59 PM PDT 24
Finished Jun 30 05:19:25 PM PDT 24
Peak memory 257232 kb
Host smart-0b6b85bf-3c96-41f8-9a63-1b1e8cf2603e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89936
7154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.899367154
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2592115574
Short name T507
Test name
Test status
Simulation time 7440792941 ps
CPU time 48.54 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:55 PM PDT 24
Peak memory 249056 kb
Host smart-d622aa71-90bc-4bd1-8779-9a98be374cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25921
15574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2592115574
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2689372553
Short name T472
Test name
Test status
Simulation time 1426063362 ps
CPU time 20.84 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:19:33 PM PDT 24
Peak memory 249212 kb
Host smart-9b7efacb-1e27-4ab2-83ee-af02fe6b6a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26893
72553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2689372553
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2814562438
Short name T454
Test name
Test status
Simulation time 1617443483 ps
CPU time 45.53 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:19:50 PM PDT 24
Peak memory 257420 kb
Host smart-501ccac5-472d-4e49-949a-7b6d3f3433fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28145
62438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2814562438
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4174435101
Short name T269
Test name
Test status
Simulation time 8144257600 ps
CPU time 404.65 seconds
Started Jun 30 05:19:06 PM PDT 24
Finished Jun 30 05:25:55 PM PDT 24
Peak memory 257584 kb
Host smart-40953b1c-9861-4f8b-8fa7-1972bc3057d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174435101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4174435101
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2064221711
Short name T93
Test name
Test status
Simulation time 192437241336 ps
CPU time 3670.69 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 06:20:14 PM PDT 24
Peak memory 305776 kb
Host smart-ebf6800e-113f-4868-a8c8-3a8a16184712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064221711 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2064221711
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3680695345
Short name T46
Test name
Test status
Simulation time 24578384 ps
CPU time 2.88 seconds
Started Jun 30 05:19:16 PM PDT 24
Finished Jun 30 05:19:19 PM PDT 24
Peak memory 249504 kb
Host smart-30c62adb-0f9f-413a-a73f-39aa7aea5b0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3680695345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3680695345
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.445742813
Short name T514
Test name
Test status
Simulation time 8188003139 ps
CPU time 1068.26 seconds
Started Jun 30 05:19:04 PM PDT 24
Finished Jun 30 05:36:57 PM PDT 24
Peak memory 285676 kb
Host smart-12b7426b-ad06-4539-a054-2a51697589b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445742813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.445742813
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.882425875
Short name T677
Test name
Test status
Simulation time 1195337816 ps
CPU time 15.52 seconds
Started Jun 30 05:19:02 PM PDT 24
Finished Jun 30 05:19:21 PM PDT 24
Peak memory 249472 kb
Host smart-24f939e7-d0e4-4776-b4a9-af98b5bbb3b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=882425875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.882425875
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2802718831
Short name T551
Test name
Test status
Simulation time 767889881 ps
CPU time 57.3 seconds
Started Jun 30 05:19:01 PM PDT 24
Finished Jun 30 05:20:01 PM PDT 24
Peak memory 250304 kb
Host smart-da8779d3-ddee-4eac-830b-5d686c32286b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28027
18831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2802718831
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.219494187
Short name T695
Test name
Test status
Simulation time 595597109 ps
CPU time 38.89 seconds
Started Jun 30 05:19:08 PM PDT 24
Finished Jun 30 05:19:50 PM PDT 24
Peak memory 257424 kb
Host smart-919bf373-672a-469d-9563-b8a21365a48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21949
4187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.219494187
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2310454546
Short name T279
Test name
Test status
Simulation time 81696291216 ps
CPU time 2580.06 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 06:02:08 PM PDT 24
Peak memory 284768 kb
Host smart-a322386c-88e6-4e94-bd3e-2867ce14aae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310454546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2310454546
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3037904291
Short name T107
Test name
Test status
Simulation time 222883873603 ps
CPU time 1445.94 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:43:08 PM PDT 24
Peak memory 273380 kb
Host smart-ccae4c02-b154-40ce-b880-57f4239d80cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037904291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3037904291
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2325439400
Short name T318
Test name
Test status
Simulation time 3625327390 ps
CPU time 153.21 seconds
Started Jun 30 05:19:00 PM PDT 24
Finished Jun 30 05:21:35 PM PDT 24
Peak memory 249204 kb
Host smart-c587c796-1607-443e-b720-8fe8bee73fad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325439400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2325439400
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.325504187
Short name T609
Test name
Test status
Simulation time 2497406249 ps
CPU time 32.27 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:19:45 PM PDT 24
Peak memory 256576 kb
Host smart-8fcb8ee8-b298-4178-958e-470a9ee14732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550
4187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.325504187
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2805446429
Short name T271
Test name
Test status
Simulation time 1999496085 ps
CPU time 35.74 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:19:49 PM PDT 24
Peak memory 249212 kb
Host smart-3397a876-9682-433c-a790-134e97395a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28054
46429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2805446429
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1839191524
Short name T64
Test name
Test status
Simulation time 143137604 ps
CPU time 16.97 seconds
Started Jun 30 05:19:05 PM PDT 24
Finished Jun 30 05:19:26 PM PDT 24
Peak memory 257428 kb
Host smart-78591a7d-a37e-4901-9194-1f40bc96edd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18391
91524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1839191524
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.823896987
Short name T351
Test name
Test status
Simulation time 243074775 ps
CPU time 14.8 seconds
Started Jun 30 05:19:03 PM PDT 24
Finished Jun 30 05:19:23 PM PDT 24
Peak memory 255408 kb
Host smart-abcc4408-612a-4b30-b0ad-216b8c4381c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82389
6987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.823896987
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.515153281
Short name T200
Test name
Test status
Simulation time 17205234 ps
CPU time 2.45 seconds
Started Jun 30 05:19:11 PM PDT 24
Finished Jun 30 05:19:15 PM PDT 24
Peak memory 249540 kb
Host smart-1889189c-5e55-4cc8-b1f9-bfff20035437
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=515153281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.515153281
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3647590912
Short name T446
Test name
Test status
Simulation time 42099178567 ps
CPU time 1409.15 seconds
Started Jun 30 05:19:13 PM PDT 24
Finished Jun 30 05:42:43 PM PDT 24
Peak memory 289724 kb
Host smart-48871e37-401a-4817-a286-58ef4e77675e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647590912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3647590912
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3477809220
Short name T356
Test name
Test status
Simulation time 506094659 ps
CPU time 13.57 seconds
Started Jun 30 05:19:21 PM PDT 24
Finished Jun 30 05:19:36 PM PDT 24
Peak memory 249208 kb
Host smart-57591687-2239-48a7-9a6d-be138b2a582f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3477809220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3477809220
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.248019464
Short name T370
Test name
Test status
Simulation time 5321579583 ps
CPU time 311.62 seconds
Started Jun 30 05:19:17 PM PDT 24
Finished Jun 30 05:24:29 PM PDT 24
Peak memory 257588 kb
Host smart-dc164db9-30b7-4c42-8b19-10b082b8b508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24801
9464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.248019464
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.637131265
Short name T393
Test name
Test status
Simulation time 79338603 ps
CPU time 6.74 seconds
Started Jun 30 05:19:11 PM PDT 24
Finished Jun 30 05:19:19 PM PDT 24
Peak memory 249640 kb
Host smart-f6a2f5b4-b02c-465d-8152-4f01b02c9b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63713
1265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.637131265
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3716868960
Short name T337
Test name
Test status
Simulation time 70619173974 ps
CPU time 984.52 seconds
Started Jun 30 05:19:18 PM PDT 24
Finished Jun 30 05:35:43 PM PDT 24
Peak memory 273300 kb
Host smart-9b85e464-385f-4cbe-9fb7-1572d90c95d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716868960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3716868960
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.10488152
Short name T428
Test name
Test status
Simulation time 33308398600 ps
CPU time 1832.75 seconds
Started Jun 30 05:19:23 PM PDT 24
Finished Jun 30 05:49:56 PM PDT 24
Peak memory 289276 kb
Host smart-455352b8-5d43-4e7f-b44d-0565c3de90a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10488152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.10488152
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1311131164
Short name T310
Test name
Test status
Simulation time 15648979988 ps
CPU time 540.11 seconds
Started Jun 30 05:19:16 PM PDT 24
Finished Jun 30 05:28:16 PM PDT 24
Peak memory 249168 kb
Host smart-5dbfafd8-a350-4287-894b-f332cbf7786b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311131164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1311131164
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2521837627
Short name T539
Test name
Test status
Simulation time 167428231 ps
CPU time 12.77 seconds
Started Jun 30 05:19:13 PM PDT 24
Finished Jun 30 05:19:26 PM PDT 24
Peak memory 249276 kb
Host smart-c0699f10-8162-4f58-bb86-574531e76d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25218
37627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2521837627
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.49442850
Short name T109
Test name
Test status
Simulation time 4200362930 ps
CPU time 60.42 seconds
Started Jun 30 05:19:13 PM PDT 24
Finished Jun 30 05:20:14 PM PDT 24
Peak memory 257508 kb
Host smart-2fc45ed2-836f-4711-bd31-27df989811e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49442
850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.49442850
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3338129346
Short name T519
Test name
Test status
Simulation time 140812908 ps
CPU time 14.76 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:19:28 PM PDT 24
Peak memory 249564 kb
Host smart-87d5e1dc-903a-4862-a8b8-ba71845b7da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33381
29346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3338129346
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2891009941
Short name T426
Test name
Test status
Simulation time 2847494970 ps
CPU time 41.23 seconds
Started Jun 30 05:19:17 PM PDT 24
Finished Jun 30 05:19:59 PM PDT 24
Peak memory 257744 kb
Host smart-76740361-2686-4f27-a8b7-31b90a891b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28910
09941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2891009941
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3634441548
Short name T414
Test name
Test status
Simulation time 11560835068 ps
CPU time 207.7 seconds
Started Jun 30 05:19:14 PM PDT 24
Finished Jun 30 05:22:42 PM PDT 24
Peak memory 257544 kb
Host smart-d3673cb3-d498-40e2-a214-5e90ee19a393
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634441548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3634441548
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2266917402
Short name T30
Test name
Test status
Simulation time 73247445889 ps
CPU time 7953.45 seconds
Started Jun 30 05:19:14 PM PDT 24
Finished Jun 30 07:31:49 PM PDT 24
Peak memory 404244 kb
Host smart-4d46d919-ffe4-4d06-bfae-89f2a14593f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266917402 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2266917402
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1306906157
Short name T203
Test name
Test status
Simulation time 18491929 ps
CPU time 2.71 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:19:15 PM PDT 24
Peak memory 249544 kb
Host smart-57e36520-c84d-4147-b5ce-95f72b27e462
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1306906157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1306906157
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3856731944
Short name T571
Test name
Test status
Simulation time 51294170208 ps
CPU time 1239.51 seconds
Started Jun 30 05:19:24 PM PDT 24
Finished Jun 30 05:40:04 PM PDT 24
Peak memory 290092 kb
Host smart-c538a182-62b8-44d6-a8e9-6b32d397f669
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856731944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3856731944
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3650800646
Short name T223
Test name
Test status
Simulation time 181238585 ps
CPU time 10.94 seconds
Started Jun 30 05:19:17 PM PDT 24
Finished Jun 30 05:19:29 PM PDT 24
Peak memory 249204 kb
Host smart-1e8d81a4-11af-4796-9132-e24c6d98b396
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3650800646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3650800646
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4091360889
Short name T570
Test name
Test status
Simulation time 8154904440 ps
CPU time 160.07 seconds
Started Jun 30 05:19:20 PM PDT 24
Finished Jun 30 05:22:00 PM PDT 24
Peak memory 256888 kb
Host smart-08ec663f-f65e-4a6b-95c5-f1530505cb91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40913
60889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4091360889
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3261449948
Short name T462
Test name
Test status
Simulation time 172268655 ps
CPU time 15.11 seconds
Started Jun 30 05:19:16 PM PDT 24
Finished Jun 30 05:19:32 PM PDT 24
Peak memory 249180 kb
Host smart-63fbe131-9c9f-4e0a-9343-9c6427d1f566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
49948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3261449948
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.4255648580
Short name T668
Test name
Test status
Simulation time 70808526240 ps
CPU time 1669.04 seconds
Started Jun 30 05:19:23 PM PDT 24
Finished Jun 30 05:47:13 PM PDT 24
Peak memory 289968 kb
Host smart-af2734a5-8d04-4be7-ad0d-ff28a9442dfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255648580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.4255648580
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1177282442
Short name T596
Test name
Test status
Simulation time 28908017037 ps
CPU time 186.03 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:22:18 PM PDT 24
Peak memory 249372 kb
Host smart-be6fd426-6a83-4689-8d25-20876915c11f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177282442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1177282442
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1222292641
Short name T352
Test name
Test status
Simulation time 2611017324 ps
CPU time 41.04 seconds
Started Jun 30 05:19:12 PM PDT 24
Finished Jun 30 05:19:54 PM PDT 24
Peak memory 256848 kb
Host smart-e2a42ffc-7a70-415b-8395-9237bca92238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12222
92641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1222292641
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1525222453
Short name T79
Test name
Test status
Simulation time 1425421699 ps
CPU time 50.2 seconds
Started Jun 30 05:19:10 PM PDT 24
Finished Jun 30 05:20:02 PM PDT 24
Peak memory 249104 kb
Host smart-2045b878-764a-4030-8399-b6daf4d40178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15252
22453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1525222453
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3507365685
Short name T28
Test name
Test status
Simulation time 369842444 ps
CPU time 43.8 seconds
Started Jun 30 05:19:09 PM PDT 24
Finished Jun 30 05:19:56 PM PDT 24
Peak memory 249464 kb
Host smart-fc0da296-8b75-42dd-b60d-2698c09ee321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35073
65685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3507365685
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.536685919
Short name T80
Test name
Test status
Simulation time 821122089 ps
CPU time 17.43 seconds
Started Jun 30 05:19:19 PM PDT 24
Finished Jun 30 05:19:37 PM PDT 24
Peak memory 256248 kb
Host smart-053f0477-f316-4fe7-804e-b4930232e64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53668
5919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.536685919
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2648210302
Short name T90
Test name
Test status
Simulation time 361563285675 ps
CPU time 9485.96 seconds
Started Jun 30 05:19:31 PM PDT 24
Finished Jun 30 07:57:38 PM PDT 24
Peak memory 389940 kb
Host smart-7b4b4f25-bdce-4bf5-983e-dc55fff3ca02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648210302 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2648210302
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%