Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65786684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31971653

1

T1

2291

T2

1104

T3

929

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14501625	1			T1	1464		T2	557		T3	384
values[0x0]	40438649	1			T1	2460		T2	1316		T3	1363
values[0x1]	42818063	1			T1	2426		T2	1316		T3	1215

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56003242	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41755095

1

T1

2862

T2

1365

T3

1176

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	684683	1			T2	18		T3	9		T4	2718
valid_sources[0x01]	294327	1			T2	12		T3	5		T4	2792
valid_sources[0x02]	288053	1			T2	16		T3	12		T4	2781
valid_sources[0x03]	309471	1			T2	14		T3	7		T4	2798
valid_sources[0x04]	299110	1			T2	11		T3	8		T4	2759
valid_sources[0x05]	300548	1			T2	8		T3	12		T4	2782
valid_sources[0x06]	302667	1			T2	18		T3	18		T4	2761
valid_sources[0x07]	299213	1			T2	17		T3	17		T4	2782
valid_sources[0x08]	332665	1			T2	16		T3	13		T4	2795
valid_sources[0x09]	301609	1			T2	12		T3	17		T4	2855
valid_sources[0x0a]	311616	1			T2	12		T3	6		T4	2743
valid_sources[0x0b]	306522	1			T2	11		T3	5		T4	2737
valid_sources[0x0c]	339449	1			T2	10		T3	8		T4	2718
valid_sources[0x0d]	320559	1			T2	4		T3	12		T4	2609
valid_sources[0x0e]	1047549	1			T2	11		T3	14		T4	2814
valid_sources[0x0f]	302042	1			T2	10		T3	11		T4	2836
valid_sources[0x10]	305668	1			T2	12		T3	11		T4	2762
valid_sources[0x11]	293651	1			T2	18		T3	3		T4	2712
valid_sources[0x12]	312210	1			T2	8		T3	14		T4	2716
valid_sources[0x13]	729392	1			T2	18		T3	23		T4	2720
valid_sources[0x14]	294613	1			T2	9		T3	9		T4	2687
valid_sources[0x15]	326605	1			T2	8		T3	11		T4	2704
valid_sources[0x16]	309309	1			T2	11		T3	5		T4	2827
valid_sources[0x17]	305830	1			T2	20		T3	8		T4	2791
valid_sources[0x18]	306694	1			T2	11		T3	11		T4	2767
valid_sources[0x19]	301986	1			T2	7		T3	10		T4	2757
valid_sources[0x1a]	305632	1			T2	8		T3	19		T4	2783
valid_sources[0x1b]	305699	1			T2	11		T3	7		T4	2658
valid_sources[0x1c]	293905	1			T2	17		T3	10		T4	2729
valid_sources[0x1d]	302453	1			T2	10		T3	10		T4	2724
valid_sources[0x1e]	298174	1			T2	8		T3	11		T4	2775
valid_sources[0x1f]	300653	1			T2	22		T3	11		T4	2901
valid_sources[0x20]	304575	1			T2	9		T3	15		T4	2763
valid_sources[0x21]	766608	1			T2	19		T3	9		T4	2686
valid_sources[0x22]	310754	1			T2	16		T3	10		T4	2786
valid_sources[0x23]	300162	1			T2	11		T3	9		T4	2816
valid_sources[0x24]	294604	1			T2	8		T3	17		T4	2742
valid_sources[0x25]	298216	1			T2	11		T3	8		T4	2741
valid_sources[0x26]	294980	1			T2	20		T3	7		T4	2766
valid_sources[0x27]	526706	1			T2	14		T3	9		T4	2707
valid_sources[0x28]	300191	1			T2	8		T3	13		T4	2830
valid_sources[0x29]	290820	1			T2	11		T3	11		T4	2858
valid_sources[0x2a]	302484	1			T2	5		T3	9		T4	2682
valid_sources[0x2b]	298763	1			T2	13		T3	14		T4	2765
valid_sources[0x2c]	290259	1			T2	15		T3	3		T4	2737
valid_sources[0x2d]	305269	1			T2	9		T3	8		T4	2776
valid_sources[0x2e]	305896	1			T2	11		T3	19		T4	2779
valid_sources[0x2f]	310493	1			T2	10		T3	3		T4	2767
valid_sources[0x30]	304212	1			T2	10		T3	11		T4	2731
valid_sources[0x31]	364805	1			T2	14		T3	11		T4	2787
valid_sources[0x32]	736785	1			T2	14		T3	11		T4	2673
valid_sources[0x33]	300487	1			T2	18		T3	1		T4	2773
valid_sources[0x34]	296629	1			T2	11		T3	13		T4	2728
valid_sources[0x35]	307602	1			T2	10		T3	15		T4	2751
valid_sources[0x36]	301580	1			T2	19		T3	18		T4	2843
valid_sources[0x37]	303668	1			T2	7		T3	12		T4	2761
valid_sources[0x38]	664061	1			T2	9		T3	11		T4	2722
valid_sources[0x39]	830060	1			T2	12		T3	14		T4	2702
valid_sources[0x3a]	805190	1			T2	19		T3	15		T4	2722
valid_sources[0x3b]	305321	1			T2	14		T3	13		T4	2820
valid_sources[0x3c]	307613	1			T2	8		T3	9		T4	2762
valid_sources[0x3d]	299124	1			T2	14		T3	12		T4	2715
valid_sources[0x3e]	532373	1			T2	9		T3	18		T4	2767
valid_sources[0x3f]	648672	1			T2	16		T3	12		T4	2787
valid_sources[0x40]	310743	1			T2	13		T3	10		T4	2712
valid_sources[0x41]	298585	1			T2	11		T3	10		T4	2763
valid_sources[0x42]	594777	1			T2	16		T3	9		T4	2703
valid_sources[0x43]	299668	1			T2	15		T3	18		T4	2684
valid_sources[0x44]	292621	1			T2	15		T3	10		T4	2816
valid_sources[0x45]	781602	1			T2	11		T3	5		T4	2788
valid_sources[0x46]	298327	1			T2	12		T3	4		T4	2820
valid_sources[0x47]	812976	1			T2	15		T3	14		T4	2750
valid_sources[0x48]	305810	1			T2	13		T3	6		T4	2734
valid_sources[0x49]	298447	1			T2	5		T3	8		T4	2809
valid_sources[0x4a]	307831	1			T2	19		T3	22		T4	2777
valid_sources[0x4b]	301632	1			T2	14		T3	14		T4	2705
valid_sources[0x4c]	311956	1			T2	20		T3	6		T4	2629
valid_sources[0x4d]	290803	1			T2	12		T3	11		T4	2698
valid_sources[0x4e]	769803	1			T2	7		T3	11		T4	2718
valid_sources[0x4f]	297364	1			T2	18		T3	9		T4	2831
valid_sources[0x50]	301068	1			T2	15		T3	17		T4	2806
valid_sources[0x51]	657135	1			T2	24		T3	15		T4	2759
valid_sources[0x52]	305017	1			T2	10		T3	11		T4	2703
valid_sources[0x53]	299754	1			T2	8		T3	12		T4	2745
valid_sources[0x54]	294116	1			T2	5		T3	7		T4	2660
valid_sources[0x55]	300354	1			T2	12		T3	17		T4	2774
valid_sources[0x56]	289186	1			T2	16		T3	14		T4	2664
valid_sources[0x57]	295200	1			T2	7		T3	12		T4	2717
valid_sources[0x58]	294043	1			T2	1		T3	8		T4	2701
valid_sources[0x59]	750601	1			T2	12		T3	19		T4	2784
valid_sources[0x5a]	303813	1			T2	13		T3	12		T4	2717
valid_sources[0x5b]	300269	1			T2	17		T3	10		T4	2728
valid_sources[0x5c]	299345	1			T2	12		T3	13		T4	2782
valid_sources[0x5d]	298907	1			T2	12		T3	16		T4	2741
valid_sources[0x5e]	296522	1			T2	14		T3	9		T4	2751
valid_sources[0x5f]	668187	1			T2	11		T3	10		T4	2692
valid_sources[0x60]	309630	1			T2	11		T3	9		T4	2778
valid_sources[0x61]	310528	1			T2	8		T3	14		T4	2736
valid_sources[0x62]	317038	1			T2	16		T3	16		T4	2729
valid_sources[0x63]	307400	1			T2	11		T3	13		T4	2782
valid_sources[0x64]	303949	1			T2	11		T3	8		T4	2773
valid_sources[0x65]	325808	1			T2	9		T3	10		T4	2784
valid_sources[0x66]	297885	1			T2	14		T3	13		T4	2789
valid_sources[0x67]	299995	1			T2	10		T3	5		T4	2702
valid_sources[0x68]	310198	1			T2	12		T3	9		T4	2708
valid_sources[0x69]	747365	1			T2	16		T3	9		T4	2731
valid_sources[0x6a]	295795	1			T2	21		T3	10		T4	2756
valid_sources[0x6b]	326885	1			T2	9		T3	19		T4	2790
valid_sources[0x6c]	302117	1			T2	23		T3	10		T4	2777
valid_sources[0x6d]	336618	1			T2	14		T3	20		T4	2671
valid_sources[0x6e]	302395	1			T2	15		T3	11		T4	2776
valid_sources[0x6f]	300233	1			T2	10		T3	12		T4	2678
valid_sources[0x70]	690007	1			T2	12		T3	12		T4	2798
valid_sources[0x71]	814024	1			T2	9		T3	7		T4	2786
valid_sources[0x72]	303555	1			T2	12		T3	11		T4	2753
valid_sources[0x73]	305426	1			T2	13		T3	7		T4	2724
valid_sources[0x74]	293083	1			T2	12		T3	8		T4	2729
valid_sources[0x75]	310567	1			T2	20		T3	13		T4	2773
valid_sources[0x76]	314843	1			T2	13		T3	16		T4	2707
valid_sources[0x77]	348696	1			T2	12		T3	17		T4	2756
valid_sources[0x78]	310662	1			T2	9		T3	18		T4	2710
valid_sources[0x79]	300216	1			T2	9		T3	12		T4	2691
valid_sources[0x7a]	675912	1			T2	10		T3	12		T4	2652
valid_sources[0x7b]	314359	1			T2	12		T3	6		T4	2804
valid_sources[0x7c]	304872	1			T2	23		T3	11		T4	2704
valid_sources[0x7d]	306061	1			T2	14		T3	17		T4	2675
valid_sources[0x7e]	306740	1			T2	14		T3	15		T4	2761
valid_sources[0x7f]	1586910	1			T2	11		T3	14		T4	2659
valid_sources[0x80]	297361	1			T2	6		T3	11		T4	2771

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7263260

1

T1

734

T2

294

T3

196

values[0x0]

all_enables

biggest_size

15562918

1

T1

1006

T2

531

T3

494

values[0x1]

all_enables

biggest_size

9145475

1

T1

551

T2

279

T3

239