Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T45,T65
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12761	0	0
DisabledNoTrigBkwd_A	2147483647	890608	0	0
DisabledNoTrigFwd_A	2147483647	1506083567	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12761	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T9	571939	0	0	0
T14	258474	0	0	0
T15	527911	0	0	0
T16	26381	0	0	0
T18	2676	364	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T43	206205	0	0	0
T45	0	858	0	0
T65	1258	576	0	0
T193	0	682	0	0
T194	0	337	0	0
T195	0	1316	0	0
T196	0	472	0	0
T197	0	463	0	0
T198	0	697	0	0
T199	0	784	0	0
T200	0	915	0	0
T201	0	411	0	0
T202	0	431	0	0
T203	0	223	0	0
T204	3941	474	0	0
T205	0	659	0	0
T206	0	1085	0	0
T207	0	1118	0	0
T208	0	316	0	0
T209	0	580	0	0
T210	37637	0	0	0
T211	274154	0	0	0
T212	541687	0	0	0
T213	927299	0	0	0
T214	30179	0	0	0
T215	158924	0	0	0
T216	418815	0	0	0
T217	147230	0	0	0
T218	147650	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	890608	0	0
T2	29494	3	0	0
T3	32100	0	0	0
T4	2277476	12763	0	0
T5	2607020	2287	0	0
T6	621780	1827	0	0
T7	1574892	493	0	0
T8	423135	11	0	0
T9	0	1	0	0
T14	1033896	6872	0	0
T15	1583733	5018	0	0
T18	10704	4	0	0
T19	383468	50	0	0
T20	109564	0	0	0
T22	0	238	0	0
T27	0	254	0	0
T43	0	566	0	0
T44	0	975	0	0
T45	0	32	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1506083567	0	0
T1	112536	29875	0	0
T2	117976	90469	0	0
T3	128400	65622	0	0
T4	2277476	1665260	0	0
T5	2607020	1298392	0	0
T6	621780	470498	0	0
T7	1574892	795426	0	0
T14	1033896	101061	0	0
T18	10704	8587	0	0
T19	383468	304425	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T207
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713683466	1592	0	0
DisabledNoTrigBkwd_A	713683466	272139	0	0
DisabledNoTrigFwd_A	713683466	313566344	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1592	0	0
T204	3941	474	0	0
T207	0	1118	0	0
T210	37637	0	0	0
T211	274154	0	0	0
T212	541687	0	0	0
T213	927299	0	0	0
T214	30179	0	0	0
T215	158924	0	0	0
T216	418815	0	0	0
T217	147230	0	0	0
T218	147650	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	272139	0	0
T2	29494	3	0	0
T3	32100	0	0	0
T4	569369	1714	0	0
T5	651755	1342	0	0
T6	155445	3	0	0
T7	393723	0	0	0
T8	0	2	0	0
T14	258474	1230	0	0
T15	0	1965	0	0
T18	2676	0	0	0
T19	95867	50	0	0
T20	27391	0	0	0
T22	0	99	0	0
T44	0	948	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	313566344	0	0
T1	28134	599	0	0
T2	29494	2155	0	0
T3	32100	16848	0	0
T4	569369	886777	0	0
T5	651755	1742	0	0
T6	155445	155092	0	0
T7	393723	6615	0	0
T14	258474	25631	0	0
T18	2676	2126	0	0
T19	95867	17118	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T193,T199
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713683466	3346	0	0
DisabledNoTrigBkwd_A	713683466	191649	0	0
DisabledNoTrigFwd_A	713683466	407550577	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	3346	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T9	571939	0	0	0
T14	258474	0	0	0
T15	527911	0	0	0
T16	26381	0	0	0
T18	2676	364	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T43	206205	0	0	0
T193	0	682	0	0
T199	0	784	0	0
T202	0	431	0	0
T206	0	1085	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	191649	0	0
T4	569369	2389	0	0
T5	651755	18	0	0
T6	155445	5	0	0
T7	393723	0	0	0
T8	141045	7	0	0
T9	0	1	0	0
T14	258474	1842	0	0
T15	527911	22	0	0
T18	2676	4	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	53	0	0
T43	0	292	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	407550577	0	0
T1	28134	603	0	0
T2	29494	29438	0	0
T3	32100	14629	0	0
T4	569369	154513	0	0
T5	651755	648499	0	0
T6	155445	154749	0	0
T7	393723	393335	0	0
T14	258474	13369	0	0
T18	2676	2142	0	0
T19	95867	95769	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T65,T195,T196
1	1	Covered	T1,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713683466	4981	0	0
DisabledNoTrigBkwd_A	713683466	223284	0	0
DisabledNoTrigFwd_A	713683466	383799990	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	4981	0	0
T25	453380	0	0	0
T33	299376	0	0	0
T65	1258	576	0	0
T66	48463	0	0	0
T69	737318	0	0	0
T70	32410	0	0	0
T72	21039	0	0	0
T195	0	1316	0	0
T196	0	472	0	0
T197	0	463	0	0
T200	0	915	0	0
T205	0	659	0	0
T209	0	580	0	0
T219	40762	0	0	0
T220	20367	0	0	0
T221	199036	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	223284	0	0
T4	569369	303	0	0
T5	651755	919	0	0
T6	155445	7	0	0
T7	393723	491	0	0
T8	141045	2	0	0
T14	258474	1835	0	0
T15	527911	2968	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	26	0	0
T27	0	2	0	0
T44	0	27	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	383799990	0	0
T1	28134	607	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	484862	0	0
T5	651755	590	0	0
T6	155445	155321	0	0
T7	393723	5930	0	0
T14	258474	10775	0	0
T18	2676	2153	0	0
T19	95867	95769	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T194,T198
1	1	Covered	T3,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713683466	2842	0	0
DisabledNoTrigBkwd_A	713683466	203536	0	0
DisabledNoTrigFwd_A	713683466	401166656	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	2842	0	0
T17	142657	0	0	0
T22	59308	0	0	0
T27	206241	0	0	0
T45	1751	858	0	0
T46	108094	0	0	0
T67	812593	0	0	0
T68	193887	0	0	0
T71	69980	0	0	0
T80	325957	0	0	0
T98	467841	0	0	0
T194	0	337	0	0
T198	0	697	0	0
T201	0	411	0	0
T203	0	223	0	0
T208	0	316	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	203536	0	0
T4	569369	8357	0	0
T5	651755	8	0	0
T6	155445	1812	0	0
T7	393723	2	0	0
T8	141045	0	0	0
T14	258474	1965	0	0
T15	527911	63	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	60	0	0
T27	0	252	0	0
T43	0	274	0	0
T45	0	32	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	401166656	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	2121	0	0
T4	569369	139108	0	0
T5	651755	647561	0	0
T6	155445	5336	0	0
T7	393723	389546	0	0
T14	258474	51286	0	0
T18	2676	2166	0	0
T19	95867	95769	0	0