Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T21,T22
1	0	Covered	T4,T19,T17

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T19,T17

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T23,T24
1	1	Covered	T1,T21,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T4,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T4,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T6

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T3,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T25,T26
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T19,T14,T27
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T28,T29,T30
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T4,T15,T17
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T4,T19,T14
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T3,T4
TimeoutSt->Phase0St	172	Covered	T1,T4,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T31,T32
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T14,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T29,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T15,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T19,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1103	0	0
CheckAccumTrig0_A	2147483647	2498	0	0
CheckAccumTrig1_A	2147483647	128	0	0
CheckClr_A	2147483647	1182	0	0
CheckEn_A	2147483647	1128159993	0	0
CheckPhase0_A	2147483647	2817	0	0
CheckPhase1_A	2147483647	2756	0	0
CheckPhase2_A	2147483647	2702	0	0
CheckPhase3_A	2147483647	2638	0	0
CheckTimeout0_A	2147483647	7263	0	0
CheckTimeoutSt1_A	2147483647	739528	0	0
CheckTimeoutSt2_A	2147483647	6882	0	0
CheckTimeoutStTrig_A	2147483647	244	0	0
ErrorStAllEscAsserted_A	2147483647	5661	0	0
ErrorStIsTerminal_A	2147483647	4701	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1103	0	0
T11	168036	255	0	0
T12	0	283	0	0
T13	0	123	0	0
T30	2567588	0	0	0
T31	2787260	0	0	0
T34	0	140	0	0
T35	0	302	0	0
T36	1111912	0	0	0
T37	78616	0	0	0
T38	72764	0	0	0
T39	960140	0	0	0
T40	1690608	0	0	0
T41	301724	0	0	0
T42	2953468	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2498	0	0
T2	29494	1	0	0
T3	32100	0	0	0
T4	2277476	25	0	0
T5	2607020	4	0	0
T6	621780	4	0	0
T7	1574892	2	0	0
T8	423135	4	0	0
T9	0	1	0	0
T14	1033896	9	0	0
T15	1583733	4	0	0
T18	10704	1	0	0
T19	383468	3	0	0
T20	109564	0	0	0
T22	0	10	0	0
T27	0	2	0	0
T43	0	8	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	128	0	0
T4	569369	3	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T10	202375	0	0	0
T14	258474	0	0	0
T15	527911	0	0	0
T17	0	1	0	0
T18	2676	0	0	0
T19	95867	2	0	0
T20	27391	0	0	0
T23	0	2	0	0
T25	0	2	0	0
T28	601019	2	0	0
T30	0	1	0	0
T42	0	2	0	0
T47	1153958	2	0	0
T48	70468	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	43541	0	0	0
T61	148764	0	0	0
T62	29652	0	0	0
T63	332724	0	0	0
T64	220634	0	0	0
T65	2516	0	0	0
T66	48463	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1182	0	0
T4	2277476	9	0	0
T5	2607020	0	0	0
T6	621780	0	0	0
T7	1574892	0	0	0
T8	564180	1	0	0
T14	1033896	5	0	0
T15	2111644	1	0	0
T17	0	11	0	0
T18	10704	0	0	0
T19	383468	4	0	0
T20	109564	0	0	0
T22	0	5	0	0
T25	0	4	0	0
T27	0	1	0	0
T28	0	16	0	0
T33	0	1	0	0
T43	0	8	0	0
T44	0	2	0	0
T47	0	10	0	0
T48	0	1	0	0
T49	0	1	0	0
T63	0	2	0	0
T67	0	2	0	0
T68	0	5	0	0
T69	0	1	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1128159993	0	0
T1	112536	29874	0	0
T2	117976	90466	0	0
T3	128400	65619	0	0
T4	2277476	1313438	0	0
T5	2607020	5848	0	0
T6	621780	26372	0	0
T7	1574892	407654	0	0
T14	1033896	81971	0	0
T18	10704	8587	0	0
T19	383468	304422	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2817	0	0
T1	28134	1	0	0
T2	58988	1	0	0
T3	64200	0	0	0
T4	2277476	27	0	0
T5	2607020	4	0	0
T6	621780	4	0	0
T7	1574892	2	0	0
T8	282090	4	0	0
T9	0	1	0	0
T14	1033896	9	0	0
T15	1055822	5	0	0
T18	10704	1	0	0
T19	383468	5	0	0
T20	82173	0	0	0
T21	0	2	0	0
T22	0	5	0	0
T27	0	2	0	0
T43	0	9	0	0
T44	0	3	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2756	0	0
T1	28134	1	0	0
T2	58988	1	0	0
T3	64200	0	0	0
T4	2277476	27	0	0
T5	2607020	4	0	0
T6	621780	4	0	0
T7	1574892	2	0	0
T8	282090	4	0	0
T9	0	1	0	0
T14	1033896	8	0	0
T15	1055822	5	0	0
T18	10704	1	0	0
T19	383468	4	0	0
T20	82173	0	0	0
T21	0	2	0	0
T22	0	5	0	0
T27	0	1	0	0
T43	0	9	0	0
T44	0	3	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2702	0	0
T1	28134	1	0	0
T2	58988	1	0	0
T3	64200	0	0	0
T4	2277476	27	0	0
T5	2607020	4	0	0
T6	621780	4	0	0
T7	1574892	2	0	0
T8	282090	4	0	0
T9	0	1	0	0
T14	1033896	8	0	0
T15	1055822	5	0	0
T18	10704	1	0	0
T19	383468	4	0	0
T20	82173	0	0	0
T21	0	2	0	0
T22	0	5	0	0
T27	0	1	0	0
T43	0	9	0	0
T44	0	3	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2638	0	0
T1	28134	1	0	0
T2	58988	1	0	0
T3	64200	0	0	0
T4	2277476	26	0	0
T5	2607020	4	0	0
T6	621780	4	0	0
T7	1574892	2	0	0
T8	282090	4	0	0
T9	0	1	0	0
T14	1033896	8	0	0
T15	1055822	4	0	0
T18	10704	1	0	0
T19	383468	4	0	0
T20	82173	0	0	0
T21	0	2	0	0
T22	0	5	0	0
T27	0	1	0	0
T43	0	9	0	0
T44	0	3	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7263	0	0
T1	84402	12	0	0
T2	88482	0	0	0
T3	128400	6	0	0
T4	2277476	4	0	0
T5	2607020	0	0	0
T6	621780	1	0	0
T7	1574892	0	0	0
T8	141045	0	0	0
T14	1033896	1	0	0
T15	0	1	0	0
T17	0	6	0	0
T18	10704	0	0	0
T19	383468	2	0	0
T20	27391	0	0	0
T21	0	7	0	0
T22	0	5	0	0
T25	0	5	0	0
T27	0	31	0	0
T28	0	67	0	0
T46	0	2	0	0
T47	0	6	0	0
T60	0	1	0	0
T61	0	1	0	0
T64	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T71	0	12	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	739528	0	0
T1	84402	1057	0	0
T2	88482	0	0	0
T3	128400	1029	0	0
T4	2277476	868	0	0
T5	2607020	0	0	0
T6	621780	84	0	0
T7	1574892	0	0	0
T8	141045	0	0	0
T14	1033896	181	0	0
T15	0	1	0	0
T17	0	329	0	0
T18	10704	0	0	0
T19	383468	31	0	0
T20	27391	0	0	0
T21	0	382	0	0
T22	0	1810	0	0
T25	0	1566	0	0
T27	0	5067	0	0
T28	0	4673	0	0
T46	0	293	0	0
T47	0	661	0	0
T60	0	47	0	0
T61	0	210	0	0
T64	0	115	0	0
T68	0	209	0	0
T70	0	162	0	0
T71	0	1611	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6882	0	0
T1	84402	11	0	0
T2	88482	0	0	0
T3	128400	6	0	0
T4	2277476	1	0	0
T5	2607020	0	0	0
T6	621780	1	0	0
T7	1574892	0	0	0
T8	141045	0	0	0
T14	1033896	1	0	0
T17	0	5	0	0
T18	10704	0	0	0
T19	383468	0	0	0
T20	27391	0	0	0
T21	0	4	0	0
T22	0	4	0	0
T23	0	3	0	0
T25	0	5	0	0
T27	0	29	0	0
T28	0	64	0	0
T43	0	3	0	0
T46	0	2	0	0
T47	0	4	0	0
T61	0	9	0	0
T64	0	2	0	0
T71	0	12	0	0
T72	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	244	0	0
T1	28134	1	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T17	285314	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	20572	2	0	0
T22	118616	1	0	0
T23	0	3	0	0
T25	0	5	0	0
T26	0	2	0	0
T27	412482	2	0	0
T28	0	1	0	0
T30	0	1	0	0
T44	115310	0	0	0
T45	1751	0	0	0
T46	216188	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T60	0	1	0	0
T67	1625186	0	0	0
T68	193887	1	0	0
T70	0	1	0	0
T71	139960	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	4	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	651914	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5661	0	0
T11	168036	1432	0	0
T12	0	1419	0	0
T13	0	652	0	0
T30	2567588	0	0	0
T31	2787260	0	0	0
T34	0	686	0	0
T35	0	1472	0	0
T36	1111912	0	0	0
T37	78616	0	0	0
T38	72764	0	0	0
T39	960140	0	0	0
T40	1690608	0	0	0
T41	301724	0	0	0
T42	2953468	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4701	0	0
T11	168036	1192	0	0
T12	0	1179	0	0
T13	0	532	0	0
T30	2567588	0	0	0
T31	2787260	0	0	0
T34	0	566	0	0
T35	0	1232	0	0
T36	1111912	0	0	0
T37	78616	0	0	0
T38	72764	0	0	0
T39	960140	0	0	0
T40	1690608	0	0	0
T41	301724	0	0	0
T42	2953468	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	112536	112264	0	0
T2	117976	117752	0	0
T3	128400	128096	0	0
T4	2277476	2277108	0	0
T5	2607020	2606692	0	0
T6	621780	621748	0	0
T7	1574892	1574868	0	0
T14	1033896	1033872	0	0
T18	10704	10376	0	0
T19	383468	383076	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	112536	112264	0	0
T2	117976	117752	0	0
T3	128400	128096	0	0
T4	2277476	2277108	0	0
T5	2607020	2606692	0	0
T6	621780	621748	0	0
T7	1574892	1574868	0	0
T14	1033896	1033872	0	0
T18	10704	10376	0	0
T19	383468	383076	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T7
1	1	0	Covered	T3,T19,T14
1	1	1	Covered	T1,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T21,T60,T25
1	0	Covered	T4,T19,T17

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T19,T17

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T21,T60,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T4,T5,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T4,T6,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T4,T80,T28

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T4,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T6,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T4,T5
Phase1St	198	Covered	T2,T4,T5
Phase2St	215	Covered	T2,T4,T5
Phase3St	233	Covered	T2,T4,T5
TerminalSt	249	Covered	T2,T4,T5
TimeoutSt	159	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T3,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T81,T82
Phase0St->Phase1St	198	Covered	T2,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T19,T14,T33
Phase1St->Phase2St	215	Covered	T2,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T83,T54
Phase2St->Phase3St	233	Covered	T2,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T84,T85
Phase3St->TerminalSt	249	Covered	T2,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T19,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T27
TimeoutSt->Phase0St	172	Covered	T4,T19,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T19,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T81,T82
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T14,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T83,T54
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T84,T85
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T19,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713683466	278	0	0
CheckAccumTrig0_A	713683466	921	0	0
CheckAccumTrig1_A	713683466	46	0	0
CheckClr_A	713683466	446	0	0
CheckEn_A	713519994	230074493	0	0
CheckPhase0_A	713683466	1017	0	0
CheckPhase1_A	713683466	996	0	0
CheckPhase2_A	713683466	977	0	0
CheckPhase3_A	713683466	960	0	0
CheckTimeout0_A	713683466	2144	0	0
CheckTimeoutSt1_A	713683466	196711	0	0
CheckTimeoutSt2_A	713683466	2027	0	0
CheckTimeoutStTrig_A	713683466	68	0	0
ErrorStAllEscAsserted_A	713683466	1454	0	0
ErrorStIsTerminal_A	713683466	1214	0	0
EscStateOut_A	713518768	713448072	0	0
u_state_regs_A	713683466	713509468	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	278	0	0
T11	42009	52	0	0
T12	0	100	0	0
T13	0	35	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	30	0	0
T35	0	61	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	921	0	0
T2	29494	1	0	0
T3	32100	0	0	0
T4	569369	10	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T14	258474	3	0	0
T15	0	1	0	0
T18	2676	0	0	0
T19	95867	3	0	0
T20	27391	0	0	0
T22	0	4	0	0
T44	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	46	0	0
T4	569369	3	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T14	258474	0	0	0
T15	527911	0	0	0
T17	0	1	0	0
T18	2676	0	0	0
T19	95867	2	0	0
T20	27391	0	0	0
T25	0	2	0	0
T28	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	446	0	0
T4	569369	4	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T14	258474	2	0	0
T15	527911	0	0	0
T17	0	6	0	0
T18	2676	0	0	0
T19	95867	4	0	0
T20	27391	0	0	0
T22	0	2	0	0
T27	0	1	0	0
T28	0	4	0	0
T44	0	2	0	0
T47	0	6	0	0
T48	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713519994	230074493	0	0
T1	28134	599	0	0
T2	29494	2155	0	0
T3	32100	16847	0	0
T4	569369	872298	0	0
T5	651755	582	0	0
T6	155445	3029	0	0
T7	393723	6615	0	0
T14	258474	22125	0	0
T18	2676	2126	0	0
T19	95867	17118	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1017	0	0
T2	29494	1	0	0
T3	32100	0	0	0
T4	569369	12	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T14	258474	3	0	0
T15	0	1	0	0
T18	2676	0	0	0
T19	95867	5	0	0
T20	27391	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	996	0	0
T2	29494	1	0	0
T3	32100	0	0	0
T4	569369	12	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T14	258474	2	0	0
T15	0	1	0	0
T18	2676	0	0	0
T19	95867	4	0	0
T20	27391	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	977	0	0
T2	29494	1	0	0
T3	32100	0	0	0
T4	569369	12	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T14	258474	2	0	0
T15	0	1	0	0
T18	2676	0	0	0
T19	95867	4	0	0
T20	27391	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	960	0	0
T2	29494	1	0	0
T3	32100	0	0	0
T4	569369	11	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T14	258474	2	0	0
T15	0	1	0	0
T18	2676	0	0	0
T19	95867	4	0	0
T20	27391	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	2144	0	0
T1	28134	5	0	0
T2	29494	0	0	0
T3	32100	1	0	0
T4	569369	3	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T17	0	3	0	0
T18	2676	0	0	0
T19	95867	2	0	0
T21	0	1	0	0
T27	0	1	0	0
T28	0	37	0	0
T60	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	196711	0	0
T1	28134	438	0	0
T2	29494	0	0	0
T3	32100	156	0	0
T4	569369	25	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T17	0	70	0	0
T18	2676	0	0	0
T19	95867	31	0	0
T21	0	36	0	0
T27	0	41	0	0
T28	0	2192	0	0
T60	0	47	0	0
T71	0	142	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	2027	0	0
T1	28134	5	0	0
T2	29494	0	0	0
T3	32100	1	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T17	0	2	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T25	0	2	0	0
T27	0	1	0	0
T28	0	36	0	0
T61	0	8	0	0
T64	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	68	0	0
T17	142657	0	0	0
T21	20572	1	0	0
T22	59308	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T27	206241	0	0	0
T44	115310	0	0	0
T45	1751	0	0	0
T46	108094	0	0	0
T53	0	1	0	0
T60	0	1	0	0
T67	812593	0	0	0
T71	69980	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0
T79	0	1	0	0
T80	325957	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1454	0	0
T11	42009	337	0	0
T12	0	364	0	0
T13	0	185	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	188	0	0
T35	0	380	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1214	0	0
T11	42009	277	0	0
T12	0	304	0	0
T13	0	155	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	158	0	0
T35	0	320	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713518768	713448072	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	713509468	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T6
1	0	1	Covered	T4,T6,T18
1	1	0	Covered	T3,T6,T43
1	1	1	Covered	T1,T6,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T21
0	1	Covered	T1,T21,T27
1	0	Covered	T28,T47,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T6,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T47,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T21
1	0	Not Covered
1	1	Covered	T1,T21,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T18,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T5,T9,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T4,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T43,T28

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T18,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T6,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T5
Phase1St	198	Covered	T1,T4,T5
Phase2St	215	Covered	T1,T4,T5
Phase3St	233	Covered	T1,T4,T5
TerminalSt	249	Covered	T1,T4,T5
TimeoutSt	159	Covered	T1,T6,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T5,T6
IdleSt->TimeoutSt	159	Covered	T1,T6,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T26,T31
Phase0St->Phase1St	198	Covered	T1,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T86,T58
Phase1St->Phase2St	215	Covered	T1,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T30,T81,T87
Phase2St->Phase3St	233	Covered	T1,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T17,T73
Phase3St->TerminalSt	249	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T14,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T6,T21
TimeoutSt->Phase0St	172	Covered	T1,T21,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T88,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T86,T58
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T81,T87
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T17,T73
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T14,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713683466	290	0	0
CheckAccumTrig0_A	713683466	503	0	0
CheckAccumTrig1_A	713683466	22	0	0
CheckClr_A	713683466	212	0	0
CheckEn_A	713519994	313559635	0	0
CheckPhase0_A	713683466	562	0	0
CheckPhase1_A	713683466	553	0	0
CheckPhase2_A	713683466	540	0	0
CheckPhase3_A	713683466	528	0	0
CheckTimeout0_A	713683466	2221	0	0
CheckTimeoutSt1_A	713683466	246491	0	0
CheckTimeoutSt2_A	713683466	2147	0	0
CheckTimeoutStTrig_A	713683466	50	0	0
ErrorStAllEscAsserted_A	713683466	1412	0	0
ErrorStIsTerminal_A	713683466	1172	0	0
EscStateOut_A	713518768	713448072	0	0
u_state_regs_A	713683466	713509468	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	290	0	0
T11	42009	54	0	0
T12	0	63	0	0
T13	0	34	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	57	0	0
T35	0	82	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	503	0	0
T4	569369	5	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	141045	1	0	0
T9	0	1	0	0
T14	258474	3	0	0
T15	527911	2	0	0
T18	2676	1	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	2	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	22	0	0
T10	202375	0	0	0
T28	601019	1	0	0
T30	0	1	0	0
T42	0	1	0	0
T47	576979	1	0	0
T48	35234	0	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	43541	0	0	0
T61	74382	0	0	0
T62	14826	0	0	0
T63	166362	0	0	0
T64	110317	0	0	0
T65	1258	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	212	0	0
T4	569369	1	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T14	258474	2	0	0
T15	527911	1	0	0
T17	0	5	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	0	1	0	0
T33	0	1	0	0
T47	0	1	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713519994	313559635	0	0
T1	28134	603	0	0
T2	29494	29437	0	0
T3	32100	14628	0	0
T4	569369	149062	0	0
T5	651755	586	0	0
T6	155445	14689	0	0
T7	393723	393335	0	0
T14	258474	2160	0	0
T18	2676	2142	0	0
T19	95867	95768	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	562	0	0
T1	28134	1	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	5	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	258474	3	0	0
T15	0	2	0	0
T18	2676	1	0	0
T19	95867	0	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	553	0	0
T1	28134	1	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	5	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	258474	3	0	0
T15	0	2	0	0
T18	2676	1	0	0
T19	95867	0	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	540	0	0
T1	28134	1	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	5	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	258474	3	0	0
T15	0	2	0	0
T18	2676	1	0	0
T19	95867	0	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	528	0	0
T1	28134	1	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	5	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	258474	3	0	0
T15	0	1	0	0
T18	2676	1	0	0
T19	95867	0	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	2221	0	0
T1	28134	3	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T17	0	3	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	0	3	0	0
T27	0	28	0	0
T28	0	6	0	0
T46	0	1	0	0
T47	0	4	0	0
T61	0	1	0	0
T64	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	246491	0	0
T1	28134	175	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	84	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T17	0	259	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	0	194	0	0
T27	0	4778	0	0
T28	0	282	0	0
T46	0	60	0	0
T47	0	448	0	0
T61	0	210	0	0
T64	0	115	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	2147	0	0
T1	28134	2	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	1	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T17	0	3	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	0	2	0	0
T27	0	27	0	0
T28	0	4	0	0
T46	0	1	0	0
T47	0	2	0	0
T61	0	1	0	0
T64	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	50	0	0
T1	28134	1	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	0	1	0	0
T23	0	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T47	0	1	0	0
T73	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1412	0	0
T11	42009	361	0	0
T12	0	348	0	0
T13	0	158	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	177	0	0
T35	0	368	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1172	0	0
T11	42009	301	0	0
T12	0	288	0	0
T13	0	128	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	147	0	0
T35	0	308	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713518768	713448072	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	713509468	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T44
1	1	0	Covered	T3,T4,T14
1	1	1	Covered	T1,T21,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T22
0	1	Covered	T22,T27,T68
1	0	Covered	T47,T23,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T21,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T23,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T22
1	0	Covered	T24
1	1	Covered	T22,T27,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T44,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T4,T5,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T6,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T7,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T6,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T15,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T5,T6
Phase1St	198	Covered	T4,T5,T6
Phase2St	215	Covered	T4,T5,T6
Phase3St	233	Covered	T4,T5,T6
TerminalSt	249	Covered	T4,T5,T6
TimeoutSt	159	Covered	T1,T21,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T5,T6
IdleSt->TimeoutSt	159	Covered	T1,T21,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T90,T91
Phase0St->Phase1St	198	Covered	T4,T5,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T32,T90
Phase1St->Phase2St	215	Covered	T4,T5,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T81,T92
Phase2St->Phase3St	233	Covered	T4,T5,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T93,T87
Phase3St->TerminalSt	249	Covered	T4,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T8,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T21,T22
TimeoutSt->Phase0St	172	Covered	T22,T27,T68

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T68
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T90,T91
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T7,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T94,T95
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T7,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T81,T92
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T7,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T93,T87
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T8,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713683466	244	0	0
CheckAccumTrig0_A	713683466	545	0	0
CheckAccumTrig1_A	713683466	32	0	0
CheckClr_A	713683466	259	0	0
CheckEn_A	713519994	283174540	0	0
CheckPhase0_A	713683466	625	0	0
CheckPhase1_A	713683466	608	0	0
CheckPhase2_A	713683466	596	0	0
CheckPhase3_A	713683466	577	0	0
CheckTimeout0_A	713683466	1455	0	0
CheckTimeoutSt1_A	713683466	176613	0	0
CheckTimeoutSt2_A	713683466	1361	0	0
CheckTimeoutStTrig_A	713683466	60	0	0
ErrorStAllEscAsserted_A	713683466	1399	0	0
ErrorStIsTerminal_A	713683466	1159	0	0
EscStateOut_A	713518768	713448072	0	0
u_state_regs_A	713683466	713509468	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	244	0	0
T11	42009	59	0	0
T12	0	48	0	0
T13	0	29	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	16	0	0
T35	0	92	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	545	0	0
T4	569369	7	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	2	0	0
T14	258474	1	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	2	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	32	0	0
T23	0	2	0	0
T32	0	2	0	0
T33	299376	0	0	0
T42	0	1	0	0
T47	576979	1	0	0
T48	35234	0	0	0
T54	0	1	0	0
T61	74382	0	0	0
T62	14826	0	0	0
T63	166362	0	0	0
T64	110317	0	0	0
T65	1258	0	0	0
T66	48463	0	0	0
T69	737318	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T87	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	259	0	0
T4	569369	3	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	1	0	0
T14	258474	0	0	0
T15	527911	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	1	0	0
T28	0	2	0	0
T47	0	2	0	0
T49	0	1	0	0
T63	0	2	0	0
T68	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713519994	283174540	0	0
T1	28134	607	0	0
T2	29494	29437	0	0
T3	32100	32023	0	0
T4	569369	153302	0	0
T5	651755	590	0	0
T6	155445	4325	0	0
T7	393723	2109	0	0
T14	258474	6400	0	0
T18	2676	2153	0	0
T19	95867	95768	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	625	0	0
T4	569369	7	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	2	0	0
T14	258474	1	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	3	0	0
T27	0	2	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	608	0	0
T4	569369	7	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	2	0	0
T14	258474	1	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	3	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	596	0	0
T4	569369	7	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	2	0	0
T14	258474	1	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	3	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	577	0	0
T4	569369	7	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	2	0	0
T14	258474	1	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	3	0	0
T27	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1455	0	0
T1	28134	4	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T25	0	5	0	0
T27	0	2	0	0
T28	0	20	0	0
T47	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T71	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	176613	0	0
T1	28134	444	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	0	46	0	0
T22	0	897	0	0
T25	0	1566	0	0
T27	0	248	0	0
T28	0	1059	0	0
T47	0	213	0	0
T68	0	209	0	0
T70	0	162	0	0
T71	0	632	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1361	0	0
T1	28134	4	0	0
T2	29494	0	0	0
T3	32100	0	0	0
T4	569369	0	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T14	258474	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	3	0	0
T25	0	3	0	0
T27	0	1	0	0
T28	0	20	0	0
T47	0	1	0	0
T71	0	5	0	0
T72	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	60	0	0
T17	142657	0	0	0
T22	59308	1	0	0
T23	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	206241	1	0	0
T28	601019	0	0	0
T46	108094	0	0	0
T67	812593	0	0	0
T68	193887	1	0	0
T70	0	1	0	0
T71	69980	0	0	0
T76	0	1	0	0
T78	0	1	0	0
T80	325957	0	0	0
T81	0	2	0	0
T98	467841	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1399	0	0
T11	42009	350	0	0
T12	0	360	0	0
T13	0	155	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	161	0	0
T35	0	373	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1159	0	0
T11	42009	290	0	0
T12	0	300	0	0
T13	0	125	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	131	0	0
T35	0	313	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713518768	713448072	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	713509468	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T4,T9,T43
1	1	0	Covered	T1,T4,T14
1	1	1	Covered	T3,T4,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T14
0	1	Covered	T43,T21,T69
1	0	Covered	T15,T47,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T47,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T14
1	0	Covered	T23
1	1	Covered	T43,T21,T69

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T6,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T14
1	Covered	T5,T7,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T22,T67

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T43,T28

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T14,T43

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T5,T6
Phase1St	198	Covered	T4,T5,T6
Phase2St	215	Covered	T4,T5,T6
Phase3St	233	Covered	T4,T5,T6
TerminalSt	249	Covered	T4,T5,T6
TimeoutSt	159	Covered	T3,T4,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T4,T5,T6
IdleSt->TimeoutSt	159	Covered	T3,T4,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T88,T99,T100
Phase0St->Phase1St	198	Covered	T4,T5,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T46,T25,T101
Phase1St->Phase2St	215	Covered	T4,T5,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T55,T102,T103
Phase2St->Phase3St	233	Covered	T4,T5,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T68,T47,T104
Phase3St->TerminalSt	249	Covered	T4,T5,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T14,T43
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T14
TimeoutSt->Phase0St	172	Covered	T15,T43,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T43,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T99,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T5,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T46,T25,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T5,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T5,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T55,T102,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T5,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T5,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T68,T47,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T5,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T5,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T14,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713683466	291	0	0
CheckAccumTrig0_A	713683466	529	0	0
CheckAccumTrig1_A	713683466	28	0	0
CheckClr_A	713683466	265	0	0
CheckEn_A	713519994	301351325	0	0
CheckPhase0_A	713683466	613	0	0
CheckPhase1_A	713683466	599	0	0
CheckPhase2_A	713683466	589	0	0
CheckPhase3_A	713683466	573	0	0
CheckTimeout0_A	713683466	1443	0	0
CheckTimeoutSt1_A	713683466	119713	0	0
CheckTimeoutSt2_A	713683466	1347	0	0
CheckTimeoutStTrig_A	713683466	66	0	0
ErrorStAllEscAsserted_A	713683466	1396	0	0
ErrorStIsTerminal_A	713683466	1156	0	0
EscStateOut_A	713518768	713448072	0	0
u_state_regs_A	713683466	713509468	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	291	0	0
T11	42009	90	0	0
T12	0	72	0	0
T13	0	25	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	37	0	0
T35	0	67	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	529	0	0
T4	569369	3	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	0	0	0
T14	258474	2	0	0
T15	527911	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	2	0	0
T27	0	1	0	0
T43	0	7	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	28	0	0
T9	571939	0	0	0
T15	527911	1	0	0
T16	26381	0	0	0
T21	20572	0	0	0
T22	59308	0	0	0
T23	0	1	0	0
T25	0	1	0	0
T27	206241	0	0	0
T43	206205	0	0	0
T44	115310	0	0	0
T45	1751	0	0	0
T46	108094	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T81	0	1	0	0
T92	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	265	0	0
T4	569369	1	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T14	258474	1	0	0
T15	527911	0	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T22	0	1	0	0
T28	0	9	0	0
T43	0	8	0	0
T46	0	1	0	0
T47	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T80	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713519994	301351325	0	0
T1	28134	28065	0	0
T2	29494	29437	0	0
T3	32100	2121	0	0
T4	569369	138776	0	0
T5	651755	4090	0	0
T6	155445	4329	0	0
T7	393723	5595	0	0
T14	258474	51286	0	0
T18	2676	2166	0	0
T19	95867	95768	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	613	0	0
T4	569369	3	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	0	0	0
T14	258474	2	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T43	0	8	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	599	0	0
T4	569369	3	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	0	0	0
T14	258474	2	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T43	0	8	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	589	0	0
T4	569369	3	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	0	0	0
T14	258474	2	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T43	0	8	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	573	0	0
T4	569369	3	0	0
T5	651755	1	0	0
T6	155445	1	0	0
T7	393723	1	0	0
T8	141045	0	0	0
T14	258474	2	0	0
T15	527911	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T43	0	8	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1443	0	0
T3	32100	5	0	0
T4	569369	1	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T14	258474	1	0	0
T15	0	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T21	0	2	0	0
T22	0	3	0	0
T28	0	4	0	0
T43	0	4	0	0
T46	0	1	0	0
T71	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	119713	0	0
T3	32100	873	0	0
T4	569369	843	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T14	258474	181	0	0
T15	0	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T21	0	106	0	0
T22	0	913	0	0
T28	0	1140	0	0
T43	0	870	0	0
T46	0	233	0	0
T71	0	837	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1347	0	0
T3	32100	5	0	0
T4	569369	1	0	0
T5	651755	0	0	0
T6	155445	0	0	0
T7	393723	0	0	0
T8	141045	0	0	0
T14	258474	1	0	0
T18	2676	0	0	0
T19	95867	0	0	0
T20	27391	0	0	0
T21	0	1	0	0
T22	0	3	0	0
T28	0	4	0	0
T43	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T71	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	66	0	0
T17	142657	0	0	0
T21	20572	1	0	0
T22	59308	0	0	0
T23	0	1	0	0
T25	0	1	0	0
T27	206241	0	0	0
T42	0	4	0	0
T43	206205	1	0	0
T44	115310	0	0	0
T45	1751	0	0	0
T46	108094	0	0	0
T49	0	5	0	0
T69	0	1	0	0
T71	69980	0	0	0
T80	325957	0	0	0
T84	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1396	0	0
T11	42009	384	0	0
T12	0	347	0	0
T13	0	154	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	160	0	0
T35	0	351	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	1156	0	0
T11	42009	324	0	0
T12	0	287	0	0
T13	0	124	0	0
T30	641897	0	0	0
T31	696815	0	0	0
T34	0	130	0	0
T35	0	291	0	0
T36	277978	0	0	0
T37	19654	0	0	0
T38	18191	0	0	0
T39	240035	0	0	0
T40	422652	0	0	0
T41	75431	0	0	0
T42	738367	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713518768	713448072	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713683466	713509468	0	0
T1	28134	28066	0	0
T2	29494	29438	0	0
T3	32100	32024	0	0
T4	569369	569277	0	0
T5	651755	651673	0	0
T6	155445	155437	0	0
T7	393723	393717	0	0
T14	258474	258468	0	0
T18	2676	2594	0	0
T19	95867	95769	0	0