Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
class_index_cp 4 0 4 100.00 100 1 1 0
esc_index_cp 4 0 4 100.00 100 1 1 0
loc_alert_cause_cp 2 0 2 100.00 100 1 1 0


Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
loc_alert_cause_cross_alert_index 8 0 8 100.00 100 1 1 0
loc_alert_cause_cross_class_index 8 0 8 100.00 100 1 1 0


Summary for Variable class_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for class_index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
class_i[0x0] 57612 1 T1 9 T3 3 T4 3
class_i[0x1] 68586 1 T1 4 T4 4 T7 8
class_i[0x2] 56369 1 T1 3214 T4 1 T7 10
class_i[0x3] 61091 1 T4 11 T7 173 T43 1772



Summary for Variable esc_index_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for esc_index_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
alert[0x0] 64645 1 T1 820 T3 2 T4 10
alert[0x1] 61434 1 T1 785 T3 1 T7 209
alert[0x2] 58645 1 T1 836 T4 7 T8 2
alert[0x3] 58934 1 T1 786 T4 2 T8 1



Summary for Variable loc_alert_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail 243404 1 T1 3227 T4 12 T7 812
esc_ping_fail 254 1 T3 3 T4 7 T8 4



Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins
loc_alert_cause_cpesc_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail alert[0x0] 64574 1 T1 820 T4 6 T7 203
esc_integrity_fail alert[0x1] 61370 1 T1 785 T7 209 T15 3
esc_integrity_fail alert[0x2] 58587 1 T1 836 T4 5 T7 234
esc_integrity_fail alert[0x3] 58873 1 T1 786 T4 1 T7 166
esc_ping_fail alert[0x0] 71 1 T3 2 T4 4 T8 1
esc_ping_fail alert[0x1] 64 1 T3 1 T70 3 T312 2
esc_ping_fail alert[0x2] 58 1 T4 2 T8 2 T70 1
esc_ping_fail alert[0x3] 61 1 T4 1 T8 1 T70 1



Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins
loc_alert_cause_cpclass_index_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
esc_integrity_fail class_i[0x0] 57561 1 T1 9 T4 2 T7 621
esc_integrity_fail class_i[0x1] 68508 1 T1 4 T7 8 T43 121
esc_integrity_fail class_i[0x2] 56307 1 T1 3214 T7 10 T21 1152
esc_integrity_fail class_i[0x3] 61028 1 T4 10 T7 173 T43 1772
esc_ping_fail class_i[0x0] 51 1 T3 3 T4 1 T8 4
esc_ping_fail class_i[0x1] 78 1 T4 4 T70 6 T322 11
esc_ping_fail class_i[0x2] 62 1 T4 1 T312 7 T320 7
esc_ping_fail class_i[0x3] 63 1 T4 1 T300 1 T314 4

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