Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	689880002	0	0	628
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	689880002	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	689880002	689716350	0	0
tb.dut.CheckAccuCntDw	0	0	628	628	0	0
tb.dut.CheckEscCntDw	0	0	628	628	0	0
tb.dut.CheckNAlerts	0	0	628	628	0	0
tb.dut.CheckNClasses	0	0	628	628	0	0
tb.dut.CheckNEscSev	0	0	628	628	0	0
tb.dut.CrashdumpKnownO_A	0	0	689880002	689716350	0	0
tb.dut.EdnKnownO_A	0	0	689880002	689716350	0	0
tb.dut.EscPKnownO_A	0	0	689880002	689716350	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	689880002	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	689880002	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	689880002	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	689880002	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	689880002	70	0	0
tb.dut.IrqAKnownO_A	0	0	689880002	689716350	0	0
tb.dut.IrqBKnownO_A	0	0	689880002	689716350	0	0
tb.dut.IrqCKnownO_A	0	0	689880002	689716350	0	0
tb.dut.IrqDKnownO_A	0	0	689880002	689716350	0	0
tb.dut.TlAReadyKnownO_A	0	0	689880002	689716350	0	0
tb.dut.TlDValidKnownO_A	0	0	689880002	689716350	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	713972464	2773858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	713972464	11491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	713972464	10849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	713972464	11427	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	713972464	11120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	713972464	11295	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	713972464	11736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	713972464	11244	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	713972464	11329	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	713972464	11376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	713972464	11582	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	713972464	11495	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	713972464	11176	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	713972464	11847	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	713972464	11100	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	713972464	11279	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	713972464	10937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	713972464	11373	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	713972464	11037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	713972464	11280	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	713972464	11480	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	713972464	11307	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	713972464	11121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	713972464	11212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	713972464	11298	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	713972464	11345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	713972464	11272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	713972464	11449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	713972464	10944	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	713972464	11554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	713972464	11528	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	713972464	10979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	713972464	11235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	713972464	11310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	713972464	11261	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	713972464	11464	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	713972464	11410	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	713972464	11167	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	713972464	11310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	713972464	11416	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	713972464	11136	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	713972464	11427	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	713972464	11226	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	713972464	11232	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	713972464	11013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	713972464	11247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	713972464	11004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	713972464	11326	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	713972464	11357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	713972464	11449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	713972464	11923	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	713972464	11295	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	713972464	11181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	713972464	11419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	713972464	11417	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	713972464	11369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	713972464	11370	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	713972464	11473	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	713972464	11400	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	713972464	11255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	713972464	11468	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	713972464	11360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	713972464	11280	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	713972464	11267	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	713972464	10943	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	713972464	11340	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	713972464	11153	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	713972464	11403	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	713972464	11368	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	713972464	11259	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	713972464	19981	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	713972464	10866	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	713972464	11511	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	713972464	11313	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	713972464	11262	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	713972464	11242	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	713972464	11251	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	713972464	11163	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	713972464	11417	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	689880002	5768	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	689880002	211786	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	689880002	396568778	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	689880002	209	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	689880002	850	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	689880002	51	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	689880002	408	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	689749940	278506665	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	689880002	957	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	689880002	940	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	689880002	916	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	689880002	897	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	689880002	1221	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	689880002	136270	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	689880002	1095	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	689880002	73	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	689880002	1264	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	689880002	1054	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	689748954	689674702	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	689880002	689716350	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	689880002	2348	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	689880002	216881	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	689880002	382775565	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	689880002	240	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	689880002	486	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	689880002	27	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	689880002	214	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	689749940	315935051	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	689880002	573	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	689880002	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	689880002	558	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	689880002	545	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	689880002	1311	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	689880002	153244	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	689880002	1209	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	689880002	73	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	689880002	1160	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	689880002	950	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	689748954	689674702	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	689880002	689716350	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	689880002	3158	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	689880002	198000	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	689880002	357374568	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	689880002	198	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	689880002	531	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	689880002	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	689880002	224	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	689749940	271699092	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	689880002	610	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	689880002	604	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	689880002	592	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	689880002	580	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	689880002	793	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	689880002	104951	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	689880002	705	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	689880002	67	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	689880002	1203	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	689880002	993	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	689748954	689674702	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	689880002	689716350	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	689880002	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	689880002	919	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	689880002	221324	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	689880002	361857216	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	689880002	241	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	689880002	507	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	689880002	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	689880002	200	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	689749940	275307199	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	689880002	584	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	689880002	572	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	689880002	564	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	689880002	557	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	689880002	1587	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	689880002	150781	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	689880002	1500	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	689880002	69	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	689880002	1261	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	689880002	1051	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	689748954	689674702	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	689880002	689716350	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	713972464	127226351	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	713972464	713315727	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	713972464	713315727	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	713972464	182836327	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	713972464	713315727	0	0
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tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0

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