Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	195	1			T5	12		T16	1		T21	1
index[0x1]	224	1			T7	1		T5	1		T16	1
index[0x2]	177	1			T4	1		T7	1		T21	2
index[0x3]	194	1			T5	2		T21	2		T81	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	247	1			T5	15		T21	4		T42	1
lens_less_than_1000[1]	147	1			T81	1		T45	2		T14	1
lens_less_than_1000[2]	114	1			T4	1		T12	7		T13	1
lens_less_than_1000[3]	109	1			T7	1		T16	2		T21	1
lens_less_than_1000[4]	65	1			T7	1		T21	1		T48	2
lens_less_than_1000[5]	45	1			T48	1		T22	1		T29	1
lens_less_than_1000[6]	23	1			T22	1		T52	1		T90	2
lens_less_than_1000[7]	13	1			T21	1		T31	1		T282	1
lens_less_than_1000[8]	8	1			T74	1		T109	2		T283	1
lens_less_than_1000[9]	5	1			T284	1		T115	1		T285	1
len_2	14	1			T30	1		T53	1		T31	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	59	1			T5	12		T21	1		T29	1
index[0x0]	lens_less_than_1000[1]	40	1			T45	1		T77	1		T286	1
index[0x0]	lens_less_than_1000[2]	33	1			T30	1		T286	1		T260	1
index[0x0]	lens_less_than_1000[3]	34	1			T16	1		T47	1		T41	1
index[0x0]	lens_less_than_1000[4]	14	1			T48	1		T287	1		T288	1
index[0x0]	lens_less_than_1000[5]	7	1			T289	5		T290	1		T99	1
index[0x0]	lens_less_than_1000[6]	3	1			T22	1		T272	1		T291	1
index[0x0]	lens_less_than_1000[7]	2	1			T292	1		T256	1		-	-
index[0x0]	lens_less_than_1000[9]	2	1			T284	1		T293	1		-	-
index[0x0]	len_2	1	1			T31	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	71	1			T5	1		T21	1		T73	1
index[0x1]	lens_less_than_1000[1]	37	1			T23	2		T286	1		T31	1
index[0x1]	lens_less_than_1000[2]	23	1			T29	2		T31	1		T239	1
index[0x1]	lens_less_than_1000[3]	30	1			T7	1		T16	1		T198	1
index[0x1]	lens_less_than_1000[4]	27	1			T21	1		T48	1		T75	1
index[0x1]	lens_less_than_1000[5]	16	1			T22	1		T57	2		T95	3
index[0x1]	lens_less_than_1000[6]	4	1			T60	1		T96	1		T294	1
index[0x1]	lens_less_than_1000[7]	5	1			T282	1		T288	1		T295	1
index[0x1]	lens_less_than_1000[8]	4	1			T74	1		T109	1		T296	1
index[0x1]	len_2	7	1			T224	1		T91	1		T64	1
index[0x2]	lens_less_than_1000[0]	51	1			T72	1		T30	1		T297	1
index[0x2]	lens_less_than_1000[1]	36	1			T76	1		T298	1		T87	2
index[0x2]	lens_less_than_1000[2]	23	1			T4	1		T12	4		T13	1
index[0x2]	lens_less_than_1000[3]	27	1			T21	1		T86	2		T198	1
index[0x2]	lens_less_than_1000[4]	11	1			T7	1		T239	1		T109	1
index[0x2]	lens_less_than_1000[5]	8	1			T48	1		T299	1		T300	1
index[0x2]	lens_less_than_1000[6]	9	1			T52	1		T90	1		T57	5
index[0x2]	lens_less_than_1000[7]	3	1			T21	1		T301	1		T302	1
index[0x2]	lens_less_than_1000[8]	3	1			T109	1		T283	1		T303	1
index[0x2]	lens_less_than_1000[9]	2	1			T115	1		T293	1		-	-
index[0x2]	len_2	4	1			T53	1		T304	1		T281	1
index[0x3]	lens_less_than_1000[0]	66	1			T5	2		T21	2		T42	1
index[0x3]	lens_less_than_1000[1]	34	1			T81	1		T45	1		T14	1
index[0x3]	lens_less_than_1000[2]	35	1			T12	3		T74	1		T52	1
index[0x3]	lens_less_than_1000[3]	18	1			T86	3		T110	1		T61	1
index[0x3]	lens_less_than_1000[4]	13	1			T49	1		T260	1		T298	1
index[0x3]	lens_less_than_1000[5]	14	1			T29	1		T57	2		T117	2
index[0x3]	lens_less_than_1000[6]	7	1			T90	1		T109	1		T63	1
index[0x3]	lens_less_than_1000[7]	3	1			T31	1		T305	1		T255	1
index[0x3]	lens_less_than_1000[8]	1	1			T263	1		-	-		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T285	1		-	-		-	-
index[0x3]	len_2	2	1			T30	1		T263	1		-	-