Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	73	1			T21	2		T81	1		T43	1
class_index[0x1]	73	1			T15	1		T21	3		T83	1
class_index[0x2]	67	1			T7	6		T21	1		T84	1
class_index[0x3]	69	1			T21	2		T84	1		T46	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	95	1			T83	1		T45	2		T76	2
intr_timeout_cnt[1]	70	1			T7	6		T15	1		T21	1
intr_timeout_cnt[2]	34	1			T21	1		T46	1		T24	1
intr_timeout_cnt[3]	25	1			T29	1		T87	1		T198	1
intr_timeout_cnt[4]	9	1			T86	3		T57	1		T266	1
intr_timeout_cnt[5]	7	1			T21	1		T28	2		T261	1
intr_timeout_cnt[6]	20	1			T43	1		T75	1		T52	1
intr_timeout_cnt[7]	8	1			T21	1		T87	1		T88	1
intr_timeout_cnt[8]	5	1			T21	3		T110	1		T233	1
intr_timeout_cnt[9]	9	1			T21	1		T57	1		T267	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[4] , intr_timeout_cnt[5]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T76	1		T29	1		T86	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T81	1		T85	1		T268	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T267	2		T64	1		T92	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T198	1		T57	1		T110	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T57	1		T266	1		T189	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T28	2		T25	1		T269	1
class_index[0x0]	intr_timeout_cnt[6]	9	1			T43	1		T52	1		T31	2
class_index[0x0]	intr_timeout_cnt[7]	2	1			T87	1		T270	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T21	2		T233	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T270	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	21	1			T83	1		T29	1		T30	4
class_index[0x1]	intr_timeout_cnt[1]	19	1			T15	1		T29	2		T30	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T21	1		T24	1		T263	1
class_index[0x1]	intr_timeout_cnt[3]	11	1			T87	1		T31	8		T228	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T271	1		T269	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	2	1			T21	1		T272	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T273	1		T267	1		T274	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T88	1		T275	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T21	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	3	1			T57	1		T267	1		T96	1
class_index[0x2]	intr_timeout_cnt[0]	24	1			T45	2		T88	6		T110	1
class_index[0x2]	intr_timeout_cnt[1]	21	1			T7	6		T21	1		T84	1
class_index[0x2]	intr_timeout_cnt[2]	8	1			T29	1		T276	1		T64	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T114	1		T270	2		T277	2
class_index[0x2]	intr_timeout_cnt[6]	2	1			T92	1		T269	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T278	1		T279	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T110	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	4	1			T280	1		T281	1		T251	2
class_index[0x3]	intr_timeout_cnt[0]	23	1			T76	1		T30	2		T87	1
class_index[0x3]	intr_timeout_cnt[1]	18	1			T84	1		T58	1		T64	3
class_index[0x3]	intr_timeout_cnt[2]	10	1			T46	1		T75	1		T86	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T29	1		T267	1		T228	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T86	3		T228	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T261	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	6	1			T75	1		T57	1		T96	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T21	1		T281	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T21	1		-	-		-	-