Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353755	1			T1	1285		T2	5		T3	19
all_values[1]	353755	1			T1	1285		T2	5		T3	19
all_values[2]	353755	1			T1	1285		T2	5		T3	19
all_values[3]	353755	1			T1	1285		T2	5		T3	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703833

1

T1

2637

T7

1645

T5

1942

auto[1]

711187

1

T1

2503

T2

20

T3

76

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

840179

1

T1

2907

T2

12

T3

67

auto[1]

574841

1

T1

2233

T2

8

T3

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102323	1			T1	367		T7	223		T5	257
all_values[0]	auto[0]	auto[1]	73931	1			T1	317		T7	216		T5	232
all_values[0]	auto[1]	auto[0]	103329	1			T1	342		T2	3		T3	16
all_values[0]	auto[1]	auto[1]	74172	1			T1	259		T2	2		T3	3
all_values[1]	auto[0]	auto[0]	105046	1			T1	388		T7	288		T5	239
all_values[1]	auto[0]	auto[1]	71259	1			T1	268		T7	118		T5	239
all_values[1]	auto[1]	auto[0]	105817	1			T1	368		T2	3		T3	19
all_values[1]	auto[1]	auto[1]	71633	1			T1	261		T2	2		T4	4
all_values[2]	auto[0]	auto[0]	104191	1			T1	328		T7	310		T5	250
all_values[2]	auto[0]	auto[1]	71389	1			T1	315		T7	101		T5	247
all_values[2]	auto[1]	auto[0]	106575	1			T1	324		T2	3		T3	19
all_values[2]	auto[1]	auto[1]	71600	1			T1	318		T2	2		T4	3
all_values[3]	auto[0]	auto[0]	105455	1			T1	401		T7	287		T5	239
all_values[3]	auto[0]	auto[1]	70239	1			T1	253		T7	102		T5	239
all_values[3]	auto[1]	auto[0]	107443	1			T1	389		T2	3		T3	13
all_values[3]	auto[1]	auto[1]	70618	1			T1	242		T2	2		T3	6