Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353755	1			T1	1285		T2	5		T3	19
all_pins[1]	353755	1			T1	1285		T2	5		T3	19
all_pins[2]	353755	1			T1	1285		T2	5		T3	19
all_pins[3]	353755	1			T1	1285		T2	5		T3	19

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1126997	1			T1	4060		T2	12		T3	67
values[0x1]	288023	1			T1	1080		T2	8		T3	9
transitions[0x0=>0x1]	190346	1			T1	723		T2	1		T3	9
transitions[0x1=>0x0]	190589	1			T1	723		T2	2		T3	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	279583	1			T1	1026		T2	3		T3	16
all_pins[0]	values[0x1]	74172	1			T1	259		T2	2		T3	3
all_pins[0]	transitions[0x0=>0x1]	73480	1			T1	259		T2	1		T3	3
all_pins[0]	transitions[0x1=>0x0]	70169	1			T1	242		T2	2		T3	6
all_pins[1]	values[0x0]	282122	1			T1	1024		T2	3		T3	19
all_pins[1]	values[0x1]	71633	1			T1	261		T2	2		T4	4
all_pins[1]	transitions[0x0=>0x1]	39305	1			T1	156		T4	4		T8	1
all_pins[1]	transitions[0x1=>0x0]	41844	1			T1	154		T3	3		T4	14
all_pins[2]	values[0x0]	282155	1			T1	967		T2	3		T3	19
all_pins[2]	values[0x1]	71600	1			T1	318		T2	2		T4	3
all_pins[2]	transitions[0x0=>0x1]	39019	1			T1	184		T4	3		T7	53
all_pins[2]	transitions[0x1=>0x0]	39052	1			T1	127		T4	4		T8	1
all_pins[3]	values[0x0]	283137	1			T1	1043		T2	3		T3	13
all_pins[3]	values[0x1]	70618	1			T1	242		T2	2		T3	6
all_pins[3]	transitions[0x0=>0x1]	38542	1			T1	124		T3	6		T4	5
all_pins[3]	transitions[0x1=>0x0]	39524	1			T1	200		T4	2		T7	48