Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T162	4		T163	7		T164	4
all_values[1]	281	1			T162	4		T163	7		T164	4
all_values[2]	281	1			T162	4		T163	7		T164	4
all_values[3]	281	1			T162	4		T163	7		T164	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603

1

T162

13

T163

12

T164

12

auto[1]

521

1

T162

3

T163

16

T164

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

426

1

T162

8

T163

10

T164

6

auto[1]

698

1

T162

8

T163

18

T164

10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T162

10

T163

16

T164

10

auto[1]

480

1

T162

6

T163

12

T164

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

76

1

T162

3

T163

1

T252

1

all_values[0]

auto[0]

auto[0]

auto[1]

23

1

T361

1

T362

1

T363

1

all_values[0]

auto[0]

auto[1]

auto[0]

34

1

T163

3

T252

1

T364

4

all_values[0]

auto[0]

auto[1]

auto[1]

32

1

T164

1

T365

2

T366

1

all_values[0]

auto[1]

auto[0]

auto[1]

54

1

T162

1

T163

1

T164

2

all_values[0]

auto[1]

auto[1]

auto[1]

62

1

T163

2

T164

1

T365

1

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T162

1

T163

1

T252

1

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T164

2

T252

1

T367

1

all_values[1]

auto[0]

auto[1]

auto[0]

38

1

T163

1

T252

1

T366

1

all_values[1]

auto[0]

auto[1]

auto[1]

32

1

T162

1

T163

2

T164

1

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T162

1

T164

1

T252

1

all_values[1]

auto[1]

auto[1]

auto[1]

58

1

T162

1

T163

3

T365

1

all_values[2]

auto[0]

auto[0]

auto[0]

63

1

T162

4

T163

1

T164

2

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T163

1

T361

1

T362

2

all_values[2]

auto[0]

auto[1]

auto[0]

52

1

T163

1

T252

3

T365

1

all_values[2]

auto[0]

auto[1]

auto[1]

29

1

T163

1

T366

2

T362

2

all_values[2]

auto[1]

auto[0]

auto[1]

62

1

T163

2

T164

2

T365

1

all_values[2]

auto[1]

auto[1]

auto[1]

51

1

T163

1

T252

1

T365

1

all_values[3]

auto[0]

auto[0]

auto[0]

49

1

T163

1

T164

3

T366

1

all_values[3]

auto[0]

auto[0]

auto[1]

27

1

T162

1

T163

1

T365

2

all_values[3]

auto[0]

auto[1]

auto[0]

53

1

T163

1

T164

1

T252

1

all_values[3]

auto[0]

auto[1]

auto[1]

24

1

T163

1

T365

1

T364

1

all_values[3]

auto[1]

auto[0]

auto[1]

72

1

T162

2

T163

3

T365

1

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T162

1

T252

3

T366

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal