Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	99347	1			T7	44		T5	514		T13	376
accum_cnt_1000	224960	1			T1	819		T7	270		T5	899
accum_cnt_100	28219	1			T1	59		T7	134		T5	43
accum_cnt_50	64334	1			T1	1011		T4	11		T7	118
accum_cnt_10	212624	1			T1	20		T2	1		T3	18
accum_cnt_0	367396	1			T1	1919		T2	7		T3	46

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	261039	1			T1	957		T2	2		T3	16
class_index[0x1]	261039	1			T1	957		T2	2		T3	16
class_index[0x2]	261039	1			T1	957		T2	2		T3	16
class_index[0x3]	261039	1			T1	957		T2	2		T3	16

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25023	1			T7	44		T13	376		T48	144
class_index[0x0]	accum_cnt_1000	57095	1			T7	191		T21	227		T42	51
class_index[0x0]	accum_cnt_100	6756	1			T7	18		T21	88		T42	12
class_index[0x0]	accum_cnt_50	16401	1			T4	11		T7	14		T21	71
class_index[0x0]	accum_cnt_10	64960	1			T3	10		T4	19		T7	63
class_index[0x0]	accum_cnt_0	80774	1			T1	957		T2	2		T3	6
class_index[0x1]	accum_cnt_2000	22602	1			T71	232		T29	30		T30	168
class_index[0x1]	accum_cnt_1000	53260	1			T22	24		T67	394		T71	203
class_index[0x1]	accum_cnt_100	6551	1			T21	34		T83	14		T48	7
class_index[0x1]	accum_cnt_50	19481	1			T15	16		T21	44		T51	8
class_index[0x1]	accum_cnt_10	40593	1			T8	1		T7	66		T15	10
class_index[0x1]	accum_cnt_0	105541	1			T1	957		T2	2		T3	16
class_index[0x2]	accum_cnt_2000	24962	1			T5	200		T14	449		T71	7
class_index[0x2]	accum_cnt_1000	59153	1			T7	49		T5	508		T21	95
class_index[0x2]	accum_cnt_100	6504	1			T7	102		T5	24		T21	69
class_index[0x2]	accum_cnt_50	15214	1			T1	950		T7	90		T5	21
class_index[0x2]	accum_cnt_10	53500	1			T1	5		T2	1		T4	32
class_index[0x2]	accum_cnt_0	90306	1			T1	2		T2	1		T3	16
class_index[0x3]	accum_cnt_2000	26760	1			T5	314		T14	746		T22	233
class_index[0x3]	accum_cnt_1000	55452	1			T1	819		T7	30		T5	391
class_index[0x3]	accum_cnt_100	8408	1			T1	59		T7	14		T5	19
class_index[0x3]	accum_cnt_50	13238	1			T1	61		T7	14		T5	13
class_index[0x3]	accum_cnt_10	53571	1			T1	15		T3	8		T4	9
class_index[0x3]	accum_cnt_0	90775	1			T1	3		T2	2		T3	8