Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	17887	1			T7	4		T13	3		T49	111
alert[0x1]	4559	1			T8	1		T48	43		T49	10
alert[0x2]	4283	1			T4	1		T7	4		T21	4
alert[0x3]	3530	1			T13	2		T30	14		T93	4
alert[0x4]	1523	1			T7	16		T21	1		T29	44
alert[0x5]	5211	1			T8	1		T13	4		T22	4
alert[0x6]	2359	1			T21	2		T29	161		T78	1
alert[0x7]	11329	1			T4	1		T15	1		T86	47
alert[0x8]	8287	1			T15	1		T49	493		T29	5
alert[0x9]	3765	1			T7	123		T13	28		T48	88
alert[0xa]	4319	1			T4	1		T43	1		T86	81
alert[0xb]	7702	1			T3	1		T4	1		T7	9
alert[0xc]	4425	1			T49	156		T93	588		T311	1
alert[0xd]	6973	1			T4	1		T7	27		T48	5
alert[0xe]	2618	1			T8	1		T7	59		T21	2
alert[0xf]	10531	1			T43	1		T70	1		T30	2
alert[0x10]	2460	1			T4	1		T43	3		T13	8
alert[0x11]	11640	1			T7	3		T15	1		T48	17
alert[0x12]	4070	1			T13	4		T48	386		T70	1
alert[0x13]	2724	1			T7	7		T13	2		T49	4
alert[0x14]	3418	1			T7	33		T49	29		T23	4
alert[0x15]	3092	1			T4	1		T7	3		T48	69
alert[0x16]	3282	1			T7	3		T15	7		T29	23
alert[0x17]	4122	1			T43	2		T29	7		T30	14
alert[0x18]	6795	1			T8	1		T7	6		T21	2
alert[0x19]	14042	1			T43	2		T23	5		T29	6434
alert[0x1a]	5336	1			T48	4		T75	3		T29	21
alert[0x1b]	3791	1			T8	1		T15	7		T43	15
alert[0x1c]	9031	1			T7	13		T21	4		T48	44
alert[0x1d]	10648	1			T8	2		T7	12		T15	3
alert[0x1e]	4808	1			T7	6		T15	1		T13	1
alert[0x1f]	4803	1			T7	6		T15	8		T43	3
alert[0x20]	6162	1			T22	1		T23	28		T30	13
alert[0x21]	6463	1			T21	5		T13	2		T49	7
alert[0x22]	4584	1			T7	55		T48	63		T70	1
alert[0x23]	9207	1			T3	1		T7	7		T43	2
alert[0x24]	9968	1			T7	6		T22	1		T23	8
alert[0x25]	5221	1			T13	51		T48	2		T23	4
alert[0x26]	4110	1			T3	2		T4	1		T7	5
alert[0x27]	9635	1			T4	1		T15	13		T86	13
alert[0x28]	5798	1			T21	1		T13	1		T49	19
alert[0x29]	9418	1			T43	1		T312	1		T86	237
alert[0x2a]	6046	1			T29	27		T312	2		T87	35
alert[0x2b]	5184	1			T72	1		T29	1089		T57	230
alert[0x2c]	7935	1			T7	17		T15	1		T21	1
alert[0x2d]	4257	1			T8	1		T57	93		T58	36
alert[0x2e]	10020	1			T23	5		T29	239		T30	438
alert[0x2f]	3502	1			T4	3		T8	2		T7	75
alert[0x30]	4893	1			T3	1		T4	1		T7	26
alert[0x31]	2376	1			T7	13		T13	3		T48	55
alert[0x32]	7927	1			T8	1		T48	304		T23	5
alert[0x33]	10874	1			T4	1		T48	16		T75	1
alert[0x34]	2309	1			T21	9		T49	74		T29	18
alert[0x35]	6519	1			T7	6		T48	16		T29	1029
alert[0x36]	7531	1			T48	89		T49	57		T30	30
alert[0x37]	5614	1			T7	34		T70	1		T29	72
alert[0x38]	7261	1			T43	1		T48	38		T49	2
alert[0x39]	4337	1			T3	1		T4	1		T7	348
alert[0x3a]	8989	1			T7	5		T43	3		T75	1
alert[0x3b]	4444	1			T8	1		T49	5		T23	2
alert[0x3c]	3742	1			T1	2		T8	1		T43	8
alert[0x3d]	7330	1			T7	1		T15	1		T48	588
alert[0x3e]	7816	1			T43	3		T13	25		T49	4
alert[0x3f]	5978	1			T1	1		T70	1		T29	3613
alert[0x40]	8298	1			T7	9		T48	16		T29	3565

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	115560	1			T1	3		T4	13		T8	2
class_i[0x1]	147284	1			T8	1		T7	22		T43	84
class_i[0x2]	56241	1			T4	2		T7	9		T15	9
class_i[0x3]	88026	1			T3	6		T8	10		T15	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

406485

1

T1

3

T7

941

T15

49

alert_ping_fail

626

1

T3

6

T4

15

T8

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	17880	1			T7	4		T13	3		T49	111
alert_integrity_fail	alert[0x1]	4550	1			T48	43		T49	10		T23	6
alert_integrity_fail	alert[0x2]	4275	1			T7	4		T21	4		T48	359
alert_integrity_fail	alert[0x3]	3528	1			T13	2		T30	14		T93	4
alert_integrity_fail	alert[0x4]	1521	1			T7	16		T21	1		T29	44
alert_integrity_fail	alert[0x5]	5197	1			T13	4		T22	4		T29	29
alert_integrity_fail	alert[0x6]	2345	1			T21	2		T29	161		T86	57
alert_integrity_fail	alert[0x7]	11316	1			T15	1		T86	47		T56	603
alert_integrity_fail	alert[0x8]	8280	1			T15	1		T49	493		T29	5
alert_integrity_fail	alert[0x9]	3758	1			T7	123		T13	28		T48	88
alert_integrity_fail	alert[0xa]	4310	1			T43	1		T86	81		T56	319
alert_integrity_fail	alert[0xb]	7689	1			T7	9		T43	14		T49	174
alert_integrity_fail	alert[0xc]	4413	1			T49	156		T93	588		T57	77
alert_integrity_fail	alert[0xd]	6962	1			T7	27		T48	5		T29	9
alert_integrity_fail	alert[0xe]	2612	1			T7	59		T21	2		T48	15
alert_integrity_fail	alert[0xf]	10520	1			T43	1		T30	2		T86	34
alert_integrity_fail	alert[0x10]	2451	1			T43	3		T13	8		T49	26
alert_integrity_fail	alert[0x11]	11628	1			T7	3		T15	1		T48	17
alert_integrity_fail	alert[0x12]	4059	1			T13	4		T48	386		T23	8
alert_integrity_fail	alert[0x13]	2714	1			T7	7		T13	2		T49	4
alert_integrity_fail	alert[0x14]	3406	1			T7	33		T49	29		T23	4
alert_integrity_fail	alert[0x15]	3080	1			T7	3		T48	69		T22	21
alert_integrity_fail	alert[0x16]	3270	1			T7	3		T15	7		T29	23
alert_integrity_fail	alert[0x17]	4114	1			T43	2		T29	7		T30	14
alert_integrity_fail	alert[0x18]	6786	1			T7	6		T21	2		T43	4
alert_integrity_fail	alert[0x19]	14039	1			T43	2		T23	5		T29	6434
alert_integrity_fail	alert[0x1a]	5329	1			T48	4		T75	3		T29	21
alert_integrity_fail	alert[0x1b]	3778	1			T15	7		T43	15		T49	7
alert_integrity_fail	alert[0x1c]	9019	1			T7	13		T21	4		T48	44
alert_integrity_fail	alert[0x1d]	10633	1			T7	12		T15	3		T43	7
alert_integrity_fail	alert[0x1e]	4799	1			T7	6		T15	1		T13	1
alert_integrity_fail	alert[0x1f]	4792	1			T7	6		T15	8		T43	3
alert_integrity_fail	alert[0x20]	6152	1			T22	1		T23	28		T30	13
alert_integrity_fail	alert[0x21]	6454	1			T21	5		T13	2		T49	7
alert_integrity_fail	alert[0x22]	4572	1			T7	55		T48	63		T198	22
alert_integrity_fail	alert[0x23]	9192	1			T7	7		T43	2		T48	31
alert_integrity_fail	alert[0x24]	9963	1			T7	6		T22	1		T23	8
alert_integrity_fail	alert[0x25]	5214	1			T13	51		T48	2		T23	4
alert_integrity_fail	alert[0x26]	4093	1			T7	5		T22	2		T29	380
alert_integrity_fail	alert[0x27]	9628	1			T15	13		T86	13		T57	2
alert_integrity_fail	alert[0x28]	5787	1			T21	1		T13	1		T49	19
alert_integrity_fail	alert[0x29]	9405	1			T43	1		T86	237		T87	1
alert_integrity_fail	alert[0x2a]	6034	1			T29	27		T87	35		T57	7
alert_integrity_fail	alert[0x2b]	5172	1			T29	1089		T57	230		T31	243
alert_integrity_fail	alert[0x2c]	7927	1			T7	17		T15	1		T21	1
alert_integrity_fail	alert[0x2d]	4249	1			T57	93		T58	36		T223	37
alert_integrity_fail	alert[0x2e]	10014	1			T23	5		T29	239		T30	438
alert_integrity_fail	alert[0x2f]	3486	1			T7	75		T43	8		T13	8
alert_integrity_fail	alert[0x30]	4882	1			T7	26		T48	75		T49	28
alert_integrity_fail	alert[0x31]	2363	1			T7	13		T13	3		T48	55
alert_integrity_fail	alert[0x32]	7918	1			T48	304		T23	5		T30	617
alert_integrity_fail	alert[0x33]	10863	1			T48	16		T75	1		T29	284
alert_integrity_fail	alert[0x34]	2301	1			T21	9		T49	74		T29	18
alert_integrity_fail	alert[0x35]	6513	1			T7	6		T48	16		T29	1029
alert_integrity_fail	alert[0x36]	7522	1			T48	89		T49	57		T30	30
alert_integrity_fail	alert[0x37]	5602	1			T7	34		T29	72		T87	2
alert_integrity_fail	alert[0x38]	7254	1			T43	1		T48	38		T49	2
alert_integrity_fail	alert[0x39]	4329	1			T7	348		T15	5		T48	3
alert_integrity_fail	alert[0x3a]	8975	1			T7	5		T43	3		T75	1
alert_integrity_fail	alert[0x3b]	4434	1			T49	5		T23	2		T93	100
alert_integrity_fail	alert[0x3c]	3737	1			T1	2		T43	8		T48	111
alert_integrity_fail	alert[0x3d]	7324	1			T7	1		T15	1		T48	588
alert_integrity_fail	alert[0x3e]	7810	1			T43	3		T13	25		T49	4
alert_integrity_fail	alert[0x3f]	5970	1			T1	1		T29	3613		T87	2
alert_integrity_fail	alert[0x40]	8293	1			T7	9		T48	16		T29	3565
alert_ping_fail	alert[0x0]	7	1			T311	1		T304	1		T313	1
alert_ping_fail	alert[0x1]	9	1			T8	1		T241	1		T314	1
alert_ping_fail	alert[0x2]	8	1			T4	1		T315	1		T241	1
alert_ping_fail	alert[0x3]	2	1			T316	1		T317	1		-	-
alert_ping_fail	alert[0x4]	2	1			T318	1		T319	1		-	-
alert_ping_fail	alert[0x5]	14	1			T8	1		T70	1		T72	1
alert_ping_fail	alert[0x6]	14	1			T78	1		T320	1		T314	1
alert_ping_fail	alert[0x7]	13	1			T4	1		T311	1		T321	1
alert_ping_fail	alert[0x8]	7	1			T312	1		T320	1		T182	2
alert_ping_fail	alert[0x9]	7	1			T322	1		T304	1		T229	1
alert_ping_fail	alert[0xa]	9	1			T4	1		T323	1		T185	1
alert_ping_fail	alert[0xb]	13	1			T3	1		T4	1		T70	1
alert_ping_fail	alert[0xc]	12	1			T311	1		T320	1		T241	2
alert_ping_fail	alert[0xd]	11	1			T4	1		T312	1		T314	1
alert_ping_fail	alert[0xe]	6	1			T8	1		T322	1		T300	1
alert_ping_fail	alert[0xf]	11	1			T70	1		T241	1		T185	1
alert_ping_fail	alert[0x10]	9	1			T4	1		T311	1		T324	1
alert_ping_fail	alert[0x11]	12	1			T70	1		T322	1		T314	1
alert_ping_fail	alert[0x12]	11	1			T70	1		T322	1		T320	1
alert_ping_fail	alert[0x13]	10	1			T314	1		T182	1		T185	1
alert_ping_fail	alert[0x14]	12	1			T72	2		T312	1		T325	1
alert_ping_fail	alert[0x15]	12	1			T4	1		T72	2		T323	2
alert_ping_fail	alert[0x16]	12	1			T322	2		T310	1		T326	1
alert_ping_fail	alert[0x17]	8	1			T327	2		T97	1		T328	1
alert_ping_fail	alert[0x18]	9	1			T8	1		T70	1		T329	1
alert_ping_fail	alert[0x19]	3	1			T300	1		T241	1		T330	1
alert_ping_fail	alert[0x1a]	7	1			T320	1		T324	1		T331	1
alert_ping_fail	alert[0x1b]	13	1			T8	1		T322	1		T241	1
alert_ping_fail	alert[0x1c]	12	1			T322	2		T332	1		T97	1
alert_ping_fail	alert[0x1d]	15	1			T8	2		T320	1		T326	1
alert_ping_fail	alert[0x1e]	9	1			T70	1		T322	1		T241	1
alert_ping_fail	alert[0x1f]	11	1			T67	1		T307	1		T322	1
alert_ping_fail	alert[0x20]	10	1			T322	1		T311	1		T320	1
alert_ping_fail	alert[0x21]	9	1			T312	1		T313	1		T185	1
alert_ping_fail	alert[0x22]	12	1			T70	1		T311	1		T333	1
alert_ping_fail	alert[0x23]	15	1			T3	1		T314	1		T334	2
alert_ping_fail	alert[0x24]	5	1			T313	1		T229	1		T335	1
alert_ping_fail	alert[0x25]	7	1			T300	1		T336	1		T337	1
alert_ping_fail	alert[0x26]	17	1			T3	2		T4	1		T70	2
alert_ping_fail	alert[0x27]	7	1			T4	1		T311	1		T338	2
alert_ping_fail	alert[0x28]	11	1			T70	1		T312	1		T306	1
alert_ping_fail	alert[0x29]	13	1			T312	1		T311	1		T320	1
alert_ping_fail	alert[0x2a]	12	1			T312	2		T311	3		T320	2
alert_ping_fail	alert[0x2b]	12	1			T72	1		T304	1		T326	1
alert_ping_fail	alert[0x2c]	8	1			T297	1		T322	1		T315	1
alert_ping_fail	alert[0x2d]	8	1			T8	1		T338	1		T182	1
alert_ping_fail	alert[0x2e]	6	1			T322	1		T300	1		T339	1
alert_ping_fail	alert[0x2f]	16	1			T4	3		T8	2		T67	1
alert_ping_fail	alert[0x30]	11	1			T3	1		T4	1		T67	1
alert_ping_fail	alert[0x31]	13	1			T70	1		T312	1		T311	1
alert_ping_fail	alert[0x32]	9	1			T8	1		T320	1		T314	1
alert_ping_fail	alert[0x33]	11	1			T4	1		T311	1		T315	1
alert_ping_fail	alert[0x34]	8	1			T322	2		T241	1		T338	1
alert_ping_fail	alert[0x35]	6	1			T314	1		T340	1		T336	1
alert_ping_fail	alert[0x36]	9	1			T324	1		T329	1		T341	1
alert_ping_fail	alert[0x37]	12	1			T70	1		T312	1		T241	1
alert_ping_fail	alert[0x38]	7	1			T300	1		T338	1		T324	1
alert_ping_fail	alert[0x39]	8	1			T3	1		T4	1		T311	1
alert_ping_fail	alert[0x3a]	14	1			T322	1		T320	1		T331	1
alert_ping_fail	alert[0x3b]	10	1			T8	1		T320	1		T185	1
alert_ping_fail	alert[0x3c]	5	1			T8	1		T329	1		T316	1
alert_ping_fail	alert[0x3d]	6	1			T314	1		T325	1		T327	1
alert_ping_fail	alert[0x3e]	6	1			T311	1		T241	1		T314	1
alert_ping_fail	alert[0x3f]	8	1			T70	1		T320	1		T315	1
alert_ping_fail	alert[0x40]	5	1			T312	1		T342	1		T318	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	115405	1			T1	3		T7	910		T15	39
alert_integrity_fail	class_i[0x1]	147118	1			T7	22		T43	84		T13	20
alert_integrity_fail	class_i[0x2]	56118	1			T7	9		T15	9		T21	31
alert_integrity_fail	class_i[0x3]	87844	1			T15	1		T13	68		T49	1093
alert_ping_fail	class_i[0x0]	155	1			T4	13		T8	2		T72	6
alert_ping_fail	class_i[0x1]	166	1			T8	1		T297	1		T312	13
alert_ping_fail	class_i[0x2]	123	1			T4	2		T67	3		T70	13
alert_ping_fail	class_i[0x3]	182	1			T3	6		T8	10		T70	1