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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.66 100.00 100.00 100.00 99.38 99.60


Total test records in report: 833
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T771 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4004137040 Jul 01 04:53:36 PM PDT 24 Jul 01 04:53:39 PM PDT 24 8738573 ps
T772 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1351190460 Jul 01 04:53:37 PM PDT 24 Jul 01 04:53:41 PM PDT 24 16024304 ps
T773 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.205036518 Jul 01 04:53:45 PM PDT 24 Jul 01 04:53:47 PM PDT 24 10794856 ps
T774 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.57276647 Jul 01 04:53:47 PM PDT 24 Jul 01 04:53:50 PM PDT 24 14641838 ps
T775 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3930912166 Jul 01 04:53:07 PM PDT 24 Jul 01 04:54:20 PM PDT 24 571878530 ps
T776 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.751748763 Jul 01 04:53:13 PM PDT 24 Jul 01 04:53:23 PM PDT 24 104335635 ps
T777 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3326707595 Jul 01 04:53:05 PM PDT 24 Jul 01 04:53:12 PM PDT 24 66979856 ps
T134 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1522135417 Jul 01 04:53:40 PM PDT 24 Jul 01 04:59:09 PM PDT 24 4348107198 ps
T168 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3270658660 Jul 01 04:53:25 PM PDT 24 Jul 01 04:53:32 PM PDT 24 57325575 ps
T778 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.613137030 Jul 01 04:53:15 PM PDT 24 Jul 01 04:53:27 PM PDT 24 493643490 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2715309628 Jul 01 04:53:23 PM PDT 24 Jul 01 04:53:29 PM PDT 24 8162587 ps
T780 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3088351324 Jul 01 04:53:24 PM PDT 24 Jul 01 04:54:02 PM PDT 24 1991216446 ps
T781 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2112964366 Jul 01 04:53:05 PM PDT 24 Jul 01 04:55:01 PM PDT 24 3146082780 ps
T782 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2047521055 Jul 01 04:53:49 PM PDT 24 Jul 01 04:53:51 PM PDT 24 6398312 ps
T783 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3008506162 Jul 01 04:52:59 PM PDT 24 Jul 01 04:53:02 PM PDT 24 17512477 ps
T784 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2493431102 Jul 01 04:53:12 PM PDT 24 Jul 01 04:53:51 PM PDT 24 2377540388 ps
T152 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4065159433 Jul 01 04:53:05 PM PDT 24 Jul 01 05:02:27 PM PDT 24 4591521402 ps
T785 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.250787228 Jul 01 04:53:23 PM PDT 24 Jul 01 04:53:39 PM PDT 24 293221548 ps
T786 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.615598829 Jul 01 04:53:25 PM PDT 24 Jul 01 04:53:45 PM PDT 24 172344484 ps
T787 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.26615173 Jul 01 04:53:41 PM PDT 24 Jul 01 04:53:44 PM PDT 24 13324275 ps
T788 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3129778450 Jul 01 04:53:23 PM PDT 24 Jul 01 04:53:48 PM PDT 24 622244987 ps
T141 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.261656362 Jul 01 04:53:40 PM PDT 24 Jul 01 05:09:42 PM PDT 24 54976106342 ps
T151 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2154634232 Jul 01 04:53:07 PM PDT 24 Jul 01 05:02:43 PM PDT 24 14631877363 ps
T789 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1202051271 Jul 01 04:53:46 PM PDT 24 Jul 01 04:53:49 PM PDT 24 18375054 ps
T790 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2931679990 Jul 01 04:53:07 PM PDT 24 Jul 01 04:53:14 PM PDT 24 54090235 ps
T172 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3269244096 Jul 01 04:53:03 PM PDT 24 Jul 01 04:53:22 PM PDT 24 612334447 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.431637044 Jul 01 04:52:58 PM PDT 24 Jul 01 04:53:14 PM PDT 24 357716002 ps
T792 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2632226475 Jul 01 04:53:24 PM PDT 24 Jul 01 04:53:36 PM PDT 24 92314918 ps
T150 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2099024258 Jul 01 04:53:25 PM PDT 24 Jul 01 04:56:55 PM PDT 24 10820946038 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2407188880 Jul 01 04:53:05 PM PDT 24 Jul 01 04:53:26 PM PDT 24 263811919 ps
T794 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3216453659 Jul 01 04:53:02 PM PDT 24 Jul 01 04:53:10 PM PDT 24 45503818 ps
T795 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2017875914 Jul 01 04:53:07 PM PDT 24 Jul 01 04:53:11 PM PDT 24 11337123 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1106060553 Jul 01 04:53:06 PM PDT 24 Jul 01 04:53:14 PM PDT 24 400493619 ps
T797 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1298221695 Jul 01 04:53:05 PM PDT 24 Jul 01 04:53:20 PM PDT 24 290983870 ps
T798 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1319817087 Jul 01 04:53:06 PM PDT 24 Jul 01 04:53:30 PM PDT 24 170839772 ps
T799 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.84333275 Jul 01 04:53:50 PM PDT 24 Jul 01 04:53:54 PM PDT 24 24167836 ps
T136 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1224835624 Jul 01 04:53:14 PM PDT 24 Jul 01 05:08:43 PM PDT 24 60512452744 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3341634293 Jul 01 04:52:55 PM PDT 24 Jul 01 05:00:22 PM PDT 24 15091519949 ps
T153 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1040997734 Jul 01 04:53:37 PM PDT 24 Jul 01 05:04:18 PM PDT 24 30186388218 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1048016877 Jul 01 04:53:25 PM PDT 24 Jul 01 04:53:47 PM PDT 24 454961458 ps
T149 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2612263451 Jul 01 04:52:59 PM PDT 24 Jul 01 05:00:02 PM PDT 24 12519639332 ps
T146 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.554910531 Jul 01 04:53:13 PM PDT 24 Jul 01 04:55:55 PM PDT 24 8649892354 ps
T802 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4120118797 Jul 01 04:53:13 PM PDT 24 Jul 01 04:53:19 PM PDT 24 21960613 ps
T157 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2602177417 Jul 01 04:53:36 PM PDT 24 Jul 01 04:56:26 PM PDT 24 4776146722 ps
T803 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.851749314 Jul 01 04:53:38 PM PDT 24 Jul 01 04:53:42 PM PDT 24 62786015 ps
T148 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.701764710 Jul 01 04:53:26 PM PDT 24 Jul 01 05:00:01 PM PDT 24 10690093514 ps
T804 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3740482379 Jul 01 04:53:11 PM PDT 24 Jul 01 04:53:38 PM PDT 24 1171910487 ps
T805 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3783788534 Jul 01 04:53:13 PM PDT 24 Jul 01 04:53:24 PM PDT 24 216474381 ps
T155 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1664825839 Jul 01 04:53:10 PM PDT 24 Jul 01 04:56:33 PM PDT 24 9986461772 ps
T806 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3236956811 Jul 01 04:53:36 PM PDT 24 Jul 01 04:53:42 PM PDT 24 91590924 ps
T807 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2366089124 Jul 01 04:53:37 PM PDT 24 Jul 01 04:54:03 PM PDT 24 640523152 ps
T156 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3228754513 Jul 01 04:53:10 PM PDT 24 Jul 01 04:55:36 PM PDT 24 7688843805 ps
T808 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1318335524 Jul 01 04:53:46 PM PDT 24 Jul 01 04:53:49 PM PDT 24 18176489 ps
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2845011856 Jul 01 04:53:25 PM PDT 24 Jul 01 04:58:34 PM PDT 24 3909086056 ps
T809 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1946255934 Jul 01 04:53:21 PM PDT 24 Jul 01 04:53:38 PM PDT 24 1077608487 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1652580233 Jul 01 04:53:03 PM PDT 24 Jul 01 04:53:12 PM PDT 24 77096854 ps
T811 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2546461054 Jul 01 04:53:36 PM PDT 24 Jul 01 04:53:45 PM PDT 24 356144886 ps
T812 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.305849884 Jul 01 04:53:35 PM PDT 24 Jul 01 04:53:38 PM PDT 24 11379474 ps
T170 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1299704471 Jul 01 04:53:24 PM PDT 24 Jul 01 04:53:49 PM PDT 24 151263506 ps
T813 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3809693470 Jul 01 04:53:25 PM PDT 24 Jul 01 04:58:22 PM PDT 24 2359053488 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1942163322 Jul 01 04:53:23 PM PDT 24 Jul 01 04:53:30 PM PDT 24 86484408 ps
T369 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1344458698 Jul 01 04:53:07 PM PDT 24 Jul 01 05:12:48 PM PDT 24 16554090476 ps
T815 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.844305060 Jul 01 04:53:22 PM PDT 24 Jul 01 04:53:32 PM PDT 24 575815683 ps
T816 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4163760641 Jul 01 04:53:09 PM PDT 24 Jul 01 04:56:29 PM PDT 24 8685421008 ps
T817 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4110295498 Jul 01 04:53:13 PM PDT 24 Jul 01 04:53:20 PM PDT 24 34703595 ps
T818 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4005822406 Jul 01 04:53:45 PM PDT 24 Jul 01 04:53:47 PM PDT 24 8879177 ps
T819 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3663074492 Jul 01 04:53:11 PM PDT 24 Jul 01 04:53:18 PM PDT 24 378855882 ps
T820 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.729366275 Jul 01 04:53:45 PM PDT 24 Jul 01 04:53:53 PM PDT 24 107093680 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1761228157 Jul 01 04:53:23 PM PDT 24 Jul 01 04:54:05 PM PDT 24 497692738 ps
T822 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1751113205 Jul 01 04:53:39 PM PDT 24 Jul 01 04:54:04 PM PDT 24 1304700270 ps
T823 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2891450679 Jul 01 04:53:23 PM PDT 24 Jul 01 04:53:29 PM PDT 24 11191648 ps
T824 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1048213585 Jul 01 04:53:06 PM PDT 24 Jul 01 04:53:10 PM PDT 24 14939270 ps
T825 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.222196776 Jul 01 04:53:25 PM PDT 24 Jul 01 04:53:41 PM PDT 24 140072569 ps
T826 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1102042552 Jul 01 04:53:12 PM PDT 24 Jul 01 04:53:16 PM PDT 24 6833215 ps
T178 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1406656894 Jul 01 04:53:07 PM PDT 24 Jul 01 04:53:47 PM PDT 24 754219517 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1518743850 Jul 01 04:53:25 PM PDT 24 Jul 01 04:56:11 PM PDT 24 1213639077 ps
T828 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3602771426 Jul 01 04:53:13 PM PDT 24 Jul 01 04:53:17 PM PDT 24 15112031 ps
T829 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3778995160 Jul 01 04:53:23 PM PDT 24 Jul 01 04:53:29 PM PDT 24 7349479 ps
T830 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4016681641 Jul 01 04:53:07 PM PDT 24 Jul 01 04:53:24 PM PDT 24 408760200 ps
T831 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.114541931 Jul 01 04:53:08 PM PDT 24 Jul 01 04:53:12 PM PDT 24 7664555 ps
T832 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2963832641 Jul 01 04:53:39 PM PDT 24 Jul 01 04:53:50 PM PDT 24 115856361 ps
T158 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1508647499 Jul 01 04:53:39 PM PDT 24 Jul 01 04:57:00 PM PDT 24 13432934432 ps
T833 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3249184103 Jul 01 04:53:11 PM PDT 24 Jul 01 04:53:25 PM PDT 24 163715551 ps

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3913317122
Short name T7
Test name
Test status
Simulation time 29540108969 ps
CPU time 2032.88 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:53:30 PM PDT 24
Peak memory 289776 kb
Host smart-be9f246c-162a-4127-bd4c-21e4f397303d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913317122 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3913317122
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4108292311
Short name T32
Test name
Test status
Simulation time 1287706029 ps
CPU time 20.61 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 05:18:14 PM PDT 24
Peak memory 271812 kb
Host smart-f7edf8ae-e1e3-4621-8042-54c2c700e091
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4108292311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4108292311
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3175025977
Short name T29
Test name
Test status
Simulation time 167946355848 ps
CPU time 1801.03 seconds
Started Jul 01 05:17:55 PM PDT 24
Finished Jul 01 05:47:59 PM PDT 24
Peak memory 288704 kb
Host smart-c7adf071-2014-4bbf-8433-05e5c6d45d7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175025977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3175025977
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2952987573
Short name T200
Test name
Test status
Simulation time 127175196 ps
CPU time 8.85 seconds
Started Jul 01 04:53:16 PM PDT 24
Finished Jul 01 04:53:27 PM PDT 24
Peak memory 237500 kb
Host smart-bd09a3fe-2897-47a3-81f4-a77b34f7896f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2952987573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2952987573
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1281562913
Short name T6
Test name
Test status
Simulation time 992883918 ps
CPU time 14.71 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:18:36 PM PDT 24
Peak memory 249300 kb
Host smart-d90311ef-0400-4b2e-b302-969fe6c9702d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1281562913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1281562913
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.984123810
Short name T22
Test name
Test status
Simulation time 15408051918 ps
CPU time 1304.23 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:40:00 PM PDT 24
Peak memory 289732 kb
Host smart-d1c89eeb-8db5-4e88-a9cd-c0b88089a5ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984123810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.984123810
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.648668389
Short name T126
Test name
Test status
Simulation time 56864218143 ps
CPU time 1017.22 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 05:10:24 PM PDT 24
Peak memory 273656 kb
Host smart-d067ddd9-f0cb-4366-8740-bc77d487ac38
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648668389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.648668389
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.695787256
Short name T98
Test name
Test status
Simulation time 15134735379 ps
CPU time 983.47 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 05:35:27 PM PDT 24
Peak memory 274180 kb
Host smart-a5def53e-3451-4b42-9fe3-acfeacce84aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695787256 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.695787256
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.300370788
Short name T102
Test name
Test status
Simulation time 18189203389 ps
CPU time 793.48 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:32:24 PM PDT 24
Peak memory 274004 kb
Host smart-fa516dec-ab06-4ead-b1ab-0406f4b08baf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300370788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.300370788
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2313954247
Short name T127
Test name
Test status
Simulation time 5851170583 ps
CPU time 378.05 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:59:46 PM PDT 24
Peak memory 265360 kb
Host smart-e9bafcb8-30c9-4cbb-8721-5d251d51e9f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2313954247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2313954247
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1263201073
Short name T72
Test name
Test status
Simulation time 125166482986 ps
CPU time 3144.72 seconds
Started Jul 01 05:20:02 PM PDT 24
Finished Jul 01 06:12:32 PM PDT 24
Peak memory 286636 kb
Host smart-dcfce48b-356a-4a1a-8510-9452690f2030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263201073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1263201073
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4279173906
Short name T114
Test name
Test status
Simulation time 81896432451 ps
CPU time 1477.03 seconds
Started Jul 01 05:19:40 PM PDT 24
Finished Jul 01 05:44:21 PM PDT 24
Peak memory 290332 kb
Host smart-952c33e3-b01d-41af-87a7-e99bea9f640e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279173906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4279173906
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4114041853
Short name T159
Test name
Test status
Simulation time 1759460161 ps
CPU time 32.8 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:54:01 PM PDT 24
Peak memory 240400 kb
Host smart-db96a20b-5951-4fea-a68e-155f2f69791d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4114041853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4114041853
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4270217369
Short name T93
Test name
Test status
Simulation time 44465016742 ps
CPU time 1229.31 seconds
Started Jul 01 05:18:52 PM PDT 24
Finished Jul 01 05:39:24 PM PDT 24
Peak memory 290280 kb
Host smart-68758457-f9de-4e23-900c-458a1241a1db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270217369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4270217369
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1821342193
Short name T135
Test name
Test status
Simulation time 4680335228 ps
CPU time 625.17 seconds
Started Jul 01 04:53:35 PM PDT 24
Finished Jul 01 05:04:01 PM PDT 24
Peak memory 272588 kb
Host smart-519cd077-2075-4960-813d-42544f51dd63
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821342193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1821342193
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.771720277
Short name T14
Test name
Test status
Simulation time 149926956431 ps
CPU time 2306.71 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:57:50 PM PDT 24
Peak memory 290180 kb
Host smart-26b89949-bfbe-4869-b871-2851a1d07ed8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771720277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.771720277
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.4237138131
Short name T97
Test name
Test status
Simulation time 7674023024 ps
CPU time 316.19 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:23:21 PM PDT 24
Peak memory 249356 kb
Host smart-46a8733d-5cd3-4399-a570-bffd417ce777
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237138131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4237138131
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2193104636
Short name T21
Test name
Test status
Simulation time 111150751077 ps
CPU time 1477.48 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:43:49 PM PDT 24
Peak memory 282360 kb
Host smart-e8484e8d-f839-49b2-a335-f9393011862c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193104636 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2193104636
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.258479616
Short name T124
Test name
Test status
Simulation time 6850566125 ps
CPU time 203.6 seconds
Started Jul 01 04:53:06 PM PDT 24
Finished Jul 01 04:56:32 PM PDT 24
Peak memory 273612 kb
Host smart-4fcd6dc1-5561-45b4-9a8c-d76c3a1db8e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=258479616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.258479616
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3415423236
Short name T4
Test name
Test status
Simulation time 45825538486 ps
CPU time 434.71 seconds
Started Jul 01 05:19:54 PM PDT 24
Finished Jul 01 05:27:14 PM PDT 24
Peak memory 248340 kb
Host smart-5d2a529e-a35c-4d44-99eb-ce422b999785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415423236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3415423236
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1914450072
Short name T163
Test name
Test status
Simulation time 14992515 ps
CPU time 1.57 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:28 PM PDT 24
Peak memory 237584 kb
Host smart-4c61c38c-ffee-477f-b1f1-5b8fe4cf7236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1914450072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1914450072
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2172902806
Short name T306
Test name
Test status
Simulation time 203395264994 ps
CPU time 2894.3 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 06:08:08 PM PDT 24
Peak memory 290192 kb
Host smart-261cfa3b-c871-414b-96ec-f6496e0239ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172902806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2172902806
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1224835624
Short name T136
Test name
Test status
Simulation time 60512452744 ps
CPU time 926.94 seconds
Started Jul 01 04:53:14 PM PDT 24
Finished Jul 01 05:08:43 PM PDT 24
Peak memory 272780 kb
Host smart-639be7c1-8fb1-41ed-aa3b-b2ff802c5532
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224835624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1224835624
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1003939865
Short name T31
Test name
Test status
Simulation time 207258258043 ps
CPU time 3353.66 seconds
Started Jul 01 05:19:54 PM PDT 24
Finished Jul 01 06:15:53 PM PDT 24
Peak memory 306560 kb
Host smart-67e4956d-0cf2-4602-ab1f-e01548a100cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003939865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1003939865
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2523397650
Short name T182
Test name
Test status
Simulation time 546769540243 ps
CPU time 2987.29 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 06:08:39 PM PDT 24
Peak memory 289736 kb
Host smart-49317d39-f1a1-46bb-a79c-8290c1f8fab7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523397650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2523397650
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1664825839
Short name T155
Test name
Test status
Simulation time 9986461772 ps
CPU time 200.82 seconds
Started Jul 01 04:53:10 PM PDT 24
Finished Jul 01 04:56:33 PM PDT 24
Peak memory 265448 kb
Host smart-f686b464-c582-40df-9032-55999b73ab39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1664825839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1664825839
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3524807381
Short name T320
Test name
Test status
Simulation time 14662774153 ps
CPU time 430.98 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:25:36 PM PDT 24
Peak memory 248328 kb
Host smart-c2acdaea-6bdd-454e-ab14-e560314b3641
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524807381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3524807381
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3505987488
Short name T139
Test name
Test status
Simulation time 6569601295 ps
CPU time 187.45 seconds
Started Jul 01 04:53:03 PM PDT 24
Finished Jul 01 04:56:12 PM PDT 24
Peak memory 271676 kb
Host smart-35319e31-7607-4985-b66e-169b9becb745
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3505987488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3505987488
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3565229047
Short name T341
Test name
Test status
Simulation time 345772578399 ps
CPU time 2506.51 seconds
Started Jul 01 05:19:12 PM PDT 24
Finished Jul 01 06:01:01 PM PDT 24
Peak memory 289312 kb
Host smart-06bf1543-496c-4f05-8321-ecb897480937
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565229047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3565229047
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2884841681
Short name T308
Test name
Test status
Simulation time 93760517511 ps
CPU time 2634.43 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 06:02:03 PM PDT 24
Peak memory 282180 kb
Host smart-797499fe-77bd-42a9-9fd9-7490e887e020
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884841681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2884841681
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1522135417
Short name T134
Test name
Test status
Simulation time 4348107198 ps
CPU time 328.3 seconds
Started Jul 01 04:53:40 PM PDT 24
Finished Jul 01 04:59:09 PM PDT 24
Peak memory 265488 kb
Host smart-6b4a2aa8-c045-466e-ae2b-3357f92550d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1522135417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1522135417
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.733257343
Short name T109
Test name
Test status
Simulation time 56138944446 ps
CPU time 2916.89 seconds
Started Jul 01 05:19:11 PM PDT 24
Finished Jul 01 06:07:51 PM PDT 24
Peak memory 299332 kb
Host smart-d5900a94-7a85-4e78-9270-95cf0dffc1bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733257343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.733257343
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3756525901
Short name T319
Test name
Test status
Simulation time 46201315859 ps
CPU time 500.89 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:26:32 PM PDT 24
Peak memory 256240 kb
Host smart-bfddfd2a-e31b-4d45-ac4c-f20b36588066
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756525901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3756525901
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1923761863
Short name T86
Test name
Test status
Simulation time 52192741386 ps
CPU time 3199.65 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 06:11:45 PM PDT 24
Peak memory 306608 kb
Host smart-d97f390e-2248-48a6-8512-c03a21d5c2a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923761863 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1923761863
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.342910178
Short name T123
Test name
Test status
Simulation time 12544525607 ps
CPU time 985.64 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 05:09:52 PM PDT 24
Peak memory 273428 kb
Host smart-5486d6ec-0472-45ea-bb40-7b4ccd11feec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342910178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.342910178
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.4043647797
Short name T64
Test name
Test status
Simulation time 34585653636 ps
CPU time 2021.98 seconds
Started Jul 01 05:19:46 PM PDT 24
Finished Jul 01 05:53:33 PM PDT 24
Peak memory 290444 kb
Host smart-df6659e9-317e-4153-94f7-9901ebd6599c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043647797 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.4043647797
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4137230006
Short name T318
Test name
Test status
Simulation time 23691474405 ps
CPU time 521.37 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:27:22 PM PDT 24
Peak memory 249440 kb
Host smart-0754554e-97df-429a-b67f-834ea57a29a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137230006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4137230006
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.278474481
Short name T241
Test name
Test status
Simulation time 10292671076 ps
CPU time 409.59 seconds
Started Jul 01 05:19:04 PM PDT 24
Finished Jul 01 05:25:56 PM PDT 24
Peak memory 249384 kb
Host smart-c982c210-7f60-4bd8-b59e-821fba1f03bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278474481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.278474481
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1644320192
Short name T563
Test name
Test status
Simulation time 34959854157 ps
CPU time 2180.85 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:56:06 PM PDT 24
Peak memory 289596 kb
Host smart-4ac6c380-e5f9-4f29-ade3-dee85a77d920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644320192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1644320192
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.534591917
Short name T160
Test name
Test status
Simulation time 38050297 ps
CPU time 2.41 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:15 PM PDT 24
Peak memory 237552 kb
Host smart-243af8fd-ba4f-44a5-9801-b5881f2d2c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=534591917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.534591917
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2845011856
Short name T147
Test name
Test status
Simulation time 3909086056 ps
CPU time 304.38 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:58:34 PM PDT 24
Peak memory 265440 kb
Host smart-067acee5-af56-4563-85ed-d4c3c6f41a12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2845011856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2845011856
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.907627436
Short name T367
Test name
Test status
Simulation time 8153574 ps
CPU time 1.46 seconds
Started Jul 01 04:53:51 PM PDT 24
Finished Jul 01 04:53:55 PM PDT 24
Peak memory 236628 kb
Host smart-328bc6f8-3490-4716-83ba-8022f7d3b748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=907627436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.907627436
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.257555753
Short name T96
Test name
Test status
Simulation time 208382242397 ps
CPU time 3187.5 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 06:11:01 PM PDT 24
Peak memory 290152 kb
Host smart-95661333-915f-40d6-bbc1-4f28f067c339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257555753 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.257555753
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2199479938
Short name T88
Test name
Test status
Simulation time 353343922492 ps
CPU time 1686.46 seconds
Started Jul 01 05:18:53 PM PDT 24
Finished Jul 01 05:47:02 PM PDT 24
Peak memory 270948 kb
Host smart-4864444b-97bc-4c1f-8ace-f2528064f0c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199479938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2199479938
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4251566782
Short name T145
Test name
Test status
Simulation time 29640291224 ps
CPU time 530.93 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 05:02:04 PM PDT 24
Peak memory 269428 kb
Host smart-88d88949-a085-47bb-9816-2f68827c8af4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251566782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.4251566782
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.4222093176
Short name T87
Test name
Test status
Simulation time 21599903845 ps
CPU time 1548.71 seconds
Started Jul 01 05:19:21 PM PDT 24
Finished Jul 01 05:45:14 PM PDT 24
Peak memory 282364 kb
Host smart-1676fba6-f993-4395-a5e2-bdf9a79aca2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222093176 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.4222093176
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3811992915
Short name T691
Test name
Test status
Simulation time 40068863100 ps
CPU time 401.96 seconds
Started Jul 01 05:18:14 PM PDT 24
Finished Jul 01 05:25:00 PM PDT 24
Peak memory 249300 kb
Host smart-fbb2bfb1-2ecc-4b5e-9443-447e70fb1bac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811992915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3811992915
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1212070682
Short name T293
Test name
Test status
Simulation time 29893233899 ps
CPU time 1971.79 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:51:37 PM PDT 24
Peak memory 290340 kb
Host smart-c924d2ca-8a39-41d5-8439-7803a074c0fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212070682 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1212070682
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3012932851
Short name T281
Test name
Test status
Simulation time 245553779939 ps
CPU time 3769.93 seconds
Started Jul 01 05:19:25 PM PDT 24
Finished Jul 01 06:22:20 PM PDT 24
Peak memory 301028 kb
Host smart-9c19627e-df47-4bf5-b7e8-4b5ea50a9092
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012932851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3012932851
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2965797918
Short name T269
Test name
Test status
Simulation time 382611275159 ps
CPU time 7160.9 seconds
Started Jul 01 05:20:02 PM PDT 24
Finished Jul 01 07:19:28 PM PDT 24
Peak memory 334984 kb
Host smart-df4ed8d4-221e-459f-878b-9da2eecae563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965797918 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2965797918
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1348387422
Short name T324
Test name
Test status
Simulation time 54546272866 ps
CPU time 584.02 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:27:55 PM PDT 24
Peak memory 255888 kb
Host smart-4556a5c0-20fe-4981-8284-6a2c9a0c9b44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348387422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1348387422
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2054287712
Short name T263
Test name
Test status
Simulation time 334227030643 ps
CPU time 5761.13 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 06:54:17 PM PDT 24
Peak memory 322960 kb
Host smart-18905b1b-a52b-400e-bc08-d9e6d804d39e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054287712 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2054287712
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.79771751
Short name T218
Test name
Test status
Simulation time 31722433 ps
CPU time 3.08 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 05:17:57 PM PDT 24
Peak memory 249652 kb
Host smart-d3ae8216-f254-4f0e-b54d-7209b9c67043
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=79771751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.79771751
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3532911944
Short name T216
Test name
Test status
Simulation time 32008705 ps
CPU time 3.35 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:17:58 PM PDT 24
Peak memory 249632 kb
Host smart-a78e73f3-d8a9-4cc4-b6ce-fdc6bf9d5b35
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3532911944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3532911944
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.133402271
Short name T220
Test name
Test status
Simulation time 171097099 ps
CPU time 2.23 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:18:23 PM PDT 24
Peak memory 249524 kb
Host smart-8fc5e5e2-6de3-416a-b4b7-80c25c3ae272
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=133402271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.133402271
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1606113525
Short name T204
Test name
Test status
Simulation time 63248045 ps
CPU time 2.68 seconds
Started Jul 01 05:18:20 PM PDT 24
Finished Jul 01 05:18:27 PM PDT 24
Peak memory 249552 kb
Host smart-eaa5b045-8a1c-4e01-b86f-9b6f1d53d0f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1606113525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1606113525
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.643219653
Short name T133
Test name
Test status
Simulation time 3170727682 ps
CPU time 99.65 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:54:49 PM PDT 24
Peak memory 265444 kb
Host smart-ad88986e-0843-4a5a-8afa-b360fbe0a5fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=643219653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.643219653
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.584757754
Short name T296
Test name
Test status
Simulation time 94837460044 ps
CPU time 1257.55 seconds
Started Jul 01 05:18:20 PM PDT 24
Finished Jul 01 05:39:21 PM PDT 24
Peak memory 273972 kb
Host smart-ff45f9ab-23df-4566-aca6-8962294284b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584757754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.584757754
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2945333673
Short name T57
Test name
Test status
Simulation time 76966507979 ps
CPU time 2245.25 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:56:06 PM PDT 24
Peak memory 284736 kb
Host smart-9fddde24-c8ac-4372-93ce-9feba77ad9ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945333673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2945333673
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3465848078
Short name T82
Test name
Test status
Simulation time 750053749 ps
CPU time 44.91 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:20:30 PM PDT 24
Peak memory 249344 kb
Host smart-203ff1c0-7c6e-40a7-ae41-1ceaf178a41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34658
48078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3465848078
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.4210826213
Short name T99
Test name
Test status
Simulation time 63467288628 ps
CPU time 6481.61 seconds
Started Jul 01 05:19:47 PM PDT 24
Finished Jul 01 07:07:54 PM PDT 24
Peak memory 349712 kb
Host smart-6856d6df-e7e6-45aa-a1a8-13981a777328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210826213 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.4210826213
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.261656362
Short name T141
Test name
Test status
Simulation time 54976106342 ps
CPU time 960.47 seconds
Started Jul 01 04:53:40 PM PDT 24
Finished Jul 01 05:09:42 PM PDT 24
Peak memory 265352 kb
Host smart-141c1269-32cf-4a09-93e6-c7135ffcb886
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261656362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.261656362
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2000173744
Short name T128
Test name
Test status
Simulation time 21367684753 ps
CPU time 283.98 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:57:58 PM PDT 24
Peak memory 269228 kb
Host smart-5f7d5777-e8c5-4f2c-b876-cd50f55ba5ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000173744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2000173744
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.135995586
Short name T717
Test name
Test status
Simulation time 11372572 ps
CPU time 1.66 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:53:30 PM PDT 24
Peak memory 237596 kb
Host smart-0aaceaaa-6d50-4354-8e47-76c29774235a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=135995586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.135995586
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2649326648
Short name T701
Test name
Test status
Simulation time 2108894355 ps
CPU time 38.48 seconds
Started Jul 01 05:17:43 PM PDT 24
Finished Jul 01 05:18:28 PM PDT 24
Peak memory 257420 kb
Host smart-325bb56d-45fb-4b66-9112-a31ce018e397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26493
26648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2649326648
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.966946469
Short name T329
Test name
Test status
Simulation time 17558037825 ps
CPU time 168.65 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:20:43 PM PDT 24
Peak memory 249420 kb
Host smart-e92c27ea-3224-4620-8bec-e9eee4e228fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966946469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.966946469
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3578155996
Short name T285
Test name
Test status
Simulation time 5067800041 ps
CPU time 73.3 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:19:37 PM PDT 24
Peak memory 248596 kb
Host smart-35d709ca-54bb-4928-b220-a167e5f924b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35781
55996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3578155996
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.493488256
Short name T110
Test name
Test status
Simulation time 102319578710 ps
CPU time 1720.22 seconds
Started Jul 01 05:18:22 PM PDT 24
Finished Jul 01 05:47:06 PM PDT 24
Peak memory 285560 kb
Host smart-5cabe5e5-82fd-419d-9845-b3b93bbc9375
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493488256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.493488256
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2978046837
Short name T278
Test name
Test status
Simulation time 281563573 ps
CPU time 21.73 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:19:06 PM PDT 24
Peak memory 255980 kb
Host smart-595605f0-e2f4-4d92-be84-41f71e58c7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
46837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2978046837
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1152249081
Short name T292
Test name
Test status
Simulation time 14777574471 ps
CPU time 1238.78 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:39:28 PM PDT 24
Peak memory 286356 kb
Host smart-7ec7cf59-ca42-47bd-89b8-104d8ca56a37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152249081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1152249081
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.488374745
Short name T346
Test name
Test status
Simulation time 128329009285 ps
CPU time 1600.8 seconds
Started Jul 01 05:18:55 PM PDT 24
Finished Jul 01 05:45:38 PM PDT 24
Peak memory 273144 kb
Host smart-ed30c1a1-9c5f-4c98-a693-e6977fcb4ad1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488374745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.488374745
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4037637594
Short name T261
Test name
Test status
Simulation time 489144113 ps
CPU time 35.8 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:49 PM PDT 24
Peak memory 248912 kb
Host smart-434afd5d-3a07-43c5-a1ae-76419d55aac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40376
37594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4037637594
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3120586853
Short name T270
Test name
Test status
Simulation time 107639226233 ps
CPU time 3109.94 seconds
Started Jul 01 05:19:16 PM PDT 24
Finished Jul 01 06:11:09 PM PDT 24
Peak memory 301168 kb
Host smart-e80c2483-e4c7-4db5-ba7b-605d4c534b72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120586853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3120586853
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3799471732
Short name T274
Test name
Test status
Simulation time 434434882 ps
CPU time 8.28 seconds
Started Jul 01 05:19:24 PM PDT 24
Finished Jul 01 05:19:35 PM PDT 24
Peak memory 248764 kb
Host smart-e1c266ca-3842-462d-89c7-5cda26d3c5b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37994
71732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3799471732
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3201023329
Short name T359
Test name
Test status
Simulation time 35690704640 ps
CPU time 1328.41 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:41:44 PM PDT 24
Peak memory 282620 kb
Host smart-b72a9d2d-f45b-4ead-a8c6-3d241ce7ec44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201023329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3201023329
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.379339777
Short name T317
Test name
Test status
Simulation time 11629575501 ps
CPU time 485.55 seconds
Started Jul 01 05:19:42 PM PDT 24
Finished Jul 01 05:27:53 PM PDT 24
Peak memory 249476 kb
Host smart-dbbbb1d3-8b38-4378-bfd9-885fee9fd76c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379339777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.379339777
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3867360770
Short name T353
Test name
Test status
Simulation time 86974139764 ps
CPU time 2208.19 seconds
Started Jul 01 05:19:56 PM PDT 24
Finished Jul 01 05:56:48 PM PDT 24
Peak memory 288660 kb
Host smart-d3bbb368-c9d9-49cb-b390-23c1c73f4e57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867360770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3867360770
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.871193913
Short name T167
Test name
Test status
Simulation time 395466132 ps
CPU time 3.66 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:42 PM PDT 24
Peak memory 237588 kb
Host smart-95b23ca5-2d9a-4875-a471-b71cc4f13e54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=871193913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.871193913
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.348388317
Short name T165
Test name
Test status
Simulation time 16961514522 ps
CPU time 77.89 seconds
Started Jul 01 04:53:35 PM PDT 24
Finished Jul 01 04:54:54 PM PDT 24
Peak memory 247980 kb
Host smart-7c2ff1c4-2898-47ea-86a8-894bc499bad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=348388317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.348388317
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1104613447
Short name T132
Test name
Test status
Simulation time 8696187315 ps
CPU time 667.92 seconds
Started Jul 01 04:53:40 PM PDT 24
Finished Jul 01 05:04:49 PM PDT 24
Peak memory 265628 kb
Host smart-1a29a465-8c7b-483e-a04a-40ec578e1f5f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104613447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1104613447
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2002277663
Short name T161
Test name
Test status
Simulation time 2495799787 ps
CPU time 87.16 seconds
Started Jul 01 04:53:14 PM PDT 24
Finished Jul 01 04:54:43 PM PDT 24
Peak memory 237808 kb
Host smart-6889eb07-5deb-4043-a8b2-009c6d5bef24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2002277663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2002277663
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2113890610
Short name T171
Test name
Test status
Simulation time 1248943702 ps
CPU time 46.58 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:54:17 PM PDT 24
Peak memory 240604 kb
Host smart-429bd6d2-8118-4206-be00-c0bcdaf3836d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2113890610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2113890610
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2575648959
Short name T173
Test name
Test status
Simulation time 47244414 ps
CPU time 3.34 seconds
Started Jul 01 04:53:22 PM PDT 24
Finished Jul 01 04:53:27 PM PDT 24
Peak memory 237576 kb
Host smart-d0dbdf80-3543-4e95-ac3f-20c71ae506af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2575648959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2575648959
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3684796452
Short name T177
Test name
Test status
Simulation time 557179101 ps
CPU time 23.2 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:54:01 PM PDT 24
Peak memory 240532 kb
Host smart-a8251d37-e8ba-4ab3-8352-71e698f52b90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3684796452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3684796452
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4281084705
Short name T169
Test name
Test status
Simulation time 57228891 ps
CPU time 2.16 seconds
Started Jul 01 04:53:38 PM PDT 24
Finished Jul 01 04:53:42 PM PDT 24
Peak memory 237576 kb
Host smart-0539bc61-0829-43a1-8922-72bbbcdf2f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4281084705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4281084705
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3178182159
Short name T166
Test name
Test status
Simulation time 2205383713 ps
CPU time 71.09 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:54:26 PM PDT 24
Peak memory 237676 kb
Host smart-0dc88050-af63-4974-a6b9-4c5f45c8f1cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3178182159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3178182159
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3269244096
Short name T172
Test name
Test status
Simulation time 612334447 ps
CPU time 17.66 seconds
Started Jul 01 04:53:03 PM PDT 24
Finished Jul 01 04:53:22 PM PDT 24
Peak memory 240492 kb
Host smart-58a21a76-a7ee-4051-a9b3-952122deeeb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3269244096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3269244096
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1406656894
Short name T178
Test name
Test status
Simulation time 754219517 ps
CPU time 37.67 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:47 PM PDT 24
Peak memory 240528 kb
Host smart-b11cf056-d089-41f4-ad8a-bec1702caf3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1406656894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1406656894
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2144107041
Short name T174
Test name
Test status
Simulation time 133556350 ps
CPU time 1.96 seconds
Started Jul 01 04:53:22 PM PDT 24
Finished Jul 01 04:53:27 PM PDT 24
Peak memory 237672 kb
Host smart-ddc1e6e5-7e10-4885-95cb-88f336680f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2144107041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2144107041
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3270658660
Short name T168
Test name
Test status
Simulation time 57325575 ps
CPU time 2.21 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:32 PM PDT 24
Peak memory 237664 kb
Host smart-67f60d96-dad9-4a9a-9c5f-b95623bbdf3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3270658660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3270658660
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3832051292
Short name T179
Test name
Test status
Simulation time 186395406 ps
CPU time 4.11 seconds
Started Jul 01 04:53:08 PM PDT 24
Finished Jul 01 04:53:14 PM PDT 24
Peak memory 238064 kb
Host smart-93a116a7-9490-4bbf-8b9f-015617e07b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3832051292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3832051292
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3307456580
Short name T25
Test name
Test status
Simulation time 50177001353 ps
CPU time 5399.15 seconds
Started Jul 01 05:18:49 PM PDT 24
Finished Jul 01 06:48:53 PM PDT 24
Peak memory 339480 kb
Host smart-80de0fb3-54b9-4722-b170-6e5a976515e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307456580 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3307456580
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1606452846
Short name T19
Test name
Test status
Simulation time 87181879647 ps
CPU time 916.06 seconds
Started Jul 01 05:18:41 PM PDT 24
Finished Jul 01 05:34:05 PM PDT 24
Peak memory 273932 kb
Host smart-7ec260a3-5d2e-4aae-8cc5-b116300ab535
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606452846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1606452846
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1092460965
Short name T20
Test name
Test status
Simulation time 484626149618 ps
CPU time 1938.44 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:50:30 PM PDT 24
Peak memory 284136 kb
Host smart-e582e361-9556-4f28-bb0a-4ffb8eaef244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092460965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1092460965
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.188858686
Short name T751
Test name
Test status
Simulation time 1113211136 ps
CPU time 135.88 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:55:25 PM PDT 24
Peak memory 240616 kb
Host smart-59a21cca-d697-4f21-9626-3e83fab90b98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=188858686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.188858686
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3341634293
Short name T800
Test name
Test status
Simulation time 15091519949 ps
CPU time 444.93 seconds
Started Jul 01 04:52:55 PM PDT 24
Finished Jul 01 05:00:22 PM PDT 24
Peak memory 240692 kb
Host smart-960337f9-5701-4df5-8de6-948fe900667b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3341634293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3341634293
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3216453659
Short name T794
Test name
Test status
Simulation time 45503818 ps
CPU time 6.46 seconds
Started Jul 01 04:53:02 PM PDT 24
Finished Jul 01 04:53:10 PM PDT 24
Peak memory 240520 kb
Host smart-7f9b15cf-e61d-4297-905c-d0278ba94ff9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3216453659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3216453659
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1298221695
Short name T797
Test name
Test status
Simulation time 290983870 ps
CPU time 12.76 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 04:53:20 PM PDT 24
Peak memory 251824 kb
Host smart-4d929d6e-5450-415f-8e39-848da7184c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298221695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1298221695
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2242593262
Short name T259
Test name
Test status
Simulation time 411009739 ps
CPU time 8.88 seconds
Started Jul 01 04:52:59 PM PDT 24
Finished Jul 01 04:53:10 PM PDT 24
Peak memory 240560 kb
Host smart-52b83f74-02f4-4b8c-a952-646d4433de81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2242593262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2242593262
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3008506162
Short name T783
Test name
Test status
Simulation time 17512477 ps
CPU time 1.47 seconds
Started Jul 01 04:52:59 PM PDT 24
Finished Jul 01 04:53:02 PM PDT 24
Peak memory 237652 kb
Host smart-dee336c7-acaf-45a1-8e20-f7852273c5c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3008506162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3008506162
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2407188880
Short name T793
Test name
Test status
Simulation time 263811919 ps
CPU time 19.4 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 04:53:26 PM PDT 24
Peak memory 244896 kb
Host smart-875016b2-f293-49db-8763-893fcbb098b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2407188880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2407188880
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2612263451
Short name T149
Test name
Test status
Simulation time 12519639332 ps
CPU time 421.45 seconds
Started Jul 01 04:52:59 PM PDT 24
Finished Jul 01 05:00:02 PM PDT 24
Peak memory 268092 kb
Host smart-a158c6e7-3f55-4be5-953a-af48c0513c77
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612263451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2612263451
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.431637044
Short name T791
Test name
Test status
Simulation time 357716002 ps
CPU time 13.7 seconds
Started Jul 01 04:52:58 PM PDT 24
Finished Jul 01 04:53:14 PM PDT 24
Peak memory 248856 kb
Host smart-9ceeb7b5-9de1-43b6-9d26-5b785db9d966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=431637044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.431637044
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4190904974
Short name T721
Test name
Test status
Simulation time 3147801637 ps
CPU time 107.37 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 04:54:54 PM PDT 24
Peak memory 240576 kb
Host smart-19f03b6c-6fe8-4f11-b735-746b58e1ef4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4190904974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4190904974
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.653242221
Short name T741
Test name
Test status
Simulation time 10575643729 ps
CPU time 193.53 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:56:23 PM PDT 24
Peak memory 240532 kb
Host smart-6fc73bcd-b4d9-4931-9c74-0ecbcaf5d7ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=653242221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.653242221
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1106060553
Short name T796
Test name
Test status
Simulation time 400493619 ps
CPU time 5.66 seconds
Started Jul 01 04:53:06 PM PDT 24
Finished Jul 01 04:53:14 PM PDT 24
Peak memory 248712 kb
Host smart-f33615df-bc94-4325-8bf8-0b2d225ca501
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1106060553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1106060553
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.957513203
Short name T202
Test name
Test status
Simulation time 238309295 ps
CPU time 8.44 seconds
Started Jul 01 04:53:04 PM PDT 24
Finished Jul 01 04:53:13 PM PDT 24
Peak memory 252336 kb
Host smart-cbc2f80d-7b10-4a6b-b419-b591a5ddfa10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957513203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.957513203
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1024989443
Short name T770
Test name
Test status
Simulation time 60251947 ps
CPU time 5.08 seconds
Started Jul 01 04:53:06 PM PDT 24
Finished Jul 01 04:53:14 PM PDT 24
Peak memory 237508 kb
Host smart-51cb4c7e-4820-414c-8e9d-dd8526523cb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1024989443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1024989443
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.114541931
Short name T831
Test name
Test status
Simulation time 7664555 ps
CPU time 1.35 seconds
Started Jul 01 04:53:08 PM PDT 24
Finished Jul 01 04:53:12 PM PDT 24
Peak memory 237660 kb
Host smart-437b8bc4-f5ef-4b50-a4af-77afac66e79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=114541931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.114541931
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1319817087
Short name T798
Test name
Test status
Simulation time 170839772 ps
CPU time 21.19 seconds
Started Jul 01 04:53:06 PM PDT 24
Finished Jul 01 04:53:30 PM PDT 24
Peak memory 245716 kb
Host smart-484b49cb-596a-4a9e-968e-3bcb89fd2c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1319817087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1319817087
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4065159433
Short name T152
Test name
Test status
Simulation time 4591521402 ps
CPU time 560.64 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 05:02:27 PM PDT 24
Peak memory 265520 kb
Host smart-b21b09b2-e5a8-4324-85a4-871c72c88108
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065159433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4065159433
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3461133610
Short name T725
Test name
Test status
Simulation time 325589342 ps
CPU time 19.87 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:30 PM PDT 24
Peak memory 254112 kb
Host smart-2a0d9f88-c27d-449a-87ea-ae149fd7702a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3461133610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3461133610
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.844305060
Short name T815
Test name
Test status
Simulation time 575815683 ps
CPU time 9.23 seconds
Started Jul 01 04:53:22 PM PDT 24
Finished Jul 01 04:53:32 PM PDT 24
Peak memory 240608 kb
Host smart-c2ee2962-eb1f-4d9a-887d-56520fbbfabc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844305060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.844305060
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1801387100
Short name T716
Test name
Test status
Simulation time 96651611 ps
CPU time 7.52 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:53:36 PM PDT 24
Peak memory 236632 kb
Host smart-d4cc0151-f287-4b1b-afc0-6309a41b15f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1801387100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1801387100
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3778995160
Short name T829
Test name
Test status
Simulation time 7349479 ps
CPU time 1.48 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:29 PM PDT 24
Peak memory 237584 kb
Host smart-ed3665c6-d2ed-41f1-8036-9b8afb216b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3778995160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3778995160
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1048016877
Short name T801
Test name
Test status
Simulation time 454961458 ps
CPU time 16.85 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:47 PM PDT 24
Peak memory 244800 kb
Host smart-9bd92c95-70d1-40f2-81ad-9b448c84f729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1048016877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1048016877
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1946255934
Short name T809
Test name
Test status
Simulation time 1077608487 ps
CPU time 15.39 seconds
Started Jul 01 04:53:21 PM PDT 24
Finished Jul 01 04:53:38 PM PDT 24
Peak memory 252172 kb
Host smart-b49fa06f-d44a-4091-9566-1da935876dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1946255934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1946255934
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2848326523
Short name T731
Test name
Test status
Simulation time 432304771 ps
CPU time 15.37 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:45 PM PDT 24
Peak memory 256020 kb
Host smart-900e33ea-3b58-4134-b71d-48b855149e9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848326523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2848326523
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1942163322
Short name T814
Test name
Test status
Simulation time 86484408 ps
CPU time 3.2 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:30 PM PDT 24
Peak memory 237552 kb
Host smart-66431f36-0f4a-4b6c-881a-2703d2960694
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1942163322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1942163322
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2891450679
Short name T823
Test name
Test status
Simulation time 11191648 ps
CPU time 1.44 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:29 PM PDT 24
Peak memory 236636 kb
Host smart-efc28b0e-2476-4e2f-833a-3590d5e3be9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2891450679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2891450679
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1761228157
Short name T821
Test name
Test status
Simulation time 497692738 ps
CPU time 38.38 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:54:05 PM PDT 24
Peak memory 248720 kb
Host smart-d9bb5596-f29e-4d5e-ad32-eeec01b785e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1761228157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1761228157
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2541216839
Short name T140
Test name
Test status
Simulation time 1317310802 ps
CPU time 106.61 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:55:16 PM PDT 24
Peak memory 265332 kb
Host smart-0c3b8ba0-ad74-47fb-b1c6-e48d0c3f13ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2541216839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2541216839
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2504507454
Short name T744
Test name
Test status
Simulation time 342160011 ps
CPU time 11.81 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:53:41 PM PDT 24
Peak memory 248880 kb
Host smart-8f3752df-eb3b-458e-b4b1-0f86702602c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504507454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2504507454
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1117491805
Short name T757
Test name
Test status
Simulation time 77221421 ps
CPU time 5.86 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:36 PM PDT 24
Peak memory 239824 kb
Host smart-8cdeb1ff-099e-48d7-ab79-ab82c76fe97a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117491805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1117491805
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2148861692
Short name T191
Test name
Test status
Simulation time 64832328 ps
CPU time 6.05 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:34 PM PDT 24
Peak memory 237516 kb
Host smart-8da22891-f8e1-4b54-a5a0-22a460f89e7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2148861692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2148861692
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3088351324
Short name T780
Test name
Test status
Simulation time 1991216446 ps
CPU time 33.23 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:54:02 PM PDT 24
Peak memory 244864 kb
Host smart-ff44fd2f-7a73-46d0-bfbd-b590c991fab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3088351324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3088351324
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2767851564
Short name T154
Test name
Test status
Simulation time 25133221244 ps
CPU time 468.47 seconds
Started Jul 01 04:53:22 PM PDT 24
Finished Jul 01 05:01:13 PM PDT 24
Peak memory 270720 kb
Host smart-1547ffac-3a62-46a8-bad6-e9c0603ec651
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767851564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2767851564
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2532889771
Short name T718
Test name
Test status
Simulation time 125152423 ps
CPU time 7.26 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:33 PM PDT 24
Peak memory 248032 kb
Host smart-2651fa11-f909-4d5d-9219-de34521db0f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2532889771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2532889771
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.883450518
Short name T724
Test name
Test status
Simulation time 353422751 ps
CPU time 14.19 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:53:43 PM PDT 24
Peak memory 243884 kb
Host smart-ac3c5d89-55ba-4cce-88fd-e7cb44c9a5c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883450518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.883450518
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.938744138
Short name T735
Test name
Test status
Simulation time 96633910 ps
CPU time 8.15 seconds
Started Jul 01 04:53:27 PM PDT 24
Finished Jul 01 04:53:39 PM PDT 24
Peak memory 237564 kb
Host smart-ce270ef7-7715-454e-b992-4d8852582fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=938744138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.938744138
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4215124817
Short name T730
Test name
Test status
Simulation time 192833352 ps
CPU time 23.51 seconds
Started Jul 01 04:53:27 PM PDT 24
Finished Jul 01 04:53:55 PM PDT 24
Peak memory 245776 kb
Host smart-dd30e36a-b699-482a-beb0-8b91ad5a278e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4215124817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4215124817
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.701764710
Short name T148
Test name
Test status
Simulation time 10690093514 ps
CPU time 390.61 seconds
Started Jul 01 04:53:26 PM PDT 24
Finished Jul 01 05:00:01 PM PDT 24
Peak memory 265572 kb
Host smart-26926dce-e0a2-4a9f-847b-f3a36d19cc1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=701764710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.701764710
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1846560391
Short name T131
Test name
Test status
Simulation time 19602732515 ps
CPU time 751.48 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 05:06:01 PM PDT 24
Peak memory 265396 kb
Host smart-3811becb-0f13-4014-a13b-4e00fa190413
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846560391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1846560391
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2632226475
Short name T792
Test name
Test status
Simulation time 92314918 ps
CPU time 7.45 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:53:36 PM PDT 24
Peak memory 248632 kb
Host smart-3678f281-a98a-43a2-b325-6a0f79f8d5b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2632226475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2632226475
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1299704471
Short name T170
Test name
Test status
Simulation time 151263506 ps
CPU time 21.27 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:53:49 PM PDT 24
Peak memory 240540 kb
Host smart-f5b2d2fb-d456-4ab0-b53a-1cf0ec5165dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1299704471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1299704471
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1447866435
Short name T746
Test name
Test status
Simulation time 37590725 ps
CPU time 5.28 seconds
Started Jul 01 04:53:38 PM PDT 24
Finished Jul 01 04:53:45 PM PDT 24
Peak memory 248640 kb
Host smart-06abef0d-5c5d-4ac9-b326-6006bd3eae9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447866435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1447866435
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3236956811
Short name T806
Test name
Test status
Simulation time 91590924 ps
CPU time 4.44 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:42 PM PDT 24
Peak memory 237572 kb
Host smart-c09ca41d-9330-4b08-bd0e-c5e39edb8b99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3236956811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3236956811
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4185949717
Short name T726
Test name
Test status
Simulation time 10352133 ps
CPU time 1.35 seconds
Started Jul 01 04:53:24 PM PDT 24
Finished Jul 01 04:53:30 PM PDT 24
Peak memory 236664 kb
Host smart-29db58b2-30ea-4eba-8bd0-25cad4012e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4185949717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4185949717
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.534245293
Short name T194
Test name
Test status
Simulation time 525529104 ps
CPU time 38.22 seconds
Started Jul 01 04:53:37 PM PDT 24
Finished Jul 01 04:54:17 PM PDT 24
Peak memory 245784 kb
Host smart-e22ace10-576c-4e3e-a8d8-b06f45a4bbc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=534245293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.534245293
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2099024258
Short name T150
Test name
Test status
Simulation time 10820946038 ps
CPU time 204.9 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:56:55 PM PDT 24
Peak memory 265484 kb
Host smart-65a9452f-684c-4152-a471-9be17be8a263
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2099024258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2099024258
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3809693470
Short name T813
Test name
Test status
Simulation time 2359053488 ps
CPU time 292.05 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:58:22 PM PDT 24
Peak memory 265468 kb
Host smart-c52abf59-4f2a-44b2-bab9-6fa81519d022
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809693470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3809693470
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.250787228
Short name T785
Test name
Test status
Simulation time 293221548 ps
CPU time 11.23 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:39 PM PDT 24
Peak memory 248764 kb
Host smart-96ee5c3a-a7be-467f-b799-e45cc4731005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=250787228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.250787228
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.49361580
Short name T371
Test name
Test status
Simulation time 31497527 ps
CPU time 4.88 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:43 PM PDT 24
Peak memory 240480 kb
Host smart-d18919b2-0cab-478a-8aba-93c8211671b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49361580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.alert_handler_csr_mem_rw_with_rand_reset.49361580
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.314246826
Short name T736
Test name
Test status
Simulation time 282158876 ps
CPU time 5.22 seconds
Started Jul 01 04:53:35 PM PDT 24
Finished Jul 01 04:53:42 PM PDT 24
Peak memory 236760 kb
Host smart-9dead1b4-9db8-499f-8d40-2d86c4fe90b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=314246826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.314246826
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4004137040
Short name T771
Test name
Test status
Simulation time 8738573 ps
CPU time 1.54 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:39 PM PDT 24
Peak memory 237580 kb
Host smart-8980d205-9db0-43da-ae27-08a1b07e611f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4004137040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4004137040
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4252986488
Short name T737
Test name
Test status
Simulation time 653681050 ps
CPU time 18.27 seconds
Started Jul 01 04:53:35 PM PDT 24
Finished Jul 01 04:53:55 PM PDT 24
Peak memory 244824 kb
Host smart-bde49402-8298-4fc1-93e9-681237af40cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4252986488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4252986488
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2602177417
Short name T157
Test name
Test status
Simulation time 4776146722 ps
CPU time 167.99 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:56:26 PM PDT 24
Peak memory 265384 kb
Host smart-651b7c2c-c19d-4202-94b3-dbf7cea04ef7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2602177417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2602177417
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2546461054
Short name T811
Test name
Test status
Simulation time 356144886 ps
CPU time 7.95 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:45 PM PDT 24
Peak memory 248772 kb
Host smart-7c8f1203-c256-426c-9d61-624aa25cb7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2546461054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2546461054
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4146426925
Short name T719
Test name
Test status
Simulation time 142815541 ps
CPU time 11.52 seconds
Started Jul 01 04:53:35 PM PDT 24
Finished Jul 01 04:53:47 PM PDT 24
Peak memory 250760 kb
Host smart-5bb608bd-318d-4f7d-a2d2-ceb99d7db7f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146426925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4146426925
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1199198218
Short name T727
Test name
Test status
Simulation time 68588817 ps
CPU time 5.99 seconds
Started Jul 01 04:53:40 PM PDT 24
Finished Jul 01 04:53:48 PM PDT 24
Peak memory 237556 kb
Host smart-c812eb31-8336-4140-8286-0771d28b0dc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1199198218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1199198218
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.305849884
Short name T812
Test name
Test status
Simulation time 11379474 ps
CPU time 1.36 seconds
Started Jul 01 04:53:35 PM PDT 24
Finished Jul 01 04:53:38 PM PDT 24
Peak memory 237592 kb
Host smart-406b9fab-cf0f-4869-9f40-dc3e5c545552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=305849884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.305849884
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2159288964
Short name T769
Test name
Test status
Simulation time 315733373 ps
CPU time 19.95 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:58 PM PDT 24
Peak memory 244848 kb
Host smart-a6deba18-03f4-4e2d-be26-5226731494b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2159288964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2159288964
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2157139770
Short name T122
Test name
Test status
Simulation time 3588753637 ps
CPU time 139.32 seconds
Started Jul 01 04:53:39 PM PDT 24
Finished Jul 01 04:55:59 PM PDT 24
Peak memory 266020 kb
Host smart-c624b8d1-5c99-4a0f-8e0d-85ec4a73b2f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2157139770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2157139770
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1040997734
Short name T153
Test name
Test status
Simulation time 30186388218 ps
CPU time 638.98 seconds
Started Jul 01 04:53:37 PM PDT 24
Finished Jul 01 05:04:18 PM PDT 24
Peak memory 268272 kb
Host smart-21b1a370-ba91-40e0-b216-5db3ba090a54
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040997734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1040997734
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2632527051
Short name T765
Test name
Test status
Simulation time 381929474 ps
CPU time 5.07 seconds
Started Jul 01 04:53:34 PM PDT 24
Finished Jul 01 04:53:40 PM PDT 24
Peak memory 248788 kb
Host smart-068fcca7-8c1a-463c-91ed-540698993a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2632527051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2632527051
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.458453505
Short name T728
Test name
Test status
Simulation time 132647047 ps
CPU time 10.66 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:49 PM PDT 24
Peak memory 255644 kb
Host smart-2056d7a8-2dae-4888-b320-49767bee552a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458453505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.458453505
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.618738548
Short name T715
Test name
Test status
Simulation time 26719945 ps
CPU time 3.26 seconds
Started Jul 01 04:53:39 PM PDT 24
Finished Jul 01 04:53:44 PM PDT 24
Peak memory 237640 kb
Host smart-664d2eb9-93cd-4076-90a7-2241eb010554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=618738548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.618738548
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1351190460
Short name T772
Test name
Test status
Simulation time 16024304 ps
CPU time 1.45 seconds
Started Jul 01 04:53:37 PM PDT 24
Finished Jul 01 04:53:41 PM PDT 24
Peak memory 236604 kb
Host smart-665e672c-ac73-41a8-99d8-1fa5362257a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1351190460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1351190460
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2366089124
Short name T807
Test name
Test status
Simulation time 640523152 ps
CPU time 23.59 seconds
Started Jul 01 04:53:37 PM PDT 24
Finished Jul 01 04:54:03 PM PDT 24
Peak memory 245840 kb
Host smart-791782d9-fcd9-47a6-917a-0a5c4ab7e4a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2366089124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2366089124
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2741102990
Short name T144
Test name
Test status
Simulation time 11639607446 ps
CPU time 200.13 seconds
Started Jul 01 04:53:38 PM PDT 24
Finished Jul 01 04:57:00 PM PDT 24
Peak memory 265484 kb
Host smart-bb8573b3-8d87-494d-a7f5-fe93f9309510
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2741102990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2741102990
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2390918418
Short name T764
Test name
Test status
Simulation time 178943179 ps
CPU time 10.92 seconds
Started Jul 01 04:53:38 PM PDT 24
Finished Jul 01 04:53:51 PM PDT 24
Peak memory 255364 kb
Host smart-980e2b39-787c-4d94-9cad-916547b040f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2390918418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2390918418
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2963832641
Short name T832
Test name
Test status
Simulation time 115856361 ps
CPU time 8.67 seconds
Started Jul 01 04:53:39 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 253028 kb
Host smart-7181d322-a91a-4523-99e6-d88956f048c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963832641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2963832641
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1484441124
Short name T201
Test name
Test status
Simulation time 64966609 ps
CPU time 3.37 seconds
Started Jul 01 04:53:40 PM PDT 24
Finished Jul 01 04:53:44 PM PDT 24
Peak memory 237536 kb
Host smart-31cc6c81-c42f-496b-8f5e-7e98edca2e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1484441124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1484441124
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.481375448
Short name T720
Test name
Test status
Simulation time 7187762 ps
CPU time 1.42 seconds
Started Jul 01 04:53:38 PM PDT 24
Finished Jul 01 04:53:41 PM PDT 24
Peak memory 235668 kb
Host smart-60a06f90-0551-40dd-ac61-215bf96c564c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481375448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.481375448
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3476000629
Short name T759
Test name
Test status
Simulation time 1321685847 ps
CPU time 49.22 seconds
Started Jul 01 04:53:40 PM PDT 24
Finished Jul 01 04:54:30 PM PDT 24
Peak memory 248788 kb
Host smart-89d6e0d7-06b3-4156-8037-0cf13e6c6a51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3476000629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3476000629
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1396582839
Short name T143
Test name
Test status
Simulation time 2527818030 ps
CPU time 340.04 seconds
Started Jul 01 04:53:40 PM PDT 24
Finished Jul 01 04:59:22 PM PDT 24
Peak memory 265476 kb
Host smart-18fa12c6-79ad-4556-955e-f7cc875be463
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396582839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1396582839
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1751113205
Short name T822
Test name
Test status
Simulation time 1304700270 ps
CPU time 23.9 seconds
Started Jul 01 04:53:39 PM PDT 24
Finished Jul 01 04:54:04 PM PDT 24
Peak memory 254476 kb
Host smart-93a3b072-6e16-453a-acfc-de8851376967
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1751113205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1751113205
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.851749314
Short name T803
Test name
Test status
Simulation time 62786015 ps
CPU time 2.33 seconds
Started Jul 01 04:53:38 PM PDT 24
Finished Jul 01 04:53:42 PM PDT 24
Peak memory 236716 kb
Host smart-112c2999-178d-4385-ae46-a470f260994a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=851749314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.851749314
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.729366275
Short name T820
Test name
Test status
Simulation time 107093680 ps
CPU time 7.16 seconds
Started Jul 01 04:53:45 PM PDT 24
Finished Jul 01 04:53:53 PM PDT 24
Peak memory 240576 kb
Host smart-0bd87399-0cb9-404d-8bb1-3b95311487f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729366275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.729366275
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2789365380
Short name T750
Test name
Test status
Simulation time 257763321 ps
CPU time 9.82 seconds
Started Jul 01 04:53:36 PM PDT 24
Finished Jul 01 04:53:47 PM PDT 24
Peak memory 240524 kb
Host smart-7f45ee8d-53e4-4148-ba5f-d353a46a52f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2789365380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2789365380
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2582012706
Short name T729
Test name
Test status
Simulation time 12215257 ps
CPU time 1.41 seconds
Started Jul 01 04:53:35 PM PDT 24
Finished Jul 01 04:53:38 PM PDT 24
Peak memory 236596 kb
Host smart-383872f6-05a3-412a-8fcc-01c53cfef707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2582012706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2582012706
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3704130201
Short name T192
Test name
Test status
Simulation time 2371524941 ps
CPU time 21.68 seconds
Started Jul 01 04:53:52 PM PDT 24
Finished Jul 01 04:54:17 PM PDT 24
Peak memory 245688 kb
Host smart-68e742a9-6c7a-47f6-82a0-cddec8fdf7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3704130201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3704130201
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1508647499
Short name T158
Test name
Test status
Simulation time 13432934432 ps
CPU time 198.83 seconds
Started Jul 01 04:53:39 PM PDT 24
Finished Jul 01 04:57:00 PM PDT 24
Peak memory 265440 kb
Host smart-7b7c9559-15ed-4f97-90da-4c194da502f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1508647499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1508647499
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2971552150
Short name T742
Test name
Test status
Simulation time 99743079 ps
CPU time 3.87 seconds
Started Jul 01 04:53:38 PM PDT 24
Finished Jul 01 04:53:43 PM PDT 24
Peak memory 248520 kb
Host smart-510b71d3-5c9b-46b2-9f91-aaf739001b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2971552150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2971552150
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1651054576
Short name T761
Test name
Test status
Simulation time 4465204043 ps
CPU time 155.34 seconds
Started Jul 01 04:53:10 PM PDT 24
Finished Jul 01 04:55:47 PM PDT 24
Peak memory 240596 kb
Host smart-095885a3-c67b-41b4-b534-fa8766b3bf1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1651054576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1651054576
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.634939905
Short name T370
Test name
Test status
Simulation time 2854957623 ps
CPU time 190.07 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:56:20 PM PDT 24
Peak memory 237636 kb
Host smart-86c56685-4797-420e-988f-f54a970412e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=634939905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.634939905
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.918038174
Short name T714
Test name
Test status
Simulation time 71095557 ps
CPU time 6.21 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 04:53:13 PM PDT 24
Peak memory 249204 kb
Host smart-89adcfd7-0345-4ec7-bafd-c414df21c94a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=918038174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.918038174
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2242722250
Short name T175
Test name
Test status
Simulation time 281758718 ps
CPU time 5.71 seconds
Started Jul 01 04:53:08 PM PDT 24
Finished Jul 01 04:53:16 PM PDT 24
Peak memory 238724 kb
Host smart-f62bac7f-ba28-4210-b079-245fda76d6ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242722250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2242722250
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1969790380
Short name T739
Test name
Test status
Simulation time 122875369 ps
CPU time 5.38 seconds
Started Jul 01 04:53:10 PM PDT 24
Finished Jul 01 04:53:17 PM PDT 24
Peak memory 237568 kb
Host smart-1087c43d-572e-4118-b56e-4879fb623d70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1969790380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1969790380
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2017875914
Short name T795
Test name
Test status
Simulation time 11337123 ps
CPU time 1.36 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:11 PM PDT 24
Peak memory 236588 kb
Host smart-11f6710a-e431-430c-8c7c-97c579781a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2017875914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2017875914
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1312757980
Short name T190
Test name
Test status
Simulation time 717611171 ps
CPU time 21.14 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:31 PM PDT 24
Peak memory 244812 kb
Host smart-2ca83c57-9342-45dd-b9d8-c7e7a353426f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1312757980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1312757980
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1524211428
Short name T129
Test name
Test status
Simulation time 2860621425 ps
CPU time 185.33 seconds
Started Jul 01 04:53:04 PM PDT 24
Finished Jul 01 04:56:11 PM PDT 24
Peak memory 267468 kb
Host smart-162d6bad-e601-4aeb-958d-3182143f8a2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1524211428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1524211428
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1344458698
Short name T369
Test name
Test status
Simulation time 16554090476 ps
CPU time 1178.06 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 05:12:48 PM PDT 24
Peak memory 272152 kb
Host smart-79aab764-6e46-41f6-9dfa-3b2cdfaee0a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344458698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1344458698
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4016681641
Short name T830
Test name
Test status
Simulation time 408760200 ps
CPU time 14.67 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:24 PM PDT 24
Peak memory 254644 kb
Host smart-9b30d198-34e0-4011-9cc0-74bdc6b27ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016681641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4016681641
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3245286111
Short name T265
Test name
Test status
Simulation time 810472953 ps
CPU time 34.19 seconds
Started Jul 01 04:53:06 PM PDT 24
Finished Jul 01 04:53:42 PM PDT 24
Peak memory 240528 kb
Host smart-2b3e8261-e58b-45fc-91ef-4fb0fc0ccaba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3245286111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3245286111
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1535994383
Short name T364
Test name
Test status
Simulation time 6460600 ps
CPU time 1.46 seconds
Started Jul 01 04:53:52 PM PDT 24
Finished Jul 01 04:53:56 PM PDT 24
Peak memory 237592 kb
Host smart-07aa368f-6020-45a2-af68-d65aeee24db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1535994383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1535994383
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2796570789
Short name T754
Test name
Test status
Simulation time 25896346 ps
CPU time 1.53 seconds
Started Jul 01 04:53:52 PM PDT 24
Finished Jul 01 04:53:56 PM PDT 24
Peak memory 237540 kb
Host smart-2529393f-074d-4de2-bfc1-104b5c12e630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2796570789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2796570789
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.57276647
Short name T774
Test name
Test status
Simulation time 14641838 ps
CPU time 1.58 seconds
Started Jul 01 04:53:47 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 235668 kb
Host smart-cd65863a-57cc-4134-9553-80ca02030d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=57276647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.57276647
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.675015911
Short name T366
Test name
Test status
Simulation time 6377769 ps
CPU time 1.43 seconds
Started Jul 01 04:53:46 PM PDT 24
Finished Jul 01 04:53:49 PM PDT 24
Peak memory 236636 kb
Host smart-3c368eea-d9ea-4ee7-96f3-40d524a2a2ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=675015911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.675015911
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.579552397
Short name T749
Test name
Test status
Simulation time 13907044 ps
CPU time 1.7 seconds
Started Jul 01 04:53:51 PM PDT 24
Finished Jul 01 04:53:55 PM PDT 24
Peak memory 236632 kb
Host smart-849aec62-15cf-4730-a0a9-bb2cbbeec5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=579552397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.579552397
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2526682552
Short name T164
Test name
Test status
Simulation time 33522308 ps
CPU time 1.32 seconds
Started Jul 01 04:53:47 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 237492 kb
Host smart-e2d4328d-b4a0-4c80-bc09-e845f50b8071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2526682552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2526682552
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1318335524
Short name T808
Test name
Test status
Simulation time 18176489 ps
CPU time 1.51 seconds
Started Jul 01 04:53:46 PM PDT 24
Finished Jul 01 04:53:49 PM PDT 24
Peak memory 237584 kb
Host smart-9cabc9b2-9def-47f3-8f6e-8ad5f2cd575d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1318335524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1318335524
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1811673000
Short name T722
Test name
Test status
Simulation time 16076695 ps
CPU time 1.36 seconds
Started Jul 01 04:53:46 PM PDT 24
Finished Jul 01 04:53:48 PM PDT 24
Peak memory 235636 kb
Host smart-4b5f5b0c-074f-42a1-a197-4b72468fbe0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1811673000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1811673000
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.205036518
Short name T773
Test name
Test status
Simulation time 10794856 ps
CPU time 1.5 seconds
Started Jul 01 04:53:45 PM PDT 24
Finished Jul 01 04:53:47 PM PDT 24
Peak memory 236632 kb
Host smart-d01d837b-24cf-49e9-859b-3a61e2bf2a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=205036518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.205036518
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3691393737
Short name T755
Test name
Test status
Simulation time 6820585 ps
CPU time 1.46 seconds
Started Jul 01 04:53:50 PM PDT 24
Finished Jul 01 04:53:54 PM PDT 24
Peak memory 236640 kb
Host smart-19aaf455-7bc6-44af-8d43-a735ec170bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3691393737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3691393737
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3930912166
Short name T775
Test name
Test status
Simulation time 571878530 ps
CPU time 71.12 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:54:20 PM PDT 24
Peak memory 237588 kb
Host smart-a9a89e07-391c-479b-af6c-b26915a96e8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3930912166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3930912166
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4163760641
Short name T816
Test name
Test status
Simulation time 8685421008 ps
CPU time 197.69 seconds
Started Jul 01 04:53:09 PM PDT 24
Finished Jul 01 04:56:29 PM PDT 24
Peak memory 237584 kb
Host smart-a2d278ff-0cfb-40fc-924b-40cfc0699309
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4163760641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4163760641
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3326707595
Short name T777
Test name
Test status
Simulation time 66979856 ps
CPU time 5.66 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 04:53:12 PM PDT 24
Peak memory 240516 kb
Host smart-86692cf4-cf59-49e4-9f2f-7a9a14812f9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3326707595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3326707595
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2456530120
Short name T745
Test name
Test status
Simulation time 198119592 ps
CPU time 8.3 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:18 PM PDT 24
Peak memory 252768 kb
Host smart-1abbf1d4-3c2d-4b90-b1b7-7aaad594a521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456530120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2456530120
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2946859643
Short name T257
Test name
Test status
Simulation time 242693565 ps
CPU time 9.21 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:23 PM PDT 24
Peak memory 240524 kb
Host smart-be2fb6a5-578b-47bf-90d7-38f74819a537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2946859643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2946859643
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2857733815
Short name T743
Test name
Test status
Simulation time 12366036 ps
CPU time 1.28 seconds
Started Jul 01 04:53:04 PM PDT 24
Finished Jul 01 04:53:06 PM PDT 24
Peak memory 236660 kb
Host smart-9469936b-10a8-4cab-b467-b46edeb48a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2857733815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2857733815
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3880185904
Short name T732
Test name
Test status
Simulation time 166946567 ps
CPU time 25.11 seconds
Started Jul 01 04:53:09 PM PDT 24
Finished Jul 01 04:53:36 PM PDT 24
Peak memory 245724 kb
Host smart-261ca3e1-1d2e-41c3-a45c-6d5022e7c583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3880185904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3880185904
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2432446165
Short name T130
Test name
Test status
Simulation time 7437747130 ps
CPU time 311.63 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 04:58:18 PM PDT 24
Peak memory 265548 kb
Host smart-9413da4f-2fb9-4c83-8712-3462b2ffb14b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432446165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2432446165
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3249184103
Short name T833
Test name
Test status
Simulation time 163715551 ps
CPU time 11.06 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:25 PM PDT 24
Peak memory 255448 kb
Host smart-dad7ad92-80e4-4079-b69e-89eeaceda303
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3249184103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3249184103
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3992286360
Short name T180
Test name
Test status
Simulation time 71395627 ps
CPU time 4.47 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:14 PM PDT 24
Peak memory 237572 kb
Host smart-04f739be-e442-4dff-8495-d265d3958c06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3992286360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3992286360
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3494777628
Short name T252
Test name
Test status
Simulation time 28478067 ps
CPU time 2.27 seconds
Started Jul 01 04:53:51 PM PDT 24
Finished Jul 01 04:53:56 PM PDT 24
Peak memory 237576 kb
Host smart-8b08ae77-19cc-48fe-8f91-f33de3d6c0d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3494777628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3494777628
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.289943898
Short name T723
Test name
Test status
Simulation time 13590039 ps
CPU time 1.67 seconds
Started Jul 01 04:53:49 PM PDT 24
Finished Jul 01 04:53:53 PM PDT 24
Peak memory 237528 kb
Host smart-2e3186c0-a6be-4261-8d5b-0bc89f3e37a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=289943898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.289943898
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3223382356
Short name T362
Test name
Test status
Simulation time 24680262 ps
CPU time 1.62 seconds
Started Jul 01 04:53:47 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 237564 kb
Host smart-407f5dd6-66fd-4fc6-beb6-53b40927e039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3223382356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3223382356
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.84333275
Short name T799
Test name
Test status
Simulation time 24167836 ps
CPU time 1.56 seconds
Started Jul 01 04:53:50 PM PDT 24
Finished Jul 01 04:53:54 PM PDT 24
Peak memory 237528 kb
Host smart-2c41901d-d955-4477-9efe-50df78603ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=84333275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.84333275
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3899012321
Short name T162
Test name
Test status
Simulation time 6240618 ps
CPU time 1.44 seconds
Started Jul 01 04:53:49 PM PDT 24
Finished Jul 01 04:53:53 PM PDT 24
Peak memory 236584 kb
Host smart-a409c478-8148-4649-ab5c-0848ce6f8ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3899012321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3899012321
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2047521055
Short name T782
Test name
Test status
Simulation time 6398312 ps
CPU time 1.43 seconds
Started Jul 01 04:53:49 PM PDT 24
Finished Jul 01 04:53:51 PM PDT 24
Peak memory 237596 kb
Host smart-fd4a58b3-7ae0-4be8-89e5-ff5f1bdf7958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2047521055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2047521055
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3140985578
Short name T763
Test name
Test status
Simulation time 10235393 ps
CPU time 1.54 seconds
Started Jul 01 04:53:51 PM PDT 24
Finished Jul 01 04:53:55 PM PDT 24
Peak memory 237592 kb
Host smart-846f317f-75fb-406e-a82a-95f898b29472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3140985578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3140985578
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3051214840
Short name T733
Test name
Test status
Simulation time 19805389 ps
CPU time 1.56 seconds
Started Jul 01 04:53:47 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 236632 kb
Host smart-87d82d14-2fba-4634-98c0-310bc98a6496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3051214840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3051214840
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2486191582
Short name T758
Test name
Test status
Simulation time 10014742 ps
CPU time 1.61 seconds
Started Jul 01 04:53:47 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 237688 kb
Host smart-e34377b7-d590-4ef5-81f0-c2e0f624e011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2486191582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2486191582
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1518743850
Short name T827
Test name
Test status
Simulation time 1213639077 ps
CPU time 160.16 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:56:11 PM PDT 24
Peak memory 240636 kb
Host smart-2c780d27-2efa-487a-8506-5c8c269448c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1518743850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1518743850
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2112964366
Short name T781
Test name
Test status
Simulation time 3146082780 ps
CPU time 114.15 seconds
Started Jul 01 04:53:05 PM PDT 24
Finished Jul 01 04:55:01 PM PDT 24
Peak memory 240592 kb
Host smart-eb4cc011-2469-4162-aa55-93e13bc0bfc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2112964366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2112964366
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2931679990
Short name T790
Test name
Test status
Simulation time 54090235 ps
CPU time 4.92 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 04:53:14 PM PDT 24
Peak memory 248708 kb
Host smart-a04693e8-e269-44d8-be7b-9169fd11646f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2931679990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2931679990
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1944038528
Short name T368
Test name
Test status
Simulation time 125112744 ps
CPU time 4.83 seconds
Started Jul 01 04:53:16 PM PDT 24
Finished Jul 01 04:53:23 PM PDT 24
Peak memory 238160 kb
Host smart-51be4c17-bd69-433c-9b2c-b9e172671906
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944038528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1944038528
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.144228063
Short name T258
Test name
Test status
Simulation time 125378807 ps
CPU time 5.88 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:20 PM PDT 24
Peak memory 237576 kb
Host smart-c982714c-6e37-4c56-81ad-068f5fc8ad25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=144228063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.144228063
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1048213585
Short name T824
Test name
Test status
Simulation time 14939270 ps
CPU time 1.37 seconds
Started Jul 01 04:53:06 PM PDT 24
Finished Jul 01 04:53:10 PM PDT 24
Peak memory 237560 kb
Host smart-11fb445d-cf59-49b5-a159-71e26ca1d771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1048213585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1048213585
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.615598829
Short name T786
Test name
Test status
Simulation time 172344484 ps
CPU time 14.87 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:45 PM PDT 24
Peak memory 245888 kb
Host smart-14e068da-ad03-4866-b2cb-08397173b9cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=615598829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.615598829
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2154634232
Short name T151
Test name
Test status
Simulation time 14631877363 ps
CPU time 573.73 seconds
Started Jul 01 04:53:07 PM PDT 24
Finished Jul 01 05:02:43 PM PDT 24
Peak memory 273116 kb
Host smart-2007f9b9-9420-4ce3-91ad-f0c4228114df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154634232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2154634232
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1652580233
Short name T810
Test name
Test status
Simulation time 77096854 ps
CPU time 8.32 seconds
Started Jul 01 04:53:03 PM PDT 24
Finished Jul 01 04:53:12 PM PDT 24
Peak memory 255628 kb
Host smart-a5cb3c99-11f8-45a4-b1aa-34d4a2742c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1652580233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1652580233
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2046470179
Short name T748
Test name
Test status
Simulation time 15233519 ps
CPU time 1.28 seconds
Started Jul 01 04:53:48 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 237588 kb
Host smart-cdce34c2-2a27-4ae3-a42d-50500928e95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2046470179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2046470179
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1202051271
Short name T789
Test name
Test status
Simulation time 18375054 ps
CPU time 1.39 seconds
Started Jul 01 04:53:46 PM PDT 24
Finished Jul 01 04:53:49 PM PDT 24
Peak memory 237576 kb
Host smart-32954a4b-134c-4fc6-b8be-2ecc8c86ae3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1202051271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1202051271
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4128030922
Short name T738
Test name
Test status
Simulation time 12961778 ps
CPU time 1.43 seconds
Started Jul 01 04:53:48 PM PDT 24
Finished Jul 01 04:53:50 PM PDT 24
Peak memory 236652 kb
Host smart-189305a5-8561-404a-aeb0-da94486ab9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4128030922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4128030922
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3327491475
Short name T365
Test name
Test status
Simulation time 9307270 ps
CPU time 1.44 seconds
Started Jul 01 04:53:49 PM PDT 24
Finished Jul 01 04:53:52 PM PDT 24
Peak memory 236652 kb
Host smart-4c15c716-94ca-4300-ae89-fe69668c1711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3327491475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3327491475
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4005822406
Short name T818
Test name
Test status
Simulation time 8879177 ps
CPU time 1.35 seconds
Started Jul 01 04:53:45 PM PDT 24
Finished Jul 01 04:53:47 PM PDT 24
Peak memory 235620 kb
Host smart-e095f4d6-56da-4bfb-8f5a-c6efd86fce6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4005822406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4005822406
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.26615173
Short name T787
Test name
Test status
Simulation time 13324275 ps
CPU time 1.49 seconds
Started Jul 01 04:53:41 PM PDT 24
Finished Jul 01 04:53:44 PM PDT 24
Peak memory 236648 kb
Host smart-3498f2cd-2af2-43ba-8ac9-59f7d2e1ca26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=26615173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.26615173
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3125378751
Short name T753
Test name
Test status
Simulation time 20955628 ps
CPU time 1.45 seconds
Started Jul 01 04:53:50 PM PDT 24
Finished Jul 01 04:53:53 PM PDT 24
Peak memory 236632 kb
Host smart-3247cf02-2f8a-45b1-91c8-01cb98be0c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3125378751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3125378751
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4250014986
Short name T363
Test name
Test status
Simulation time 10465097 ps
CPU time 1.64 seconds
Started Jul 01 04:53:49 PM PDT 24
Finished Jul 01 04:53:52 PM PDT 24
Peak memory 236640 kb
Host smart-ce69006e-e744-4668-b6f0-e6268ad36812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4250014986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4250014986
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4132085723
Short name T760
Test name
Test status
Simulation time 10407585 ps
CPU time 1.4 seconds
Started Jul 01 04:53:50 PM PDT 24
Finished Jul 01 04:53:54 PM PDT 24
Peak memory 235620 kb
Host smart-accce273-d0cb-4a42-a74c-c632d6c96129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4132085723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4132085723
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.507514305
Short name T752
Test name
Test status
Simulation time 11039086 ps
CPU time 1.36 seconds
Started Jul 01 04:53:55 PM PDT 24
Finished Jul 01 04:53:59 PM PDT 24
Peak memory 236636 kb
Host smart-42fa6bb5-9839-4b45-8233-566d94b0c1a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=507514305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.507514305
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3663074492
Short name T819
Test name
Test status
Simulation time 378855882 ps
CPU time 5.43 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:18 PM PDT 24
Peak memory 252052 kb
Host smart-b868c135-93d8-4554-b1e6-a56cb3f151b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663074492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3663074492
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.613137030
Short name T778
Test name
Test status
Simulation time 493643490 ps
CPU time 9.9 seconds
Started Jul 01 04:53:15 PM PDT 24
Finished Jul 01 04:53:27 PM PDT 24
Peak memory 240520 kb
Host smart-7279a1b5-f50a-41e8-aa63-08ca9f0b158d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=613137030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.613137030
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1955841944
Short name T768
Test name
Test status
Simulation time 7320566 ps
CPU time 1.35 seconds
Started Jul 01 04:53:12 PM PDT 24
Finished Jul 01 04:53:16 PM PDT 24
Peak memory 235696 kb
Host smart-17769436-fbef-4503-b032-6753078fa9b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1955841944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1955841944
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1993352849
Short name T193
Test name
Test status
Simulation time 1419287178 ps
CPU time 51.35 seconds
Started Jul 01 04:53:10 PM PDT 24
Finished Jul 01 04:54:03 PM PDT 24
Peak memory 248696 kb
Host smart-a644625d-4c1a-4206-aca7-447a9bc621eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1993352849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1993352849
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3205828166
Short name T138
Test name
Test status
Simulation time 5051950583 ps
CPU time 325.22 seconds
Started Jul 01 04:53:16 PM PDT 24
Finished Jul 01 04:58:43 PM PDT 24
Peak memory 265460 kb
Host smart-de637536-e65c-4691-b28b-c118b2123616
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3205828166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3205828166
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1715256734
Short name T767
Test name
Test status
Simulation time 271526200 ps
CPU time 8.85 seconds
Started Jul 01 04:53:12 PM PDT 24
Finished Jul 01 04:53:23 PM PDT 24
Peak memory 255120 kb
Host smart-2f6b6371-f28b-42d8-94a8-d37d73aaa477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1715256734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1715256734
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4110295498
Short name T817
Test name
Test status
Simulation time 34703595 ps
CPU time 4.78 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:53:20 PM PDT 24
Peak memory 239728 kb
Host smart-f42ab836-bfff-4f0d-b0ef-c172cec93425
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110295498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4110295498
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3306459542
Short name T762
Test name
Test status
Simulation time 92894645 ps
CPU time 5.52 seconds
Started Jul 01 04:53:14 PM PDT 24
Finished Jul 01 04:53:22 PM PDT 24
Peak memory 236616 kb
Host smart-050ba982-0c8d-4252-9b5a-f7a239d3d41d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3306459542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3306459542
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1102042552
Short name T826
Test name
Test status
Simulation time 6833215 ps
CPU time 1.44 seconds
Started Jul 01 04:53:12 PM PDT 24
Finished Jul 01 04:53:16 PM PDT 24
Peak memory 236636 kb
Host smart-4f76775d-2180-477e-8852-b188be0c2a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102042552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1102042552
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3652429333
Short name T756
Test name
Test status
Simulation time 411041588 ps
CPU time 14.77 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:45 PM PDT 24
Peak memory 245692 kb
Host smart-be8b26a3-2c6e-4182-8e59-fb146d47fa37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3652429333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3652429333
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2581696107
Short name T121
Test name
Test status
Simulation time 948040879 ps
CPU time 91.92 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:55:02 PM PDT 24
Peak memory 265348 kb
Host smart-f83c4d75-05a1-468c-b2d8-1e40151f5922
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2581696107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2581696107
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3783788534
Short name T805
Test name
Test status
Simulation time 216474381 ps
CPU time 7.89 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:53:24 PM PDT 24
Peak memory 251860 kb
Host smart-9093bdc0-326e-4766-b9c8-8a0b6d58dd39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3783788534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3783788534
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2493431102
Short name T784
Test name
Test status
Simulation time 2377540388 ps
CPU time 36.55 seconds
Started Jul 01 04:53:12 PM PDT 24
Finished Jul 01 04:53:51 PM PDT 24
Peak memory 240568 kb
Host smart-5c7211bf-a873-406c-8dd0-f764eb4c254e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2493431102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2493431102
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.751748763
Short name T776
Test name
Test status
Simulation time 104335635 ps
CPU time 7.58 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:53:23 PM PDT 24
Peak memory 256768 kb
Host smart-80afcf0c-94cf-4427-b52e-457478a01ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751748763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.751748763
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4120118797
Short name T802
Test name
Test status
Simulation time 21960613 ps
CPU time 3.57 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:53:19 PM PDT 24
Peak memory 240664 kb
Host smart-958db5e2-befa-430c-a666-82a6ff4a80f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4120118797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4120118797
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3260181967
Short name T361
Test name
Test status
Simulation time 8066834 ps
CPU time 1.52 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:14 PM PDT 24
Peak memory 235572 kb
Host smart-21bffa80-a2ec-4189-b76b-0ffccd1f2b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3260181967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3260181967
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3740482379
Short name T804
Test name
Test status
Simulation time 1171910487 ps
CPU time 25.17 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:38 PM PDT 24
Peak memory 248732 kb
Host smart-4c877f75-9cc8-4c49-bbba-016deaf1afd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3740482379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3740482379
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.554910531
Short name T146
Test name
Test status
Simulation time 8649892354 ps
CPU time 159.35 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:55:55 PM PDT 24
Peak memory 267568 kb
Host smart-e0c528c0-20c7-4f08-a29f-75114474a1f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=554910531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.554910531
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1217020780
Short name T142
Test name
Test status
Simulation time 51563642159 ps
CPU time 1027.84 seconds
Started Jul 01 04:53:12 PM PDT 24
Finished Jul 01 05:10:23 PM PDT 24
Peak memory 265420 kb
Host smart-e2e6a186-80b7-465b-90ed-dbc1025987e1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217020780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1217020780
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1655287045
Short name T747
Test name
Test status
Simulation time 701754014 ps
CPU time 28.14 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:59 PM PDT 24
Peak memory 248344 kb
Host smart-83bf5a8b-7a9b-472c-aed6-98f12769d9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1655287045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1655287045
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2614607701
Short name T176
Test name
Test status
Simulation time 228151022 ps
CPU time 8.87 seconds
Started Jul 01 04:53:15 PM PDT 24
Finished Jul 01 04:53:26 PM PDT 24
Peak memory 240572 kb
Host smart-35ec3328-3731-48a8-9e6d-dca91504ca2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614607701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2614607701
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3602771426
Short name T828
Test name
Test status
Simulation time 15112031 ps
CPU time 1.36 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:53:17 PM PDT 24
Peak memory 236628 kb
Host smart-9349a652-d8c8-43f6-ba90-cf06229bfc5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3602771426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3602771426
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.595050702
Short name T766
Test name
Test status
Simulation time 11270611094 ps
CPU time 39.84 seconds
Started Jul 01 04:53:13 PM PDT 24
Finished Jul 01 04:53:55 PM PDT 24
Peak memory 244760 kb
Host smart-23fd7d78-cce2-4081-9125-dbc6cd1d3d45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=595050702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.595050702
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3228754513
Short name T156
Test name
Test status
Simulation time 7688843805 ps
CPU time 143.37 seconds
Started Jul 01 04:53:10 PM PDT 24
Finished Jul 01 04:55:36 PM PDT 24
Peak memory 265444 kb
Host smart-2f61cabf-b291-4375-9ca9-76b0843b6255
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3228754513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3228754513
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.960055269
Short name T713
Test name
Test status
Simulation time 321838904 ps
CPU time 10.44 seconds
Started Jul 01 04:53:11 PM PDT 24
Finished Jul 01 04:53:23 PM PDT 24
Peak memory 248644 kb
Host smart-f80ff94a-e226-4555-a557-2ed794b3dbc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=960055269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.960055269
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3317141177
Short name T740
Test name
Test status
Simulation time 152236534 ps
CPU time 6.53 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:34 PM PDT 24
Peak memory 241016 kb
Host smart-b0b43c23-b199-4838-aa84-25ecb987b8b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317141177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3317141177
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2247142449
Short name T734
Test name
Test status
Simulation time 130042020 ps
CPU time 5.29 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:33 PM PDT 24
Peak memory 240444 kb
Host smart-5c35162e-a68e-47c0-aecc-aacd22546889
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2247142449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2247142449
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2715309628
Short name T779
Test name
Test status
Simulation time 8162587 ps
CPU time 1.52 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:29 PM PDT 24
Peak memory 237688 kb
Host smart-f6e62ba1-e96d-4d5e-babd-4f72096cd82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2715309628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2715309628
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3129778450
Short name T788
Test name
Test status
Simulation time 622244987 ps
CPU time 21.53 seconds
Started Jul 01 04:53:23 PM PDT 24
Finished Jul 01 04:53:48 PM PDT 24
Peak memory 244832 kb
Host smart-538a68d0-f510-4b17-99b0-68dbeaea3e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3129778450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3129778450
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3171095306
Short name T137
Test name
Test status
Simulation time 9725866238 ps
CPU time 174.68 seconds
Started Jul 01 04:53:16 PM PDT 24
Finished Jul 01 04:56:13 PM PDT 24
Peak memory 267820 kb
Host smart-fbbba03a-ab1a-42ef-944c-bd4aad933181
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3171095306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3171095306
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3266837006
Short name T125
Test name
Test status
Simulation time 30092137174 ps
CPU time 531.85 seconds
Started Jul 01 04:53:12 PM PDT 24
Finished Jul 01 05:02:06 PM PDT 24
Peak memory 265624 kb
Host smart-caf92dad-d2e0-48d5-9400-152d6c3d5bad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266837006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3266837006
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.222196776
Short name T825
Test name
Test status
Simulation time 140072569 ps
CPU time 10.79 seconds
Started Jul 01 04:53:25 PM PDT 24
Finished Jul 01 04:53:41 PM PDT 24
Peak memory 253076 kb
Host smart-51236af7-867b-4db5-93ee-a556eb4ee2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=222196776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.222196776
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3040420313
Short name T651
Test name
Test status
Simulation time 55303671394 ps
CPU time 1681.55 seconds
Started Jul 01 05:17:45 PM PDT 24
Finished Jul 01 05:45:52 PM PDT 24
Peak memory 284692 kb
Host smart-56bd02ba-e631-474f-91bd-81ba4346cd5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040420313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3040420313
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4218633773
Short name T579
Test name
Test status
Simulation time 275998938 ps
CPU time 15.67 seconds
Started Jul 01 05:17:41 PM PDT 24
Finished Jul 01 05:18:03 PM PDT 24
Peak memory 249236 kb
Host smart-8226effb-a04f-4d20-a31c-38a932c14ee7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4218633773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4218633773
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1016635863
Short name T647
Test name
Test status
Simulation time 2207247723 ps
CPU time 57.25 seconds
Started Jul 01 05:17:44 PM PDT 24
Finished Jul 01 05:18:47 PM PDT 24
Peak memory 257632 kb
Host smart-1febc00a-78b9-4653-b403-703a659e01d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
35863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1016635863
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1529131434
Short name T286
Test name
Test status
Simulation time 47153644841 ps
CPU time 1133.09 seconds
Started Jul 01 05:17:45 PM PDT 24
Finished Jul 01 05:36:43 PM PDT 24
Peak memory 273884 kb
Host smart-2111e06a-69e2-4920-b765-79a1fb0f830d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529131434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1529131434
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1515290839
Short name T599
Test name
Test status
Simulation time 141221102669 ps
CPU time 1973.77 seconds
Started Jul 01 05:17:45 PM PDT 24
Finished Jul 01 05:50:44 PM PDT 24
Peak memory 282968 kb
Host smart-8e8a711f-45a9-4edb-8acd-c669b9c99f33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515290839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1515290839
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2505357060
Short name T501
Test name
Test status
Simulation time 4345778993 ps
CPU time 96.82 seconds
Started Jul 01 05:17:43 PM PDT 24
Finished Jul 01 05:19:26 PM PDT 24
Peak memory 249344 kb
Host smart-a1f521bc-70f1-47b2-972e-4e5d873e11a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505357060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2505357060
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3347468093
Short name T427
Test name
Test status
Simulation time 407517400 ps
CPU time 29.51 seconds
Started Jul 01 05:17:45 PM PDT 24
Finished Jul 01 05:18:19 PM PDT 24
Peak memory 256640 kb
Host smart-1c5800d7-80e9-4a34-bfb3-e374a9d25bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33474
68093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3347468093
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4174424333
Short name T55
Test name
Test status
Simulation time 60725379 ps
CPU time 4.62 seconds
Started Jul 01 05:17:45 PM PDT 24
Finished Jul 01 05:17:55 PM PDT 24
Peak memory 241132 kb
Host smart-58fb1664-c9d2-4f8b-8139-b70a651dd88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
24333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4174424333
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2552598085
Short name T667
Test name
Test status
Simulation time 164250527 ps
CPU time 20.87 seconds
Started Jul 01 05:17:47 PM PDT 24
Finished Jul 01 05:18:12 PM PDT 24
Peak memory 256848 kb
Host smart-138040f6-cc45-4d37-9dcd-ab5bcc6361ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25525
98085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2552598085
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2665698429
Short name T197
Test name
Test status
Simulation time 583669124 ps
CPU time 14.73 seconds
Started Jul 01 05:17:45 PM PDT 24
Finished Jul 01 05:18:05 PM PDT 24
Peak memory 256532 kb
Host smart-b9f36f65-5f3b-4d5a-8a10-c4c740d6ded3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26656
98429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2665698429
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1596652325
Short name T61
Test name
Test status
Simulation time 12055566215 ps
CPU time 1198.17 seconds
Started Jul 01 05:17:43 PM PDT 24
Finished Jul 01 05:37:48 PM PDT 24
Peak memory 289928 kb
Host smart-704bd9a4-f352-4a34-88b0-12c4ded57b40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596652325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1596652325
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3897670210
Short name T431
Test name
Test status
Simulation time 52759119804 ps
CPU time 3204.28 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 06:11:19 PM PDT 24
Peak memory 290496 kb
Host smart-51f5d704-324b-4e71-8ab4-4f51dce02221
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897670210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3897670210
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.766370492
Short name T574
Test name
Test status
Simulation time 109425364 ps
CPU time 7.05 seconds
Started Jul 01 05:17:48 PM PDT 24
Finished Jul 01 05:18:00 PM PDT 24
Peak memory 249244 kb
Host smart-e225e736-b4c7-4947-bf66-cfbba357b2e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=766370492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.766370492
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1117117102
Short name T547
Test name
Test status
Simulation time 12720900497 ps
CPU time 186.7 seconds
Started Jul 01 05:17:52 PM PDT 24
Finished Jul 01 05:21:02 PM PDT 24
Peak memory 257184 kb
Host smart-4744c3d3-3357-4109-9122-8f6503c778f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
17102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1117117102
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3618191536
Short name T236
Test name
Test status
Simulation time 323123817 ps
CPU time 14.14 seconds
Started Jul 01 05:17:49 PM PDT 24
Finished Jul 01 05:18:07 PM PDT 24
Peak memory 257040 kb
Host smart-6b82488a-12ba-4c83-ba79-fb40cada868a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36181
91536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3618191536
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1152915508
Short name T351
Test name
Test status
Simulation time 9293497619 ps
CPU time 988.38 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:34:23 PM PDT 24
Peak memory 273420 kb
Host smart-67900c13-dc35-489e-bc16-075af6c33a1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152915508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1152915508
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2135345388
Short name T644
Test name
Test status
Simulation time 50699908828 ps
CPU time 3086.15 seconds
Started Jul 01 05:17:52 PM PDT 24
Finished Jul 01 06:09:22 PM PDT 24
Peak memory 290160 kb
Host smart-49196035-dc3a-4f1e-a711-c05c40d5ee99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135345388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2135345388
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1389665155
Short name T646
Test name
Test status
Simulation time 1920556205 ps
CPU time 55.53 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:18:50 PM PDT 24
Peak memory 256564 kb
Host smart-d04d7357-7526-4fde-ba46-fecf88dce9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13896
65155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1389665155
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2819132511
Short name T640
Test name
Test status
Simulation time 254239802 ps
CPU time 11.12 seconds
Started Jul 01 05:17:56 PM PDT 24
Finished Jul 01 05:18:09 PM PDT 24
Peak memory 248556 kb
Host smart-95d13a78-fd8d-4781-83fd-3772ad061159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28191
32511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2819132511
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.813235286
Short name T11
Test name
Test status
Simulation time 428934773 ps
CPU time 24.13 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 05:18:18 PM PDT 24
Peak memory 271680 kb
Host smart-7997a87a-8ace-4e67-abaa-7437b287b952
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=813235286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.813235286
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1307072920
Short name T544
Test name
Test status
Simulation time 1401490024 ps
CPU time 13.97 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 05:18:07 PM PDT 24
Peak memory 249344 kb
Host smart-cd0f5434-f803-4f63-a86d-12bdf126c43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
72920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1307072920
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1210013848
Short name T533
Test name
Test status
Simulation time 394035993 ps
CPU time 31.81 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 05:18:25 PM PDT 24
Peak memory 256760 kb
Host smart-7cf6bcaf-258b-4c4d-85a2-f07cdf26c284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12100
13848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1210013848
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2309477126
Short name T92
Test name
Test status
Simulation time 43497316874 ps
CPU time 2464.13 seconds
Started Jul 01 05:17:56 PM PDT 24
Finished Jul 01 05:59:03 PM PDT 24
Peak memory 290212 kb
Host smart-af3590dd-b8f5-4d12-9387-9b641721ebe8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309477126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2309477126
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.282040709
Short name T578
Test name
Test status
Simulation time 62612593194 ps
CPU time 1216.7 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:38:33 PM PDT 24
Peak memory 282936 kb
Host smart-cfef8f14-a65d-48b2-b25c-c7230af68a2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282040709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.282040709
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2921946165
Short name T36
Test name
Test status
Simulation time 287923105 ps
CPU time 14.09 seconds
Started Jul 01 05:18:14 PM PDT 24
Finished Jul 01 05:18:32 PM PDT 24
Peak memory 249340 kb
Host smart-9fc5d8a1-85f4-43de-a650-4ecd243c2e7f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2921946165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2921946165
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1965376897
Short name T299
Test name
Test status
Simulation time 571196296 ps
CPU time 43.1 seconds
Started Jul 01 05:18:10 PM PDT 24
Finished Jul 01 05:18:56 PM PDT 24
Peak memory 256668 kb
Host smart-ae3d1ae8-7a51-473a-bc6a-8ab9602ebc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19653
76897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1965376897
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4031645044
Short name T248
Test name
Test status
Simulation time 546025031 ps
CPU time 31.05 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:18:54 PM PDT 24
Peak memory 249324 kb
Host smart-91bf3fbd-1c42-407c-b795-11cc2ae29f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316
45044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4031645044
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1077844249
Short name T662
Test name
Test status
Simulation time 35907921082 ps
CPU time 2104.19 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:53:22 PM PDT 24
Peak memory 289416 kb
Host smart-b56357d5-287a-45c4-b357-4c3cdb695377
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077844249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1077844249
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4123341340
Short name T581
Test name
Test status
Simulation time 225253341478 ps
CPU time 3561.5 seconds
Started Jul 01 05:18:10 PM PDT 24
Finished Jul 01 06:17:35 PM PDT 24
Peak memory 290384 kb
Host smart-7b26fab0-9f94-4982-a52a-ef2621bfebea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123341340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4123341340
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1977722330
Short name T619
Test name
Test status
Simulation time 19369285807 ps
CPU time 411.54 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:25:06 PM PDT 24
Peak memory 256312 kb
Host smart-c9260dd6-57b3-4f17-9eec-f39f8662b92d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977722330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1977722330
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2063908072
Short name T661
Test name
Test status
Simulation time 595358307 ps
CPU time 13.96 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:18:31 PM PDT 24
Peak memory 256052 kb
Host smart-2e694c54-d27d-4522-9b9d-3c8bf14ace91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20639
08072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2063908072
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3458532238
Short name T45
Test name
Test status
Simulation time 1909208517 ps
CPU time 57.47 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:19:18 PM PDT 24
Peak memory 257424 kb
Host smart-6af39be4-18c1-47b6-97c2-81ea80c72a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
32238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3458532238
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1413087689
Short name T283
Test name
Test status
Simulation time 283378741 ps
CPU time 39.14 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:19:02 PM PDT 24
Peak memory 249064 kb
Host smart-23c69c40-e2cd-44cc-83cc-4a9e63b3150e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14130
87689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1413087689
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2544333859
Short name T196
Test name
Test status
Simulation time 279076054 ps
CPU time 26.64 seconds
Started Jul 01 05:18:14 PM PDT 24
Finished Jul 01 05:18:46 PM PDT 24
Peak memory 249200 kb
Host smart-e9c83531-f22f-47b1-98bf-4c379dfab3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25443
33859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2544333859
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.704119184
Short name T624
Test name
Test status
Simulation time 237280191483 ps
CPU time 1663.89 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:46:07 PM PDT 24
Peak memory 285400 kb
Host smart-8c2c8576-102b-4a6f-9552-75da1caec82a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704119184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.704119184
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3828363547
Short name T302
Test name
Test status
Simulation time 137805372370 ps
CPU time 1399.66 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:41:41 PM PDT 24
Peak memory 290040 kb
Host smart-1b6b565a-88a2-4bae-be85-6d7383694cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828363547 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3828363547
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1695773416
Short name T213
Test name
Test status
Simulation time 22073601 ps
CPU time 2.99 seconds
Started Jul 01 05:18:16 PM PDT 24
Finished Jul 01 05:18:24 PM PDT 24
Peak memory 249580 kb
Host smart-b3b06ea7-3da8-4484-9f41-abd7c4ff41a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1695773416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1695773416
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3022994185
Short name T235
Test name
Test status
Simulation time 23967424394 ps
CPU time 1264.7 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:39:22 PM PDT 24
Peak memory 273292 kb
Host smart-04c8cee6-2080-4ee7-be79-95e62a2980d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022994185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3022994185
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4064264033
Short name T649
Test name
Test status
Simulation time 642773266 ps
CPU time 9.61 seconds
Started Jul 01 05:18:14 PM PDT 24
Finished Jul 01 05:18:29 PM PDT 24
Peak memory 249232 kb
Host smart-fc383834-0373-41eb-9267-5957f17b1233
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4064264033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4064264033
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3845185091
Short name T398
Test name
Test status
Simulation time 747629606 ps
CPU time 23.17 seconds
Started Jul 01 05:18:15 PM PDT 24
Finished Jul 01 05:18:43 PM PDT 24
Peak memory 256940 kb
Host smart-e7aa3514-894f-46cf-9326-2e77c5082678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
85091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3845185091
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.820673644
Short name T674
Test name
Test status
Simulation time 940665036 ps
CPU time 43.2 seconds
Started Jul 01 05:18:14 PM PDT 24
Finished Jul 01 05:19:01 PM PDT 24
Peak memory 256836 kb
Host smart-e7b3bb0e-3fc6-44ff-9a3d-7dcdf65d8c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82067
3644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.820673644
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1895026630
Short name T245
Test name
Test status
Simulation time 7544351844 ps
CPU time 695.24 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:29:51 PM PDT 24
Peak memory 273140 kb
Host smart-c2d254c1-7175-47c7-a403-613c2ac0c500
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895026630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1895026630
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.652999093
Short name T636
Test name
Test status
Simulation time 21873469691 ps
CPU time 1197.98 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:38:13 PM PDT 24
Peak memory 287188 kb
Host smart-483ed154-10f9-44b4-85bb-f9a4be7f538e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652999093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.652999093
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2657760351
Short name T496
Test name
Test status
Simulation time 947127620 ps
CPU time 15.23 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:18:32 PM PDT 24
Peak memory 249320 kb
Host smart-28e6af0b-f57c-4a93-9be1-f6a344f8599b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577
60351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2657760351
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2997038093
Short name T690
Test name
Test status
Simulation time 235643248 ps
CPU time 7.43 seconds
Started Jul 01 05:18:10 PM PDT 24
Finished Jul 01 05:18:21 PM PDT 24
Peak memory 255472 kb
Host smart-89862f85-b8fa-4336-acdf-c936306a3f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29970
38093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2997038093
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.151245986
Short name T244
Test name
Test status
Simulation time 320740624 ps
CPU time 12.24 seconds
Started Jul 01 05:18:15 PM PDT 24
Finished Jul 01 05:18:32 PM PDT 24
Peak memory 249712 kb
Host smart-7cfd1372-5fef-42c2-8c31-e991b52105ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
5986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.151245986
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1698499446
Short name T205
Test name
Test status
Simulation time 27332008 ps
CPU time 2.43 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:18:24 PM PDT 24
Peak memory 249652 kb
Host smart-620a59b3-1d52-44a9-81e1-150a7e122489
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1698499446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1698499446
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4207833079
Short name T94
Test name
Test status
Simulation time 66322725966 ps
CPU time 1597.52 seconds
Started Jul 01 05:18:26 PM PDT 24
Finished Jul 01 05:45:06 PM PDT 24
Peak memory 273932 kb
Host smart-c99fb70c-826c-4096-85c6-07716a870259
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207833079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4207833079
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1913135553
Short name T120
Test name
Test status
Simulation time 10234635489 ps
CPU time 25.25 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:18:50 PM PDT 24
Peak memory 249344 kb
Host smart-25d13c34-0276-4072-8f0b-e28b26b42bd0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1913135553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1913135553
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.991149365
Short name T655
Test name
Test status
Simulation time 938380433 ps
CPU time 17.22 seconds
Started Jul 01 05:18:24 PM PDT 24
Finished Jul 01 05:18:44 PM PDT 24
Peak memory 256708 kb
Host smart-5d9a85f6-0aa8-4ca0-9013-e2deaa8f966f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99114
9365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.991149365
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4261698632
Short name T604
Test name
Test status
Simulation time 1308672174 ps
CPU time 53.17 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:19:16 PM PDT 24
Peak memory 256688 kb
Host smart-7eca57ec-9880-4a94-bee6-49ac11df4528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42616
98632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4261698632
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.274329628
Short name T621
Test name
Test status
Simulation time 87040773234 ps
CPU time 1623.63 seconds
Started Jul 01 05:18:26 PM PDT 24
Finished Jul 01 05:45:32 PM PDT 24
Peak memory 289752 kb
Host smart-af622e38-5233-4f73-a7df-7cb4da5b1e26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274329628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.274329628
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3849178297
Short name T677
Test name
Test status
Simulation time 63373876159 ps
CPU time 1774 seconds
Started Jul 01 05:18:20 PM PDT 24
Finished Jul 01 05:47:58 PM PDT 24
Peak memory 285032 kb
Host smart-8287eb5e-49f4-4dff-8b72-d41b6d0b2565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849178297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3849178297
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.749412740
Short name T185
Test name
Test status
Simulation time 15202517339 ps
CPU time 338.41 seconds
Started Jul 01 05:18:18 PM PDT 24
Finished Jul 01 05:24:01 PM PDT 24
Peak memory 249556 kb
Host smart-8bb3cf40-54ef-4c58-92e4-29f0248866ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749412740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.749412740
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1574392574
Short name T487
Test name
Test status
Simulation time 243677309 ps
CPU time 6.64 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:18:29 PM PDT 24
Peak memory 255024 kb
Host smart-e076410d-566d-476e-8044-15e5773e6b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15743
92574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1574392574
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2101769333
Short name T515
Test name
Test status
Simulation time 619515388 ps
CPU time 20.97 seconds
Started Jul 01 05:18:22 PM PDT 24
Finished Jul 01 05:18:47 PM PDT 24
Peak memory 255792 kb
Host smart-cf00505d-f8f5-4d33-925f-851c69c22f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21017
69333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2101769333
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1651793391
Short name T52
Test name
Test status
Simulation time 79633613 ps
CPU time 4.58 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:18:29 PM PDT 24
Peak memory 241076 kb
Host smart-c00b571c-129c-409f-8d9a-5199e034a316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
93391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1651793391
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.352815546
Short name T447
Test name
Test status
Simulation time 385648151 ps
CPU time 17.84 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:18:39 PM PDT 24
Peak memory 249316 kb
Host smart-dc3878f2-a499-47f0-b7d0-926cbb8bbfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281
5546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.352815546
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.774744096
Short name T116
Test name
Test status
Simulation time 5547351704 ps
CPU time 174.47 seconds
Started Jul 01 05:18:20 PM PDT 24
Finished Jul 01 05:21:18 PM PDT 24
Peak memory 257620 kb
Host smart-d4ed918a-bbbd-49d0-8af8-4fb8c8ac66db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774744096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.774744096
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2784751776
Short name T189
Test name
Test status
Simulation time 283467316900 ps
CPU time 8420.44 seconds
Started Jul 01 05:18:20 PM PDT 24
Finished Jul 01 07:38:45 PM PDT 24
Peak memory 370264 kb
Host smart-ee49d1ce-ed73-4362-bfca-42e898d82f23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784751776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2784751776
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2873945386
Short name T211
Test name
Test status
Simulation time 104792476 ps
CPU time 3.1 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:18:28 PM PDT 24
Peak memory 249612 kb
Host smart-276cc940-8a8b-434c-8370-5790ceb87fe0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2873945386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2873945386
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1124137513
Short name T670
Test name
Test status
Simulation time 85558929463 ps
CPU time 519.51 seconds
Started Jul 01 05:18:18 PM PDT 24
Finished Jul 01 05:27:01 PM PDT 24
Peak memory 273456 kb
Host smart-b27ea866-83dc-4712-a880-5b3fc55a3fc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124137513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1124137513
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1527155406
Short name T183
Test name
Test status
Simulation time 714823862 ps
CPU time 20.51 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:18:45 PM PDT 24
Peak memory 249300 kb
Host smart-874c9119-9e34-4d63-9ddc-b178fe3d88e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1527155406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1527155406
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3220545137
Short name T598
Test name
Test status
Simulation time 3056386425 ps
CPU time 171.17 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:21:14 PM PDT 24
Peak memory 257112 kb
Host smart-a89e1c2f-626e-4036-a9a3-b688aa3e9008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32205
45137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3220545137
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3128470831
Short name T412
Test name
Test status
Simulation time 231028240 ps
CPU time 17.7 seconds
Started Jul 01 05:18:18 PM PDT 24
Finished Jul 01 05:18:40 PM PDT 24
Peak memory 249712 kb
Host smart-383da947-82e0-4bc9-887f-6b91eb73d57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
70831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3128470831
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3640247299
Short name T408
Test name
Test status
Simulation time 11592721654 ps
CPU time 791.11 seconds
Started Jul 01 05:18:20 PM PDT 24
Finished Jul 01 05:31:36 PM PDT 24
Peak memory 273992 kb
Host smart-2d7b0e13-01a7-4c6a-bdaa-aec281f77430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640247299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3640247299
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2704360362
Short name T612
Test name
Test status
Simulation time 139237629 ps
CPU time 5.69 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 05:18:34 PM PDT 24
Peak memory 249332 kb
Host smart-9dba9389-3d4d-4cd0-bf20-670cae9921e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27043
60362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2704360362
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.900309082
Short name T664
Test name
Test status
Simulation time 245316084 ps
CPU time 5.13 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:18:28 PM PDT 24
Peak memory 240468 kb
Host smart-70efe2c5-c7a8-492d-9dff-15a5de02c555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90030
9082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.900309082
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4142746069
Short name T548
Test name
Test status
Simulation time 1115903235 ps
CPU time 36.23 seconds
Started Jul 01 05:18:18 PM PDT 24
Finished Jul 01 05:18:59 PM PDT 24
Peak memory 256940 kb
Host smart-4e442fb8-cfa9-490b-9336-104bff7b8885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41427
46069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4142746069
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2955672443
Short name T188
Test name
Test status
Simulation time 675892538 ps
CPU time 38.77 seconds
Started Jul 01 05:18:16 PM PDT 24
Finished Jul 01 05:18:59 PM PDT 24
Peak memory 256564 kb
Host smart-396223db-acfd-4e79-8722-17d3b9820ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
72443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2955672443
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3788719110
Short name T43
Test name
Test status
Simulation time 17196788784 ps
CPU time 1406.36 seconds
Started Jul 01 05:18:25 PM PDT 24
Finished Jul 01 05:41:54 PM PDT 24
Peak memory 282256 kb
Host smart-5622b5ee-2e5b-4559-889c-99f5af372bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788719110 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3788719110
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3091832479
Short name T648
Test name
Test status
Simulation time 8430831352 ps
CPU time 945.82 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:34:11 PM PDT 24
Peak memory 282164 kb
Host smart-3c04181f-ae0b-43a9-af79-e3c171a5eb24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091832479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3091832479
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2709395104
Short name T37
Test name
Test status
Simulation time 373719327 ps
CPU time 7.61 seconds
Started Jul 01 05:18:22 PM PDT 24
Finished Jul 01 05:18:33 PM PDT 24
Peak memory 249308 kb
Host smart-df85c9c8-77f8-4ca5-a188-ef3ca85695ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2709395104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2709395104
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.115552323
Short name T567
Test name
Test status
Simulation time 399668216 ps
CPU time 9.36 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:18:34 PM PDT 24
Peak memory 255276 kb
Host smart-8405476d-f826-4861-8940-112022336c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11555
2323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.115552323
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.4115489717
Short name T704
Test name
Test status
Simulation time 1497493388 ps
CPU time 47.14 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:19:09 PM PDT 24
Peak memory 249316 kb
Host smart-2750e120-7899-41af-93a9-06b55c55a108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
89717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.4115489717
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1166519678
Short name T358
Test name
Test status
Simulation time 35005941904 ps
CPU time 2135.58 seconds
Started Jul 01 05:18:25 PM PDT 24
Finished Jul 01 05:54:03 PM PDT 24
Peak memory 273376 kb
Host smart-7b2f6686-94c8-4972-95a7-510d57bc633f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166519678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1166519678
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3260281581
Short name T634
Test name
Test status
Simulation time 49077390570 ps
CPU time 1515.8 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:43:41 PM PDT 24
Peak memory 273760 kb
Host smart-62f9f300-21e3-432d-a001-bcb65bd3c02d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260281581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3260281581
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.602564951
Short name T573
Test name
Test status
Simulation time 5756010737 ps
CPU time 121.06 seconds
Started Jul 01 05:18:18 PM PDT 24
Finished Jul 01 05:20:23 PM PDT 24
Peak memory 255684 kb
Host smart-23f6db45-a755-48f2-9613-7c7fc1f84f19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602564951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.602564951
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.281093087
Short name T402
Test name
Test status
Simulation time 314643460 ps
CPU time 21.62 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:18:45 PM PDT 24
Peak memory 256536 kb
Host smart-9d37c757-db60-4b23-b879-469191567bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28109
3087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.281093087
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.213507266
Short name T68
Test name
Test status
Simulation time 1761048512 ps
CPU time 33.16 seconds
Started Jul 01 05:18:22 PM PDT 24
Finished Jul 01 05:18:59 PM PDT 24
Peak memory 249400 kb
Host smart-785656b8-49ba-4f94-a912-8ae57408d89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
7266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.213507266
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1615047317
Short name T629
Test name
Test status
Simulation time 781761271 ps
CPU time 55.77 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 05:19:25 PM PDT 24
Peak memory 256636 kb
Host smart-bc5170a2-90a3-4467-abab-2da45900c90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16150
47317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1615047317
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3453482437
Short name T444
Test name
Test status
Simulation time 1382768600 ps
CPU time 27.43 seconds
Started Jul 01 05:18:23 PM PDT 24
Finished Jul 01 05:18:53 PM PDT 24
Peak memory 257240 kb
Host smart-917f5744-a6a0-47a9-a435-63aa67aa4c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34534
82437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3453482437
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.23772340
Short name T290
Test name
Test status
Simulation time 82107443053 ps
CPU time 1724.59 seconds
Started Jul 01 05:18:22 PM PDT 24
Finished Jul 01 05:47:11 PM PDT 24
Peak memory 306816 kb
Host smart-f945417d-f324-41c0-a678-8972a9923198
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23772340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_hand
ler_stress_all.23772340
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2795362427
Short name T38
Test name
Test status
Simulation time 26517020611 ps
CPU time 2246.51 seconds
Started Jul 01 05:18:21 PM PDT 24
Finished Jul 01 05:55:52 PM PDT 24
Peak memory 306820 kb
Host smart-e1c4cee8-8211-4afe-b06c-9731fb314b51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795362427 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2795362427
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3582684853
Short name T209
Test name
Test status
Simulation time 30183350 ps
CPU time 2.87 seconds
Started Jul 01 05:18:28 PM PDT 24
Finished Jul 01 05:18:34 PM PDT 24
Peak memory 249632 kb
Host smart-fe363756-d7e3-4cae-b487-07f4d2f299e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3582684853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3582684853
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.842554018
Short name T564
Test name
Test status
Simulation time 173287520625 ps
CPU time 2105.7 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:53:39 PM PDT 24
Peak memory 282256 kb
Host smart-8992bef4-51f5-47de-bbcc-3a25a8797324
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842554018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.842554018
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.766230677
Short name T522
Test name
Test status
Simulation time 3242694984 ps
CPU time 38.28 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:19:11 PM PDT 24
Peak memory 249364 kb
Host smart-e45d0558-23e0-4971-b913-80f1bd43e39f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=766230677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.766230677
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3729341623
Short name T264
Test name
Test status
Simulation time 2999385758 ps
CPU time 156.96 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 05:21:06 PM PDT 24
Peak memory 257708 kb
Host smart-7292459b-a89d-4880-9827-34db5e90c689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37293
41623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3729341623
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1697243311
Short name T467
Test name
Test status
Simulation time 122756797 ps
CPU time 10.75 seconds
Started Jul 01 05:18:23 PM PDT 24
Finished Jul 01 05:18:37 PM PDT 24
Peak memory 248360 kb
Host smart-47b4a1d1-99a6-471d-970d-29740dd9bd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16972
43311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1697243311
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1221379817
Short name T310
Test name
Test status
Simulation time 115849632782 ps
CPU time 1863.1 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:49:49 PM PDT 24
Peak memory 273996 kb
Host smart-7331c798-8a0f-4cb6-9550-ade8ad7710ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221379817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1221379817
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2721590954
Short name T554
Test name
Test status
Simulation time 58094199659 ps
CPU time 1910.87 seconds
Started Jul 01 05:18:30 PM PDT 24
Finished Jul 01 05:50:25 PM PDT 24
Peak memory 273868 kb
Host smart-ba5d118b-4830-4dce-80ac-bde424fd0498
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721590954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2721590954
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3700197902
Short name T335
Test name
Test status
Simulation time 7383890355 ps
CPU time 308.37 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:23:55 PM PDT 24
Peak memory 249420 kb
Host smart-53a14ac0-a7a0-4f57-b980-9348a3de3743
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700197902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3700197902
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3832184720
Short name T436
Test name
Test status
Simulation time 194602136 ps
CPU time 17.84 seconds
Started Jul 01 05:18:26 PM PDT 24
Finished Jul 01 05:18:46 PM PDT 24
Peak memory 256616 kb
Host smart-b435b287-68ac-4c6f-b102-20fc691577de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38321
84720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3832184720
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3071158469
Short name T575
Test name
Test status
Simulation time 8739818969 ps
CPU time 38.18 seconds
Started Jul 01 05:18:26 PM PDT 24
Finished Jul 01 05:19:06 PM PDT 24
Peak memory 250124 kb
Host smart-73d77028-9560-4820-8ecf-eea139895daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30711
58469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3071158469
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2186155676
Short name T251
Test name
Test status
Simulation time 1027897887 ps
CPU time 69.39 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:19:56 PM PDT 24
Peak memory 257056 kb
Host smart-d169f891-c5b7-4fea-a06e-e706cea1dba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21861
55676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2186155676
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1720274097
Short name T438
Test name
Test status
Simulation time 47717247 ps
CPU time 5.28 seconds
Started Jul 01 05:18:20 PM PDT 24
Finished Jul 01 05:18:29 PM PDT 24
Peak memory 252468 kb
Host smart-0d34576c-a197-4479-a431-3724e64f6ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17202
74097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1720274097
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3417539379
Short name T107
Test name
Test status
Simulation time 109073714095 ps
CPU time 2343.7 seconds
Started Jul 01 05:18:28 PM PDT 24
Finished Jul 01 05:57:35 PM PDT 24
Peak memory 284272 kb
Host smart-4c2212be-9e3c-41aa-880b-38467bb0f650
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417539379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3417539379
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2978097152
Short name T255
Test name
Test status
Simulation time 29846952428 ps
CPU time 494.77 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 268924 kb
Host smart-de0caf73-b1cb-43f3-914b-58249a17fc69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978097152 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2978097152
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3322048671
Short name T206
Test name
Test status
Simulation time 20252636 ps
CPU time 2.65 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:18:43 PM PDT 24
Peak memory 249584 kb
Host smart-284a1634-cd01-43ef-92a8-1428b3280056
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3322048671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3322048671
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3076705032
Short name T432
Test name
Test status
Simulation time 30310082977 ps
CPU time 1752.65 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:47:59 PM PDT 24
Peak memory 281512 kb
Host smart-6f439849-0c72-4fee-a38a-c1d4dbebd19c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076705032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3076705032
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1263397687
Short name T393
Test name
Test status
Simulation time 332266016 ps
CPU time 9.98 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:18:43 PM PDT 24
Peak memory 249344 kb
Host smart-0a145322-7702-4ff2-91d6-9acee6983551
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1263397687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1263397687
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3388293201
Short name T35
Test name
Test status
Simulation time 433673076 ps
CPU time 9.66 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:18:43 PM PDT 24
Peak memory 254216 kb
Host smart-e5995bf7-0428-44e1-bc54-afae2d357e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33882
93201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3388293201
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.642766547
Short name T518
Test name
Test status
Simulation time 3013058308 ps
CPU time 14.84 seconds
Started Jul 01 05:18:28 PM PDT 24
Finished Jul 01 05:18:46 PM PDT 24
Peak memory 249508 kb
Host smart-7ddfa0bc-b41c-4204-a7fe-c8b1db75c115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64276
6547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.642766547
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.670060973
Short name T614
Test name
Test status
Simulation time 100452173087 ps
CPU time 1660.62 seconds
Started Jul 01 05:18:28 PM PDT 24
Finished Jul 01 05:46:11 PM PDT 24
Peak memory 272948 kb
Host smart-b96a198a-aea4-47fa-b2d1-09fcabe575a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670060973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.670060973
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.714624238
Short name T489
Test name
Test status
Simulation time 177620472120 ps
CPU time 2505.77 seconds
Started Jul 01 05:18:30 PM PDT 24
Finished Jul 01 06:00:20 PM PDT 24
Peak memory 284008 kb
Host smart-39fa190f-f3f5-4ffc-88a3-3e9c95316058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714624238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.714624238
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3543688573
Short name T338
Test name
Test status
Simulation time 7585124882 ps
CPU time 320.4 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:24:02 PM PDT 24
Peak memory 249420 kb
Host smart-5ae28ed8-05f8-4964-8849-6094f9a0bfce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543688573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3543688573
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2872322419
Short name T503
Test name
Test status
Simulation time 560611441 ps
CPU time 35.33 seconds
Started Jul 01 05:18:30 PM PDT 24
Finished Jul 01 05:19:09 PM PDT 24
Peak memory 249364 kb
Host smart-a7297faf-8e99-40ce-87ec-def5a98cd5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28723
22419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2872322419
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3814481329
Short name T478
Test name
Test status
Simulation time 843525532 ps
CPU time 21.37 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 05:18:51 PM PDT 24
Peak memory 257260 kb
Host smart-fbba92bd-26cc-40d1-990c-9a76a5854c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
81329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3814481329
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2404312628
Short name T85
Test name
Test status
Simulation time 531125966 ps
CPU time 38.6 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:19:21 PM PDT 24
Peak memory 249396 kb
Host smart-912c9a1f-801f-4317-8935-86c59aece1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043
12628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2404312628
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3582477874
Short name T697
Test name
Test status
Simulation time 614966332 ps
CPU time 32.79 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:19:19 PM PDT 24
Peak memory 257120 kb
Host smart-18cccb5d-5351-4e92-aa6e-fff092fe5da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35824
77874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3582477874
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2599156012
Short name T246
Test name
Test status
Simulation time 168400899526 ps
CPU time 1197.49 seconds
Started Jul 01 05:18:34 PM PDT 24
Finished Jul 01 05:38:34 PM PDT 24
Peak memory 289784 kb
Host smart-76e4a30e-2b8a-46c0-bdd8-4fcfe7c5e544
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599156012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2599156012
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1281912776
Short name T221
Test name
Test status
Simulation time 45943664 ps
CPU time 4.02 seconds
Started Jul 01 05:18:36 PM PDT 24
Finished Jul 01 05:18:43 PM PDT 24
Peak memory 249564 kb
Host smart-ea34ec4b-022e-43ce-8a0e-a47807e15a42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1281912776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1281912776
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.706096065
Short name T294
Test name
Test status
Simulation time 41348257503 ps
CPU time 2396.26 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:58:39 PM PDT 24
Peak memory 290160 kb
Host smart-05aac9fc-2895-4564-8e5b-f1d729bb891d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706096065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.706096065
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1348160986
Short name T69
Test name
Test status
Simulation time 772848830 ps
CPU time 10.95 seconds
Started Jul 01 05:18:30 PM PDT 24
Finished Jul 01 05:18:44 PM PDT 24
Peak memory 249228 kb
Host smart-b844f725-6a9a-4141-ac80-07776b243b45
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1348160986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1348160986
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2304122006
Short name T458
Test name
Test status
Simulation time 1807841502 ps
CPU time 113.61 seconds
Started Jul 01 05:18:30 PM PDT 24
Finished Jul 01 05:20:27 PM PDT 24
Peak memory 257036 kb
Host smart-58ac0268-6adf-48ec-b698-197c338acae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23041
22006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2304122006
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.206691418
Short name T17
Test name
Test status
Simulation time 46501155 ps
CPU time 5.28 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 05:18:35 PM PDT 24
Peak memory 248844 kb
Host smart-586c9431-1af6-450b-9778-d629110358af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20669
1418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.206691418
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1996464612
Short name T508
Test name
Test status
Simulation time 19899249959 ps
CPU time 1367.61 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:41:32 PM PDT 24
Peak memory 290156 kb
Host smart-b5f6ce68-8887-4585-a4fb-914a546eea4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996464612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1996464612
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2939036005
Short name T311
Test name
Test status
Simulation time 14929943267 ps
CPU time 515.69 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 05:27:05 PM PDT 24
Peak memory 248380 kb
Host smart-604de2c4-a26d-4825-a606-a97b67c76136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939036005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2939036005
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.136764023
Short name T377
Test name
Test status
Simulation time 228820197 ps
CPU time 17.03 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:18:51 PM PDT 24
Peak memory 256760 kb
Host smart-4c4a362f-2ebb-429c-8943-b8630f3091d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13676
4023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.136764023
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2827819549
Short name T493
Test name
Test status
Simulation time 485733983 ps
CPU time 7.37 seconds
Started Jul 01 05:18:31 PM PDT 24
Finished Jul 01 05:18:42 PM PDT 24
Peak memory 251744 kb
Host smart-99d0864b-9bd1-4db6-a62b-422e17cc0578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28278
19549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2827819549
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2780362080
Short name T280
Test name
Test status
Simulation time 233661718 ps
CPU time 26.81 seconds
Started Jul 01 05:18:30 PM PDT 24
Finished Jul 01 05:19:01 PM PDT 24
Peak memory 248700 kb
Host smart-1da79d9b-7812-4dd8-8346-4bd28aa96afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27803
62080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2780362080
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3616155486
Short name T466
Test name
Test status
Simulation time 207585711 ps
CPU time 11.12 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:18:58 PM PDT 24
Peak memory 255780 kb
Host smart-1d8736e2-44dc-4465-b73f-2f58b075575f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161
55486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3616155486
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2451909192
Short name T582
Test name
Test status
Simulation time 174701688424 ps
CPU time 3264.7 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 06:12:54 PM PDT 24
Peak memory 305900 kb
Host smart-67f25774-41b8-4a91-b259-d800882d225a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451909192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2451909192
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3464838268
Short name T208
Test name
Test status
Simulation time 118584914 ps
CPU time 2.73 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:18:45 PM PDT 24
Peak memory 249600 kb
Host smart-3179be37-e462-4c96-8fc2-68288222126d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3464838268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3464838268
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1256312647
Short name T446
Test name
Test status
Simulation time 35889200574 ps
CPU time 824.82 seconds
Started Jul 01 05:18:31 PM PDT 24
Finished Jul 01 05:32:19 PM PDT 24
Peak memory 273956 kb
Host smart-795be2d8-0738-430b-a07d-2460a4c639f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256312647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1256312647
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3967759736
Short name T238
Test name
Test status
Simulation time 378248518 ps
CPU time 7.73 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:18:48 PM PDT 24
Peak memory 249192 kb
Host smart-0698a4b8-f95f-4c0c-94cc-61bc8576cd76
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3967759736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3967759736
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1715313320
Short name T633
Test name
Test status
Simulation time 12115879335 ps
CPU time 347.07 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:24:29 PM PDT 24
Peak memory 257564 kb
Host smart-38f8ebea-5b7d-4db0-8bc5-90b917ea782e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17153
13320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1715313320
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.237154308
Short name T404
Test name
Test status
Simulation time 264113914 ps
CPU time 7.29 seconds
Started Jul 01 05:18:28 PM PDT 24
Finished Jul 01 05:18:38 PM PDT 24
Peak memory 249332 kb
Host smart-1d17c7bc-7d30-4fe0-a90d-184bae2b6332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23715
4308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.237154308
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.913001667
Short name T566
Test name
Test status
Simulation time 9993607948 ps
CPU time 828.54 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:32:32 PM PDT 24
Peak memory 273572 kb
Host smart-b21ebb88-0a49-4e77-85c3-6312cbcee19a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913001667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.913001667
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2877029936
Short name T676
Test name
Test status
Simulation time 52428801626 ps
CPU time 3212.48 seconds
Started Jul 01 05:18:27 PM PDT 24
Finished Jul 01 06:12:02 PM PDT 24
Peak memory 290152 kb
Host smart-3b870e38-535c-4ffe-abc4-af64445f4075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877029936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2877029936
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3947138653
Short name T596
Test name
Test status
Simulation time 26918805294 ps
CPU time 301.12 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:23:34 PM PDT 24
Peak memory 249416 kb
Host smart-11f388ea-b634-4263-9d10-d39dfa7d0527
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947138653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3947138653
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.867909382
Short name T374
Test name
Test status
Simulation time 698116368 ps
CPU time 44.42 seconds
Started Jul 01 05:18:31 PM PDT 24
Finished Jul 01 05:19:19 PM PDT 24
Peak memory 256676 kb
Host smart-9981792c-a710-4c7b-87be-f0c7cbca8d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86790
9382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.867909382
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3886502312
Short name T74
Test name
Test status
Simulation time 609391841 ps
CPU time 36.18 seconds
Started Jul 01 05:18:29 PM PDT 24
Finished Jul 01 05:19:09 PM PDT 24
Peak memory 249316 kb
Host smart-ae6756d9-fce6-4f64-b802-b8b35151145d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38865
02312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3886502312
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2683634154
Short name T272
Test name
Test status
Simulation time 2435718146 ps
CPU time 45.31 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:19:32 PM PDT 24
Peak memory 257196 kb
Host smart-f9f73d14-4c48-4f63-a527-8a0825338e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836
34154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2683634154
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3127223854
Short name T572
Test name
Test status
Simulation time 78286268 ps
CPU time 6.93 seconds
Started Jul 01 05:18:31 PM PDT 24
Finished Jul 01 05:18:41 PM PDT 24
Peak memory 249296 kb
Host smart-f974e059-ca8e-413e-b573-01c1ad681b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31272
23854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3127223854
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1895262669
Short name T228
Test name
Test status
Simulation time 80613421448 ps
CPU time 2014.83 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:52:21 PM PDT 24
Peak memory 305900 kb
Host smart-3568d5f1-5886-4747-aea4-642430586977
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895262669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1895262669
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1793185620
Short name T210
Test name
Test status
Simulation time 13992995 ps
CPU time 2.72 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:18:48 PM PDT 24
Peak memory 249548 kb
Host smart-d37407d1-9cad-4fbb-8ecc-2dc11d58d199
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1793185620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1793185620
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3946831982
Short name T459
Test name
Test status
Simulation time 14815790440 ps
CPU time 1465.54 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:43:08 PM PDT 24
Peak memory 289456 kb
Host smart-7c1cbc70-897f-4e87-a285-f2a640412cb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946831982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3946831982
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1727408923
Short name T708
Test name
Test status
Simulation time 357335597 ps
CPU time 9.77 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:18:55 PM PDT 24
Peak memory 249364 kb
Host smart-c47c14c5-8fdc-40db-a246-d2cd55d2dc68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1727408923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1727408923
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1401086465
Short name T682
Test name
Test status
Simulation time 15448764357 ps
CPU time 316.11 seconds
Started Jul 01 05:18:42 PM PDT 24
Finished Jul 01 05:24:05 PM PDT 24
Peak memory 257084 kb
Host smart-13d4bde5-7f53-46ea-bc16-5d6d0bb0d0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14010
86465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1401086465
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2349547865
Short name T81
Test name
Test status
Simulation time 1709209144 ps
CPU time 55.33 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:19:47 PM PDT 24
Peak memory 248504 kb
Host smart-810032dd-a6eb-4ad8-8e65-7d7cfb3b2730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23495
47865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2349547865
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1659332694
Short name T529
Test name
Test status
Simulation time 127219178688 ps
CPU time 1712.76 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:47:23 PM PDT 24
Peak memory 274000 kb
Host smart-5c5cccbc-8db2-42e8-b88f-0db528c6cdc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659332694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1659332694
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4116398951
Short name T465
Test name
Test status
Simulation time 159794640648 ps
CPU time 2445.2 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:59:30 PM PDT 24
Peak memory 284396 kb
Host smart-338e8a15-bc58-40b7-ba65-c88baa71a426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116398951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4116398951
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3035065154
Short name T315
Test name
Test status
Simulation time 15713624512 ps
CPU time 175.76 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:21:40 PM PDT 24
Peak memory 249400 kb
Host smart-e3732a71-dae3-4333-aca2-9410a78c2b65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035065154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3035065154
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4180036339
Short name T437
Test name
Test status
Simulation time 1025147960 ps
CPU time 33.95 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:19:19 PM PDT 24
Peak memory 256880 kb
Host smart-41b3f48e-b15f-432d-8815-93d305abcc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41800
36339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4180036339
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2817734866
Short name T187
Test name
Test status
Simulation time 1894975238 ps
CPU time 25.12 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:19:10 PM PDT 24
Peak memory 257468 kb
Host smart-1ea3a482-18a8-4b21-98c3-6fbd645ac197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28177
34866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2817734866
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3825450026
Short name T546
Test name
Test status
Simulation time 695558855 ps
CPU time 20.33 seconds
Started Jul 01 05:18:42 PM PDT 24
Finished Jul 01 05:19:09 PM PDT 24
Peak memory 257404 kb
Host smart-9d9ef607-236a-4545-8f87-06906778081f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38254
50026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3825450026
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.613739497
Short name T386
Test name
Test status
Simulation time 250817486 ps
CPU time 20.21 seconds
Started Jul 01 05:18:41 PM PDT 24
Finished Jul 01 05:19:08 PM PDT 24
Peak memory 256580 kb
Host smart-7d91116c-4d35-410b-ad51-d475016d6318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61373
9497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.613739497
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.849635764
Short name T550
Test name
Test status
Simulation time 77513342831 ps
CPU time 1615.6 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:45:42 PM PDT 24
Peak memory 306392 kb
Host smart-2d849ef1-cfea-442c-b5c3-f9b88363027b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849635764 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.849635764
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1123255589
Short name T214
Test name
Test status
Simulation time 15906583 ps
CPU time 2.63 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:17:57 PM PDT 24
Peak memory 249676 kb
Host smart-3ae1f51a-67b5-4717-992e-e4b775cc2a3e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1123255589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1123255589
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2658544198
Short name T448
Test name
Test status
Simulation time 14894747712 ps
CPU time 700.92 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:29:35 PM PDT 24
Peak memory 273448 kb
Host smart-196988a5-3c01-4c95-8b23-b33f35546c10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658544198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2658544198
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1794482055
Short name T500
Test name
Test status
Simulation time 883423785 ps
CPU time 13.37 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:18:08 PM PDT 24
Peak memory 249292 kb
Host smart-ac957153-4e67-4744-bf9b-d5837d81f90c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1794482055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1794482055
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3307184224
Short name T538
Test name
Test status
Simulation time 2472547844 ps
CPU time 56.71 seconds
Started Jul 01 05:17:52 PM PDT 24
Finished Jul 01 05:18:52 PM PDT 24
Peak memory 257264 kb
Host smart-fd245897-d0ee-421f-8153-9a22918bd32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
84224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3307184224
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1050166231
Short name T111
Test name
Test status
Simulation time 589505649 ps
CPU time 39.04 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 05:18:33 PM PDT 24
Peak memory 256904 kb
Host smart-b68191fa-5cb3-4491-8001-e900bbc19244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10501
66231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1050166231
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1382491284
Short name T333
Test name
Test status
Simulation time 28649151055 ps
CPU time 1749.83 seconds
Started Jul 01 05:17:53 PM PDT 24
Finished Jul 01 05:47:06 PM PDT 24
Peak memory 273324 kb
Host smart-2a172087-69c9-4f18-a37d-21bd6b07248c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382491284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1382491284
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4223674938
Short name T389
Test name
Test status
Simulation time 12784979099 ps
CPU time 1051.75 seconds
Started Jul 01 05:17:52 PM PDT 24
Finished Jul 01 05:35:27 PM PDT 24
Peak memory 273964 kb
Host smart-05aaca7a-0081-48e8-a3ed-c3a156da55df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223674938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4223674938
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2169554603
Short name T330
Test name
Test status
Simulation time 21420458499 ps
CPU time 160.66 seconds
Started Jul 01 05:17:52 PM PDT 24
Finished Jul 01 05:20:36 PM PDT 24
Peak memory 249504 kb
Host smart-6e3af118-796d-4737-8a7b-9e04e9cc6553
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169554603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2169554603
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3071842762
Short name T526
Test name
Test status
Simulation time 2878177429 ps
CPU time 33.43 seconds
Started Jul 01 05:17:49 PM PDT 24
Finished Jul 01 05:18:26 PM PDT 24
Peak memory 256744 kb
Host smart-10725c6f-fc70-44ce-9021-a252a2eb9cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30718
42762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3071842762
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1086515606
Short name T519
Test name
Test status
Simulation time 430322638 ps
CPU time 37.16 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:18:31 PM PDT 24
Peak memory 250340 kb
Host smart-a5fe49c8-b732-4236-a7b0-0ce6ed53c4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10865
15606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1086515606
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2003420845
Short name T10
Test name
Test status
Simulation time 842837043 ps
CPU time 11.31 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:18:06 PM PDT 24
Peak memory 276600 kb
Host smart-f5efc8dd-f714-4927-b50e-d0eb1d1c44ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2003420845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2003420845
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.513739382
Short name T222
Test name
Test status
Simulation time 85350890 ps
CPU time 4.27 seconds
Started Jul 01 05:17:51 PM PDT 24
Finished Jul 01 05:17:59 PM PDT 24
Peak memory 241124 kb
Host smart-bcd99776-482c-434b-89d9-50087e6088d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51373
9382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.513739382
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.835206241
Short name T231
Test name
Test status
Simulation time 16132978 ps
CPU time 2.71 seconds
Started Jul 01 05:17:56 PM PDT 24
Finished Jul 01 05:18:01 PM PDT 24
Peak memory 251408 kb
Host smart-f2030bec-afd2-4e85-a778-bb386e99c672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83520
6241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.835206241
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2986212383
Short name T89
Test name
Test status
Simulation time 51717135185 ps
CPU time 3344.03 seconds
Started Jul 01 05:17:49 PM PDT 24
Finished Jul 01 06:13:38 PM PDT 24
Peak memory 304484 kb
Host smart-5ab263c6-607b-4472-89c2-5ecc912fd3a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986212383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2986212383
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.757339801
Short name T254
Test name
Test status
Simulation time 263357795214 ps
CPU time 3427.5 seconds
Started Jul 01 05:17:49 PM PDT 24
Finished Jul 01 06:15:00 PM PDT 24
Peak memory 290600 kb
Host smart-54185024-1c02-4f3b-b096-3854e8a077ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757339801 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.757339801
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4070773359
Short name T13
Test name
Test status
Simulation time 105793342751 ps
CPU time 1641.92 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:46:08 PM PDT 24
Peak memory 273696 kb
Host smart-21550092-dd8b-4c0c-9df8-59da8dca557f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070773359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4070773359
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4282575199
Short name T576
Test name
Test status
Simulation time 6496961591 ps
CPU time 64.7 seconds
Started Jul 01 05:18:42 PM PDT 24
Finished Jul 01 05:19:53 PM PDT 24
Peak memory 257608 kb
Host smart-1052037e-0e1e-412f-95bf-590f63bf5035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42825
75199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4282575199
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3384708706
Short name T653
Test name
Test status
Simulation time 3214033845 ps
CPU time 50.87 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:19:38 PM PDT 24
Peak memory 257104 kb
Host smart-fcc8f17f-df76-43da-b740-fe1a3ea36298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33847
08706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3384708706
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.96008630
Short name T356
Test name
Test status
Simulation time 119464965167 ps
CPU time 2386.51 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:58:27 PM PDT 24
Peak memory 288772 kb
Host smart-6dabdba1-ba6e-4cd5-a136-51b1bcd35e02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96008630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.96008630
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3476635539
Short name T101
Test name
Test status
Simulation time 94929971743 ps
CPU time 1517.76 seconds
Started Jul 01 05:18:42 PM PDT 24
Finished Jul 01 05:44:07 PM PDT 24
Peak memory 273776 kb
Host smart-2f46ce27-fe9e-4b44-921c-b0af01b9c7b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476635539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3476635539
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3844329534
Short name T521
Test name
Test status
Simulation time 692293656 ps
CPU time 40.98 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:19:25 PM PDT 24
Peak memory 256864 kb
Host smart-ab1753a6-194e-412e-bdc9-e8159aa89d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38443
29534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3844329534
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.978816472
Short name T525
Test name
Test status
Simulation time 1157358487 ps
CPU time 29 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:19:13 PM PDT 24
Peak memory 257052 kb
Host smart-84bdbcad-9607-4bd4-8b51-5d0d26e19ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97881
6472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.978816472
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3004762764
Short name T450
Test name
Test status
Simulation time 1458049953 ps
CPU time 35.98 seconds
Started Jul 01 05:18:45 PM PDT 24
Finished Jul 01 05:19:27 PM PDT 24
Peak memory 249444 kb
Host smart-bee6807c-5c09-43f4-acf9-8b1396b9de0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30047
62764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3004762764
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2999912350
Short name T635
Test name
Test status
Simulation time 8585845796 ps
CPU time 360.21 seconds
Started Jul 01 05:18:45 PM PDT 24
Finished Jul 01 05:24:51 PM PDT 24
Peak memory 265784 kb
Host smart-0ea28606-6554-4394-835d-2539d343edb3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999912350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2999912350
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.191054652
Short name T48
Test name
Test status
Simulation time 78138289272 ps
CPU time 1877.34 seconds
Started Jul 01 05:18:44 PM PDT 24
Finished Jul 01 05:50:08 PM PDT 24
Peak memory 303112 kb
Host smart-7f5e63be-d9de-444d-b766-cba4f48cb4bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191054652 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.191054652
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1154527325
Short name T44
Test name
Test status
Simulation time 626380629 ps
CPU time 29.39 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:19:10 PM PDT 24
Peak memory 249036 kb
Host smart-21b6824b-25f9-43e6-aae6-b0f8dff625bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11545
27325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1154527325
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.756227332
Short name T401
Test name
Test status
Simulation time 101665408 ps
CPU time 7.85 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:18:54 PM PDT 24
Peak memory 249328 kb
Host smart-a7de5c97-d3a5-4f97-97bd-bde60c9b937b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75622
7332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.756227332
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2333644937
Short name T352
Test name
Test status
Simulation time 161869978392 ps
CPU time 2122.45 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:54:12 PM PDT 24
Peak memory 273908 kb
Host smart-4d622e23-3c2b-49de-b173-35bda3c706d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333644937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2333644937
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.43385764
Short name T628
Test name
Test status
Simulation time 35741050941 ps
CPU time 2267.05 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:56:34 PM PDT 24
Peak memory 282200 kb
Host smart-582fcc83-ded3-4b1f-91ea-3d0b3ab5a078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43385764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.43385764
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1494956140
Short name T506
Test name
Test status
Simulation time 29118493750 ps
CPU time 119.25 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:20:46 PM PDT 24
Peak memory 254896 kb
Host smart-f265fc66-316f-45a9-a580-9e53740c23b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494956140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1494956140
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1418073185
Short name T388
Test name
Test status
Simulation time 5097535677 ps
CPU time 21.73 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:19:08 PM PDT 24
Peak memory 249584 kb
Host smart-4f8e1cd2-12fa-4036-ad7c-793b9c5d407c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
73185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1418073185
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2695098916
Short name T498
Test name
Test status
Simulation time 1401261571 ps
CPU time 30.41 seconds
Started Jul 01 05:18:44 PM PDT 24
Finished Jul 01 05:19:21 PM PDT 24
Peak memory 249284 kb
Host smart-c56b1a05-a74e-49c4-990c-7337be11b297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26950
98916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2695098916
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3298283491
Short name T232
Test name
Test status
Simulation time 867203509 ps
CPU time 29.54 seconds
Started Jul 01 05:18:39 PM PDT 24
Finished Jul 01 05:19:16 PM PDT 24
Peak memory 249400 kb
Host smart-5bd0a8a8-d323-49a9-b2db-8ed51871a5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
83491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3298283491
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2848394841
Short name T422
Test name
Test status
Simulation time 329097160 ps
CPU time 23.22 seconds
Started Jul 01 05:18:35 PM PDT 24
Finished Jul 01 05:19:01 PM PDT 24
Peak memory 257252 kb
Host smart-f483f0bf-99b9-460a-92b7-cc67548599f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28483
94841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2848394841
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1620992542
Short name T298
Test name
Test status
Simulation time 547782245195 ps
CPU time 2327.59 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:57:37 PM PDT 24
Peak memory 289872 kb
Host smart-6a292e77-3eb9-4408-bec4-bf1cf2ef6ad1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620992542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1620992542
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3897147397
Short name T428
Test name
Test status
Simulation time 63805072111 ps
CPU time 5832.62 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 06:56:02 PM PDT 24
Peak memory 350492 kb
Host smart-a070d523-4774-4ae7-bc3e-48c2035ca722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897147397 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3897147397
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.288113313
Short name T605
Test name
Test status
Simulation time 123645415715 ps
CPU time 1630.18 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:46:02 PM PDT 24
Peak memory 273368 kb
Host smart-c271d557-ad2d-4f8f-b034-55f63828a76b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288113313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.288113313
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.749061201
Short name T492
Test name
Test status
Simulation time 1937004638 ps
CPU time 110.12 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:20:42 PM PDT 24
Peak memory 249736 kb
Host smart-7ae79ccf-4491-4268-8ea6-ae77df9689bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74906
1201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.749061201
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3098841770
Short name T570
Test name
Test status
Simulation time 412460466 ps
CPU time 15.97 seconds
Started Jul 01 05:18:37 PM PDT 24
Finished Jul 01 05:18:56 PM PDT 24
Peak memory 248808 kb
Host smart-6eea3ab8-dab1-466a-929e-f1718d328d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30988
41770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3098841770
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3951712564
Short name T344
Test name
Test status
Simulation time 89584379019 ps
CPU time 1323.21 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:40:48 PM PDT 24
Peak memory 273144 kb
Host smart-0884726b-ec07-444e-a775-60ba69abd97b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951712564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3951712564
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2320085774
Short name T463
Test name
Test status
Simulation time 27385238467 ps
CPU time 1629.97 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:45:56 PM PDT 24
Peak memory 274008 kb
Host smart-7dc55d4c-e8cb-4666-a1c5-9ecb850c268b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320085774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2320085774
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1885665760
Short name T3
Test name
Test status
Simulation time 5211481417 ps
CPU time 214.78 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:22:26 PM PDT 24
Peak memory 255812 kb
Host smart-f50a5e17-9eaa-4297-ade2-f4ba6b0d4fc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885665760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1885665760
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.38279017
Short name T556
Test name
Test status
Simulation time 949087332 ps
CPU time 10.2 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:19:00 PM PDT 24
Peak memory 255804 kb
Host smart-6a31af49-974b-4f77-a03c-0a7d2855cbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38279
017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.38279017
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.316797179
Short name T90
Test name
Test status
Simulation time 505782913 ps
CPU time 30.57 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:19:20 PM PDT 24
Peak memory 256936 kb
Host smart-8ff3a061-5dc2-4c56-9310-879f55fe3ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31679
7179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.316797179
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2303025598
Short name T611
Test name
Test status
Simulation time 1852832003 ps
CPU time 16.9 seconds
Started Jul 01 05:18:42 PM PDT 24
Finished Jul 01 05:19:05 PM PDT 24
Peak memory 249308 kb
Host smart-b2f2c5aa-a39e-44c4-ac32-bc265542101c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23030
25598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2303025598
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3900284909
Short name T541
Test name
Test status
Simulation time 2549495483 ps
CPU time 44.24 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:19:31 PM PDT 24
Peak memory 257532 kb
Host smart-3165b2b2-fd56-44a8-a026-58c4a73d4862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002
84909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3900284909
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1690330179
Short name T707
Test name
Test status
Simulation time 27287711744 ps
CPU time 1305.48 seconds
Started Jul 01 05:18:38 PM PDT 24
Finished Jul 01 05:40:28 PM PDT 24
Peak memory 288728 kb
Host smart-0c501868-26b7-4627-8626-77f4842a167e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690330179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1690330179
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4281229654
Short name T509
Test name
Test status
Simulation time 343464880081 ps
CPU time 2800.7 seconds
Started Jul 01 05:18:49 PM PDT 24
Finished Jul 01 06:05:34 PM PDT 24
Peak memory 298728 kb
Host smart-83375fc8-fcdf-4768-be17-0ef4cd160181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281229654 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4281229654
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2398069310
Short name T105
Test name
Test status
Simulation time 8378452177 ps
CPU time 889.17 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:33:36 PM PDT 24
Peak memory 273928 kb
Host smart-ffa14ed1-3f86-4d49-b928-875f56bedc7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398069310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2398069310
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3373087128
Short name T282
Test name
Test status
Simulation time 20983349675 ps
CPU time 93.69 seconds
Started Jul 01 05:18:49 PM PDT 24
Finished Jul 01 05:20:26 PM PDT 24
Peak memory 257556 kb
Host smart-a5346e73-c3f0-4fb0-8a94-97134424a8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33730
87128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3373087128
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2183985295
Short name T405
Test name
Test status
Simulation time 72771985 ps
CPU time 5.61 seconds
Started Jul 01 05:18:49 PM PDT 24
Finished Jul 01 05:18:59 PM PDT 24
Peak memory 249240 kb
Host smart-7cd356c8-cd39-454f-9a9e-71b4800baee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21839
85295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2183985295
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3464916169
Short name T360
Test name
Test status
Simulation time 6642867930 ps
CPU time 662.15 seconds
Started Jul 01 05:18:42 PM PDT 24
Finished Jul 01 05:29:51 PM PDT 24
Peak memory 272936 kb
Host smart-ab0fa7af-9dc0-4bf2-83cf-2b6a0afd6cb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464916169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3464916169
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3985961487
Short name T253
Test name
Test status
Simulation time 65190337963 ps
CPU time 1865.35 seconds
Started Jul 01 05:18:49 PM PDT 24
Finished Jul 01 05:49:59 PM PDT 24
Peak memory 273784 kb
Host smart-a5cb4ab2-f4b9-4891-9586-100534f893d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985961487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3985961487
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1184437309
Short name T326
Test name
Test status
Simulation time 30542783037 ps
CPU time 334.1 seconds
Started Jul 01 05:18:49 PM PDT 24
Finished Jul 01 05:24:27 PM PDT 24
Peak memory 249416 kb
Host smart-90c50923-364e-4197-a68d-e47362eff58e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184437309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1184437309
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.948447541
Short name T711
Test name
Test status
Simulation time 1597821280 ps
CPU time 51.24 seconds
Started Jul 01 05:18:41 PM PDT 24
Finished Jul 01 05:19:40 PM PDT 24
Peak memory 257004 kb
Host smart-03979e1c-537b-4f1e-a212-95da425c3d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94844
7541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.948447541
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1812882938
Short name T430
Test name
Test status
Simulation time 242943459 ps
CPU time 15.23 seconds
Started Jul 01 05:18:40 PM PDT 24
Finished Jul 01 05:19:02 PM PDT 24
Peak memory 256580 kb
Host smart-aca39251-e04c-4867-aa87-3cbc9af3326b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
82938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1812882938
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.822992469
Short name T488
Test name
Test status
Simulation time 263164662 ps
CPU time 9.45 seconds
Started Jul 01 05:18:41 PM PDT 24
Finished Jul 01 05:18:58 PM PDT 24
Peak memory 248840 kb
Host smart-1f14545d-f62d-44e6-b8f8-070fab8290aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82299
2469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.822992469
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2286276715
Short name T595
Test name
Test status
Simulation time 3680864977 ps
CPU time 35 seconds
Started Jul 01 05:18:41 PM PDT 24
Finished Jul 01 05:19:22 PM PDT 24
Peak memory 257616 kb
Host smart-eec83d79-66ab-4567-a601-33b433bdb353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
76715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2286276715
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.679595609
Short name T65
Test name
Test status
Simulation time 40785712785 ps
CPU time 1587.96 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:45:18 PM PDT 24
Peak memory 300704 kb
Host smart-d392c819-0906-49e6-9c73-3f1a53167daf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679595609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.679595609
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1968413899
Short name T505
Test name
Test status
Simulation time 98073549299 ps
CPU time 1700.03 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:47:10 PM PDT 24
Peak memory 290492 kb
Host smart-dead2360-2c3b-4d8d-a660-16ad1677c23a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968413899 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1968413899
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2552625556
Short name T475
Test name
Test status
Simulation time 121383532136 ps
CPU time 1454.16 seconds
Started Jul 01 05:18:45 PM PDT 24
Finished Jul 01 05:43:05 PM PDT 24
Peak memory 273792 kb
Host smart-c1a532e4-f15a-42f4-bd58-cc005f5ea57a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552625556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2552625556
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3684628193
Short name T391
Test name
Test status
Simulation time 3852877492 ps
CPU time 58.07 seconds
Started Jul 01 05:18:45 PM PDT 24
Finished Jul 01 05:19:49 PM PDT 24
Peak memory 257632 kb
Host smart-3abf0938-586c-4887-b4f6-13c5dc1fb51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846
28193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3684628193
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1798118149
Short name T249
Test name
Test status
Simulation time 177577259 ps
CPU time 13.06 seconds
Started Jul 01 05:18:44 PM PDT 24
Finished Jul 01 05:19:03 PM PDT 24
Peak memory 249436 kb
Host smart-8693764e-e5b6-4cc2-a0d7-839e0e715566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17981
18149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1798118149
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.370731040
Short name T409
Test name
Test status
Simulation time 9291614668 ps
CPU time 977.44 seconds
Started Jul 01 05:18:44 PM PDT 24
Finished Jul 01 05:35:07 PM PDT 24
Peak memory 289524 kb
Host smart-7b296370-17c7-4610-82bb-da24d1fd9b27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370731040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.370731040
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2422290704
Short name T332
Test name
Test status
Simulation time 15649501048 ps
CPU time 318.91 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:24:10 PM PDT 24
Peak memory 248292 kb
Host smart-09156fcb-cc1f-4062-b512-b619a310eeeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422290704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2422290704
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2061466934
Short name T675
Test name
Test status
Simulation time 121624334 ps
CPU time 7.35 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:18:57 PM PDT 24
Peak memory 249300 kb
Host smart-ef8aac75-89bc-4947-b0bb-f4ba77755751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
66934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2061466934
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3170985686
Short name T630
Test name
Test status
Simulation time 600742350 ps
CPU time 18.23 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:19:09 PM PDT 24
Peak memory 249192 kb
Host smart-e5f48008-02a3-4ac8-8eb4-75c2c73c9d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31709
85686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3170985686
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3285228736
Short name T382
Test name
Test status
Simulation time 297803947 ps
CPU time 13.2 seconds
Started Jul 01 05:18:45 PM PDT 24
Finished Jul 01 05:19:04 PM PDT 24
Peak memory 255472 kb
Host smart-e73496bf-ab2a-4f65-ad4f-b01283d0ede5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32852
28736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3285228736
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.4089883599
Short name T442
Test name
Test status
Simulation time 277495877 ps
CPU time 24.31 seconds
Started Jul 01 05:18:43 PM PDT 24
Finished Jul 01 05:19:13 PM PDT 24
Peak memory 249216 kb
Host smart-2f35cd65-b23c-44da-b0ea-1a86ca7dece1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40898
83599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.4089883599
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3028471571
Short name T591
Test name
Test status
Simulation time 17915954188 ps
CPU time 1770.23 seconds
Started Jul 01 05:18:45 PM PDT 24
Finished Jul 01 05:48:21 PM PDT 24
Peak memory 290320 kb
Host smart-5ad0e8fb-15a9-481a-ab5a-fbf0c1c22ab4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028471571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3028471571
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3387799860
Short name T34
Test name
Test status
Simulation time 3103234898 ps
CPU time 75.89 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:20:07 PM PDT 24
Peak memory 256972 kb
Host smart-8719176d-2d03-46fe-baa1-62d718e5f1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33877
99860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3387799860
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1888487122
Short name T452
Test name
Test status
Simulation time 145322390 ps
CPU time 5.96 seconds
Started Jul 01 05:18:48 PM PDT 24
Finished Jul 01 05:18:58 PM PDT 24
Peak memory 254268 kb
Host smart-acfd7f80-b72d-4e08-a966-73bccf736e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18884
87122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1888487122
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1272352647
Short name T343
Test name
Test status
Simulation time 88327489181 ps
CPU time 1339.09 seconds
Started Jul 01 05:18:53 PM PDT 24
Finished Jul 01 05:41:15 PM PDT 24
Peak memory 273920 kb
Host smart-3abf97db-7b68-4266-9c8d-0913414a4bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272352647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1272352647
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1822304711
Short name T645
Test name
Test status
Simulation time 105565515199 ps
CPU time 1338.27 seconds
Started Jul 01 05:18:52 PM PDT 24
Finished Jul 01 05:41:14 PM PDT 24
Peak memory 282208 kb
Host smart-da666dd4-7482-4b74-aadc-977fb80178c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822304711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1822304711
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2080302030
Short name T342
Test name
Test status
Simulation time 8198684567 ps
CPU time 164.21 seconds
Started Jul 01 05:18:51 PM PDT 24
Finished Jul 01 05:21:39 PM PDT 24
Peak memory 249456 kb
Host smart-1e9664da-b6a4-4abe-99aa-6028ca8af091
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080302030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2080302030
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1301041415
Short name T569
Test name
Test status
Simulation time 470297717 ps
CPU time 27.51 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:19:19 PM PDT 24
Peak memory 256592 kb
Host smart-b28e691c-2bf7-46b0-953a-ea1bd748d658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13010
41415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1301041415
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.47331324
Short name T406
Test name
Test status
Simulation time 1425034580 ps
CPU time 42.81 seconds
Started Jul 01 05:18:48 PM PDT 24
Finished Jul 01 05:19:35 PM PDT 24
Peak memory 256784 kb
Host smart-6e2115bc-d2b3-463c-8149-be1ea283eb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47331
324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.47331324
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1506623824
Short name T397
Test name
Test status
Simulation time 569565518 ps
CPU time 20.69 seconds
Started Jul 01 05:18:46 PM PDT 24
Finished Jul 01 05:19:12 PM PDT 24
Peak memory 257564 kb
Host smart-f428a1b0-04a9-4cfb-80eb-9c750dc3994c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15066
23824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1506623824
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1879781736
Short name T652
Test name
Test status
Simulation time 447365332 ps
CPU time 23.76 seconds
Started Jul 01 05:18:49 PM PDT 24
Finished Jul 01 05:19:17 PM PDT 24
Peak memory 257404 kb
Host smart-42058079-a234-4c79-93c5-d705b0ebdbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18797
81736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1879781736
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1551650773
Short name T243
Test name
Test status
Simulation time 82840212959 ps
CPU time 1141.01 seconds
Started Jul 01 05:18:52 PM PDT 24
Finished Jul 01 05:37:56 PM PDT 24
Peak memory 273256 kb
Host smart-a41e97c8-12e8-495e-bff8-d7018be1116b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551650773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1551650773
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2421674824
Short name T256
Test name
Test status
Simulation time 71060570518 ps
CPU time 2292.23 seconds
Started Jul 01 05:18:52 PM PDT 24
Finished Jul 01 05:57:08 PM PDT 24
Peak memory 290560 kb
Host smart-8d737033-8799-4235-85c1-1d0a985bdd43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421674824 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2421674824
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.520763990
Short name T470
Test name
Test status
Simulation time 5786341767 ps
CPU time 133.13 seconds
Started Jul 01 05:18:55 PM PDT 24
Finished Jul 01 05:21:11 PM PDT 24
Peak memory 257024 kb
Host smart-c67b601e-4307-483b-8946-ba592c3e1713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52076
3990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.520763990
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1839608878
Short name T587
Test name
Test status
Simulation time 720931244 ps
CPU time 17.58 seconds
Started Jul 01 05:18:54 PM PDT 24
Finished Jul 01 05:19:14 PM PDT 24
Peak memory 248908 kb
Host smart-175fc165-0767-4ecc-ad5d-7ae66c0641ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18396
08878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1839608878
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4264095338
Short name T585
Test name
Test status
Simulation time 27658669203 ps
CPU time 1467.65 seconds
Started Jul 01 05:18:52 PM PDT 24
Finished Jul 01 05:43:23 PM PDT 24
Peak memory 273992 kb
Host smart-277d49d0-e39a-403c-888a-b9b0e29a6016
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264095338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4264095338
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1492975001
Short name T472
Test name
Test status
Simulation time 23351945857 ps
CPU time 1593.79 seconds
Started Jul 01 05:18:51 PM PDT 24
Finished Jul 01 05:45:28 PM PDT 24
Peak memory 273972 kb
Host smart-e4429d6d-fb4f-4609-9c09-2c627fe0e79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492975001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1492975001
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2082774913
Short name T331
Test name
Test status
Simulation time 48884613599 ps
CPU time 502.58 seconds
Started Jul 01 05:18:55 PM PDT 24
Finished Jul 01 05:27:20 PM PDT 24
Peak memory 256632 kb
Host smart-aadd586f-ea33-433f-bc1b-a34b98d7a6e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082774913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2082774913
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2204884681
Short name T494
Test name
Test status
Simulation time 180019636 ps
CPU time 22.5 seconds
Started Jul 01 05:18:58 PM PDT 24
Finished Jul 01 05:19:23 PM PDT 24
Peak memory 256780 kb
Host smart-7c3576c4-d403-4fbe-8bc2-cb58b6228823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22048
84681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2204884681
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2083725082
Short name T106
Test name
Test status
Simulation time 311503235 ps
CPU time 30.14 seconds
Started Jul 01 05:18:58 PM PDT 24
Finished Jul 01 05:19:30 PM PDT 24
Peak memory 256912 kb
Host smart-a68d3209-5711-45b3-b1d4-ad7673ce3f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20837
25082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2083725082
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2294274969
Short name T588
Test name
Test status
Simulation time 482222612 ps
CPU time 26.14 seconds
Started Jul 01 05:18:54 PM PDT 24
Finished Jul 01 05:19:23 PM PDT 24
Peak memory 256512 kb
Host smart-3e7ed090-20d4-478a-b0dc-a87237306763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22942
74969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2294274969
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3411592183
Short name T79
Test name
Test status
Simulation time 1012375789 ps
CPU time 19.4 seconds
Started Jul 01 05:18:55 PM PDT 24
Finished Jul 01 05:19:16 PM PDT 24
Peak memory 256640 kb
Host smart-a5506ecb-535f-4eb9-ba7f-c3dc60dc4487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34115
92183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3411592183
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.4230217094
Short name T233
Test name
Test status
Simulation time 267369857188 ps
CPU time 4386.94 seconds
Started Jul 01 05:18:51 PM PDT 24
Finished Jul 01 06:32:02 PM PDT 24
Peak memory 322576 kb
Host smart-d9d801ed-99fe-4d86-8510-2350b4444319
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230217094 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.4230217094
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.694935759
Short name T540
Test name
Test status
Simulation time 54556100268 ps
CPU time 1514.21 seconds
Started Jul 01 05:18:51 PM PDT 24
Finished Jul 01 05:44:09 PM PDT 24
Peak memory 273984 kb
Host smart-336cb92e-a2a9-4c53-862b-afbe8f69ce96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694935759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.694935759
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1525120762
Short name T497
Test name
Test status
Simulation time 389543963 ps
CPU time 28.92 seconds
Started Jul 01 05:18:52 PM PDT 24
Finished Jul 01 05:19:24 PM PDT 24
Peak memory 256700 kb
Host smart-79e490d3-d695-41de-af90-e09670e7dbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15251
20762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1525120762
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1686239764
Short name T481
Test name
Test status
Simulation time 2268498500 ps
CPU time 32.44 seconds
Started Jul 01 05:18:51 PM PDT 24
Finished Jul 01 05:19:27 PM PDT 24
Peak memory 249032 kb
Host smart-7773fdcb-7d03-4cda-b8a9-f3db1e9b77f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16862
39764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1686239764
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1991307343
Short name T471
Test name
Test status
Simulation time 374084012409 ps
CPU time 2171.32 seconds
Started Jul 01 05:19:02 PM PDT 24
Finished Jul 01 05:55:16 PM PDT 24
Peak memory 288416 kb
Host smart-ab5c6ec4-70d8-4a58-b778-9d4a965881d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991307343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1991307343
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1571788810
Short name T668
Test name
Test status
Simulation time 21295607828 ps
CPU time 429.63 seconds
Started Jul 01 05:18:55 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 249224 kb
Host smart-7862ea6f-bf7c-466c-b9d9-afb3bff56da8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571788810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1571788810
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4116264510
Short name T631
Test name
Test status
Simulation time 1962524437 ps
CPU time 46.91 seconds
Started Jul 01 05:18:52 PM PDT 24
Finished Jul 01 05:19:42 PM PDT 24
Peak memory 256852 kb
Host smart-b68cc19f-879c-40da-bdcb-dcd854c86d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41162
64510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4116264510
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4045242752
Short name T539
Test name
Test status
Simulation time 183953863 ps
CPU time 17.79 seconds
Started Jul 01 05:18:51 PM PDT 24
Finished Jul 01 05:19:12 PM PDT 24
Peak memory 249304 kb
Host smart-618db834-c72f-46ce-bc21-05684c7a0648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40452
42752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4045242752
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.853757337
Short name T28
Test name
Test status
Simulation time 839750185 ps
CPU time 26.03 seconds
Started Jul 01 05:18:51 PM PDT 24
Finished Jul 01 05:19:20 PM PDT 24
Peak memory 249308 kb
Host smart-52bfb06c-dafb-4c8d-a1c1-e49071cc521b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85375
7337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.853757337
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2314979205
Short name T73
Test name
Test status
Simulation time 1683519683 ps
CPU time 46.32 seconds
Started Jul 01 05:18:53 PM PDT 24
Finished Jul 01 05:19:42 PM PDT 24
Peak memory 249612 kb
Host smart-e87d3660-e63b-4cbc-9696-7ccaabd562da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23149
79205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2314979205
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3278936200
Short name T266
Test name
Test status
Simulation time 27951625144 ps
CPU time 639.33 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:29:53 PM PDT 24
Peak memory 273944 kb
Host smart-6cfaba4f-db3e-4e67-9cde-25c44d1cb9cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278936200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3278936200
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2552485742
Short name T440
Test name
Test status
Simulation time 28122874103 ps
CPU time 1301.46 seconds
Started Jul 01 05:18:59 PM PDT 24
Finished Jul 01 05:40:42 PM PDT 24
Peak memory 289388 kb
Host smart-0edd3019-f543-44b4-b4ed-cf845a6cedcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552485742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2552485742
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2181283067
Short name T2
Test name
Test status
Simulation time 73614795 ps
CPU time 5.69 seconds
Started Jul 01 05:19:00 PM PDT 24
Finished Jul 01 05:19:08 PM PDT 24
Peak memory 252400 kb
Host smart-53539a7c-90e2-41ad-944f-97f7c3b251b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812
83067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2181283067
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2181310217
Short name T535
Test name
Test status
Simulation time 196366562 ps
CPU time 14.67 seconds
Started Jul 01 05:19:03 PM PDT 24
Finished Jul 01 05:19:20 PM PDT 24
Peak memory 248804 kb
Host smart-ec5a9101-aafc-4651-92ba-21667cffb075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
10217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2181310217
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3025936600
Short name T349
Test name
Test status
Simulation time 16364654891 ps
CPU time 1353.42 seconds
Started Jul 01 05:19:03 PM PDT 24
Finished Jul 01 05:41:39 PM PDT 24
Peak memory 290368 kb
Host smart-ddcea3fe-ebea-4127-8de0-b05969ba204e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025936600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3025936600
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3462510887
Short name T513
Test name
Test status
Simulation time 81302193193 ps
CPU time 1203.6 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:39:17 PM PDT 24
Peak memory 287796 kb
Host smart-e177575e-21f6-441e-be0a-4c8321e2da59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462510887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3462510887
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3258310723
Short name T304
Test name
Test status
Simulation time 29418504199 ps
CPU time 169.83 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 05:21:53 PM PDT 24
Peak memory 249416 kb
Host smart-293a3e6d-8c9b-48af-84fe-1511c88b03e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258310723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3258310723
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.88361073
Short name T455
Test name
Test status
Simulation time 341226936 ps
CPU time 19.31 seconds
Started Jul 01 05:19:00 PM PDT 24
Finished Jul 01 05:19:22 PM PDT 24
Peak memory 255928 kb
Host smart-f8f23b27-57e5-4560-a83b-4a3c1168bc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88361
073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.88361073
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3388763727
Short name T240
Test name
Test status
Simulation time 984259165 ps
CPU time 37.4 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 05:19:41 PM PDT 24
Peak memory 257036 kb
Host smart-48d3dba1-6000-4daa-bfd8-ad1bb89608ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33887
63727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3388763727
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2147008596
Short name T198
Test name
Test status
Simulation time 1111077263 ps
CPU time 70.37 seconds
Started Jul 01 05:19:02 PM PDT 24
Finished Jul 01 05:20:15 PM PDT 24
Peak memory 248752 kb
Host smart-09455607-0ee8-44fe-b289-7609ac960a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21470
08596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2147008596
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1468944021
Short name T441
Test name
Test status
Simulation time 2947803609 ps
CPU time 42.53 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:55 PM PDT 24
Peak memory 257176 kb
Host smart-95d6d5c4-e0b8-47c8-bacd-951a5d2a6ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14689
44021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1468944021
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1644349751
Short name T545
Test name
Test status
Simulation time 1756414228 ps
CPU time 162.11 seconds
Started Jul 01 05:19:00 PM PDT 24
Finished Jul 01 05:21:44 PM PDT 24
Peak memory 257524 kb
Host smart-741fe76a-853a-4d65-a76a-a17a3d446fed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644349751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1644349751
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3505918417
Short name T100
Test name
Test status
Simulation time 205130909250 ps
CPU time 3092.81 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 06:10:37 PM PDT 24
Peak memory 289520 kb
Host smart-2229f9cb-27c1-4f2e-8529-7ef843e48ad5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505918417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3505918417
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.82188095
Short name T684
Test name
Test status
Simulation time 2851582613 ps
CPU time 101.47 seconds
Started Jul 01 05:19:05 PM PDT 24
Finished Jul 01 05:20:48 PM PDT 24
Peak memory 257592 kb
Host smart-e96055dc-1380-4a76-92e0-710cd59e2563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82188
095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.82188095
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.846787550
Short name T590
Test name
Test status
Simulation time 392756163 ps
CPU time 9.19 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:22 PM PDT 24
Peak memory 248852 kb
Host smart-0b9797ad-84f1-48b7-9c86-ecf857254021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84678
7550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.846787550
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3898743783
Short name T627
Test name
Test status
Simulation time 19810581581 ps
CPU time 1112.51 seconds
Started Jul 01 05:18:59 PM PDT 24
Finished Jul 01 05:37:33 PM PDT 24
Peak memory 283852 kb
Host smart-9f89ca35-bcf7-4c3a-bdbb-ad90600a12a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898743783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3898743783
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.566166177
Short name T392
Test name
Test status
Simulation time 36222522083 ps
CPU time 1428.25 seconds
Started Jul 01 05:18:59 PM PDT 24
Finished Jul 01 05:42:50 PM PDT 24
Peak memory 288136 kb
Host smart-158df7de-3c60-47a2-bb92-8e95206761e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566166177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.566166177
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2385341537
Short name T300
Test name
Test status
Simulation time 20552478859 ps
CPU time 149 seconds
Started Jul 01 05:19:04 PM PDT 24
Finished Jul 01 05:21:35 PM PDT 24
Peak memory 256496 kb
Host smart-8ba84f63-5d54-412f-af34-f04ffde9a371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385341537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2385341537
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2893274787
Short name T491
Test name
Test status
Simulation time 524545436 ps
CPU time 13.87 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 05:19:17 PM PDT 24
Peak memory 256764 kb
Host smart-12adc15b-81f7-4ca5-8a2d-aa606508d2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28932
74787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2893274787
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2583604260
Short name T234
Test name
Test status
Simulation time 363424872 ps
CPU time 19.09 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:31 PM PDT 24
Peak memory 256908 kb
Host smart-2464db10-12bf-4ceb-bf91-1269c2ce1c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25836
04260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2583604260
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.26927551
Short name T687
Test name
Test status
Simulation time 658975753 ps
CPU time 12.28 seconds
Started Jul 01 05:18:59 PM PDT 24
Finished Jul 01 05:19:14 PM PDT 24
Peak memory 256568 kb
Host smart-92e7aa7a-3074-47a2-890a-a54c045f2e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26927
551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.26927551
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.421019639
Short name T609
Test name
Test status
Simulation time 1600923844 ps
CPU time 38 seconds
Started Jul 01 05:19:00 PM PDT 24
Finished Jul 01 05:19:40 PM PDT 24
Peak memory 257480 kb
Host smart-8f0e58ff-2146-4ac2-96ee-d66e2c82f172
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421019639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.421019639
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2731104014
Short name T118
Test name
Test status
Simulation time 242572293717 ps
CPU time 6426.76 seconds
Started Jul 01 05:18:59 PM PDT 24
Finished Jul 01 07:06:09 PM PDT 24
Peak memory 355604 kb
Host smart-4c8f6ef3-81eb-4893-848a-aee7ac987ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731104014 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2731104014
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1711812457
Short name T215
Test name
Test status
Simulation time 163682767 ps
CPU time 3.52 seconds
Started Jul 01 05:17:57 PM PDT 24
Finished Jul 01 05:18:03 PM PDT 24
Peak memory 249520 kb
Host smart-0b953cbb-40fc-4a1c-8a0b-a1bdf050c875
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1711812457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1711812457
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2602157068
Short name T642
Test name
Test status
Simulation time 17421838368 ps
CPU time 1458.2 seconds
Started Jul 01 05:17:55 PM PDT 24
Finished Jul 01 05:42:15 PM PDT 24
Peak memory 289728 kb
Host smart-684469e1-a392-4141-b7a7-3aba4286f2d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602157068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2602157068
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1838648638
Short name T225
Test name
Test status
Simulation time 1546686495 ps
CPU time 20.55 seconds
Started Jul 01 05:17:57 PM PDT 24
Finished Jul 01 05:18:20 PM PDT 24
Peak memory 249420 kb
Host smart-71ae9271-0cae-4ad2-aaea-8aff61fbd4ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1838648638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1838648638
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.163527165
Short name T692
Test name
Test status
Simulation time 2858109420 ps
CPU time 175.24 seconds
Started Jul 01 05:17:49 PM PDT 24
Finished Jul 01 05:20:48 PM PDT 24
Peak memory 257120 kb
Host smart-0b45e77f-faff-419f-b5c2-1a8b3c84b3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
7165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.163527165
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1189132012
Short name T703
Test name
Test status
Simulation time 372594170 ps
CPU time 33.01 seconds
Started Jul 01 05:17:48 PM PDT 24
Finished Jul 01 05:18:25 PM PDT 24
Peak memory 256996 kb
Host smart-dfe4bc5b-de15-43c6-9e21-ef0880ed5c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11891
32012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1189132012
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.165667914
Short name T348
Test name
Test status
Simulation time 22397179404 ps
CPU time 779.05 seconds
Started Jul 01 05:17:57 PM PDT 24
Finished Jul 01 05:30:59 PM PDT 24
Peak memory 273880 kb
Host smart-e0bd7467-ca64-4134-87d9-1ff3006287cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165667914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.165667914
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3509402887
Short name T411
Test name
Test status
Simulation time 20972341426 ps
CPU time 776.61 seconds
Started Jul 01 05:17:58 PM PDT 24
Finished Jul 01 05:30:57 PM PDT 24
Peak memory 272804 kb
Host smart-7329fca1-36a2-4de3-bb10-a03550689e03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509402887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3509402887
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.279384442
Short name T340
Test name
Test status
Simulation time 10702099484 ps
CPU time 417.52 seconds
Started Jul 01 05:17:57 PM PDT 24
Finished Jul 01 05:24:56 PM PDT 24
Peak memory 249484 kb
Host smart-d1b4429d-927b-4cef-aba8-4d789351a6f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279384442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.279384442
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3279907248
Short name T77
Test name
Test status
Simulation time 3985226045 ps
CPU time 28.64 seconds
Started Jul 01 05:17:55 PM PDT 24
Finished Jul 01 05:18:26 PM PDT 24
Peak memory 256928 kb
Host smart-22345788-2f65-47ac-9106-9473cf54b140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32799
07248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3279907248
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.902489536
Short name T287
Test name
Test status
Simulation time 47987513 ps
CPU time 6.36 seconds
Started Jul 01 05:17:49 PM PDT 24
Finished Jul 01 05:17:59 PM PDT 24
Peak memory 240640 kb
Host smart-e7927594-3959-444b-9ecc-ac15dedaca21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90248
9536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.902489536
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3052919909
Short name T9
Test name
Test status
Simulation time 820092310 ps
CPU time 12.98 seconds
Started Jul 01 05:17:59 PM PDT 24
Finished Jul 01 05:18:14 PM PDT 24
Peak memory 267592 kb
Host smart-57f8bbce-c60e-4f27-82e2-f85c2c02a8f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3052919909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3052919909
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1631938117
Short name T568
Test name
Test status
Simulation time 2356859371 ps
CPU time 34.05 seconds
Started Jul 01 05:17:47 PM PDT 24
Finished Jul 01 05:18:25 PM PDT 24
Peak memory 249444 kb
Host smart-aa1a0eea-bb39-4ec4-94ce-ad31c0bb2b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319
38117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1631938117
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.619776808
Short name T663
Test name
Test status
Simulation time 284762569 ps
CPU time 29.26 seconds
Started Jul 01 05:17:50 PM PDT 24
Finished Jul 01 05:18:23 PM PDT 24
Peak memory 249720 kb
Host smart-df4bb46a-52f0-47cc-95a0-94b7860b6e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61977
6808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.619776808
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3951337436
Short name T75
Test name
Test status
Simulation time 55719977195 ps
CPU time 1941.5 seconds
Started Jul 01 05:17:57 PM PDT 24
Finished Jul 01 05:50:20 PM PDT 24
Peak memory 289920 kb
Host smart-c4788991-fb65-47af-9c0c-98ebdae7a8bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951337436 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3951337436
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3190566231
Short name T91
Test name
Test status
Simulation time 48348164636 ps
CPU time 1242.8 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 05:39:46 PM PDT 24
Peak memory 290268 kb
Host smart-2126ea77-3799-47c3-8a43-556003e89a99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190566231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3190566231
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1621425190
Short name T226
Test name
Test status
Simulation time 23089823961 ps
CPU time 346.33 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 05:24:51 PM PDT 24
Peak memory 251960 kb
Host smart-a24d0428-04c4-4ced-9bdd-39326b4698c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214
25190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1621425190
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.4220064708
Short name T420
Test name
Test status
Simulation time 841691259 ps
CPU time 54.24 seconds
Started Jul 01 05:19:00 PM PDT 24
Finished Jul 01 05:19:58 PM PDT 24
Peak memory 249404 kb
Host smart-cf115429-18a0-48a6-86ce-c0f0406f9fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42200
64708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.4220064708
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.983665110
Short name T357
Test name
Test status
Simulation time 111486851665 ps
CPU time 3208.68 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 06:12:41 PM PDT 24
Peak memory 290340 kb
Host smart-0ffb883c-4fa6-446c-b623-0093a340ba26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983665110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.983665110
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.809548535
Short name T486
Test name
Test status
Simulation time 15259199529 ps
CPU time 1444.19 seconds
Started Jul 01 05:19:00 PM PDT 24
Finished Jul 01 05:43:08 PM PDT 24
Peak memory 290356 kb
Host smart-eed0983a-f648-4ee2-a3ef-8b144d4aa6e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809548535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.809548535
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4146220951
Short name T543
Test name
Test status
Simulation time 352846695 ps
CPU time 9.54 seconds
Started Jul 01 05:19:03 PM PDT 24
Finished Jul 01 05:19:15 PM PDT 24
Peak memory 249300 kb
Host smart-bddfd882-5225-45da-a67a-e46237e6523b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41462
20951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4146220951
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.159158205
Short name T680
Test name
Test status
Simulation time 3359283181 ps
CPU time 52.43 seconds
Started Jul 01 05:19:00 PM PDT 24
Finished Jul 01 05:19:55 PM PDT 24
Peak memory 257416 kb
Host smart-a56dbf03-8802-40cc-8fb8-2234d1cc3947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15915
8205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.159158205
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3442891620
Short name T476
Test name
Test status
Simulation time 1086719319 ps
CPU time 25.59 seconds
Started Jul 01 05:19:01 PM PDT 24
Finished Jul 01 05:19:29 PM PDT 24
Peak memory 249328 kb
Host smart-42809647-15a3-44aa-bd4c-1e2102244729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34428
91620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3442891620
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3933916155
Short name T686
Test name
Test status
Simulation time 2420748177 ps
CPU time 42.7 seconds
Started Jul 01 05:18:58 PM PDT 24
Finished Jul 01 05:19:43 PM PDT 24
Peak memory 257556 kb
Host smart-f4d02be3-ffa6-4b4b-ae35-7eb1b03263b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39339
16155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3933916155
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3468068565
Short name T553
Test name
Test status
Simulation time 2031218363 ps
CPU time 185.61 seconds
Started Jul 01 05:18:59 PM PDT 24
Finished Jul 01 05:22:07 PM PDT 24
Peak memory 257608 kb
Host smart-249a0b16-df70-4252-8988-6c399f9599c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468068565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3468068565
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3931684874
Short name T514
Test name
Test status
Simulation time 86203670194 ps
CPU time 1052.26 seconds
Started Jul 01 05:19:11 PM PDT 24
Finished Jul 01 05:36:46 PM PDT 24
Peak memory 284112 kb
Host smart-5c0eb8a4-b81a-41ff-8a6b-385a6653412f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931684874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3931684874
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2926508334
Short name T702
Test name
Test status
Simulation time 1734814338 ps
CPU time 27.32 seconds
Started Jul 01 05:19:15 PM PDT 24
Finished Jul 01 05:19:44 PM PDT 24
Peak memory 256988 kb
Host smart-f4a2ff74-5110-4ea8-b6ea-ad9437cf9b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29265
08334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2926508334
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1665711854
Short name T51
Test name
Test status
Simulation time 1555274454 ps
CPU time 29.42 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:19:41 PM PDT 24
Peak memory 249288 kb
Host smart-e9eddbf6-e8d6-479e-93e7-07a81ecad8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
11854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1665711854
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2381168320
Short name T403
Test name
Test status
Simulation time 92102617634 ps
CPU time 872.47 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:33:45 PM PDT 24
Peak memory 273940 kb
Host smart-c5bb1ef9-f1b6-41b1-b207-e1c0a684241d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381168320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2381168320
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2710610347
Short name T313
Test name
Test status
Simulation time 4744615824 ps
CPU time 194.31 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:22:26 PM PDT 24
Peak memory 249416 kb
Host smart-3814edfe-8a84-4062-a5ae-ad416c947a86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710610347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2710610347
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1915170230
Short name T429
Test name
Test status
Simulation time 243973738 ps
CPU time 15.82 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:29 PM PDT 24
Peak memory 257448 kb
Host smart-db3365bf-a3ff-4391-b90b-5e6488b755d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
70230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1915170230
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3153236905
Short name T490
Test name
Test status
Simulation time 259427753 ps
CPU time 26.8 seconds
Started Jul 01 05:19:15 PM PDT 24
Finished Jul 01 05:19:44 PM PDT 24
Peak memory 249280 kb
Host smart-f769a83b-d6ea-475b-8c7c-b8e5069ed732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532
36905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3153236905
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.183266765
Short name T504
Test name
Test status
Simulation time 218543391 ps
CPU time 4.16 seconds
Started Jul 01 05:19:11 PM PDT 24
Finished Jul 01 05:19:18 PM PDT 24
Peak memory 253020 kb
Host smart-7c2169cd-1d5d-4833-bc69-b96edaa19fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18326
6765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.183266765
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3879757792
Short name T524
Test name
Test status
Simulation time 495740810 ps
CPU time 31.46 seconds
Started Jul 01 05:19:08 PM PDT 24
Finished Jul 01 05:19:41 PM PDT 24
Peak memory 257532 kb
Host smart-a1384ca2-7e96-49ea-9b37-baed4db64366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38797
57792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3879757792
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.294439951
Short name T262
Test name
Test status
Simulation time 22395927964 ps
CPU time 2093.13 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:54:05 PM PDT 24
Peak memory 305800 kb
Host smart-2a59843b-888e-4e13-97d8-2f0d1e0e4e9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294439951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.294439951
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1704463374
Short name T607
Test name
Test status
Simulation time 64557596394 ps
CPU time 1599.13 seconds
Started Jul 01 05:19:08 PM PDT 24
Finished Jul 01 05:45:50 PM PDT 24
Peak memory 290320 kb
Host smart-645f62b6-5e79-4165-8549-1d87d83c0e2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704463374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1704463374
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3355991712
Short name T685
Test name
Test status
Simulation time 736797305 ps
CPU time 69.03 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:20:20 PM PDT 24
Peak memory 256804 kb
Host smart-f4deaf10-5dc2-4709-9d14-a167da31a346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33559
91712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3355991712
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4023490071
Short name T594
Test name
Test status
Simulation time 201757527 ps
CPU time 8.67 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:21 PM PDT 24
Peak memory 248944 kb
Host smart-b492fd0e-ea41-4acb-a849-237b95e90d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40234
90071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4023490071
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2374209465
Short name T416
Test name
Test status
Simulation time 56196031392 ps
CPU time 1611.63 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:46:04 PM PDT 24
Peak memory 290200 kb
Host smart-88191e1f-1c7b-4962-a29f-afa60b496606
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374209465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2374209465
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2946663295
Short name T229
Test name
Test status
Simulation time 26542762974 ps
CPU time 276.7 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:23:50 PM PDT 24
Peak memory 249416 kb
Host smart-bf8b2757-7cd5-4bf5-b5d2-0d732fb7a18a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946663295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2946663295
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.4045649670
Short name T683
Test name
Test status
Simulation time 964755071 ps
CPU time 39.1 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:52 PM PDT 24
Peak memory 249288 kb
Host smart-24b556db-6f25-49b6-9576-812852ebbb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
49670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.4045649670
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.868644066
Short name T712
Test name
Test status
Simulation time 979639424 ps
CPU time 35.21 seconds
Started Jul 01 05:19:11 PM PDT 24
Finished Jul 01 05:19:49 PM PDT 24
Peak memory 255956 kb
Host smart-cc0ce74d-a849-4083-941f-e503e1089a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86864
4066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.868644066
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3106530016
Short name T549
Test name
Test status
Simulation time 1790364734 ps
CPU time 37.94 seconds
Started Jul 01 05:19:12 PM PDT 24
Finished Jul 01 05:19:52 PM PDT 24
Peak memory 249280 kb
Host smart-8dd8cee7-23d6-4bc8-9259-297994467877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31065
30016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3106530016
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3097847943
Short name T473
Test name
Test status
Simulation time 868492056 ps
CPU time 50.57 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:20:04 PM PDT 24
Peak memory 257412 kb
Host smart-0ac1a77b-c80e-4cb5-8194-dd8a32ae7a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30978
47943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3097847943
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2501579136
Short name T223
Test name
Test status
Simulation time 117595806463 ps
CPU time 1833.72 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:49:45 PM PDT 24
Peak memory 282180 kb
Host smart-7b534dde-cb86-4837-9169-45e7d445d7ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501579136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2501579136
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1097624921
Short name T527
Test name
Test status
Simulation time 293518061 ps
CPU time 26.98 seconds
Started Jul 01 05:19:12 PM PDT 24
Finished Jul 01 05:19:41 PM PDT 24
Peak memory 249332 kb
Host smart-4564f11e-4061-4253-be09-afbd6471cdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10976
24921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1097624921
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2935915981
Short name T688
Test name
Test status
Simulation time 418779031 ps
CPU time 20.48 seconds
Started Jul 01 05:19:09 PM PDT 24
Finished Jul 01 05:19:33 PM PDT 24
Peak memory 248864 kb
Host smart-41aaedfa-42ef-4a26-9a5d-ae21223f32bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29359
15981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2935915981
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.48820471
Short name T517
Test name
Test status
Simulation time 50892737255 ps
CPU time 1323.07 seconds
Started Jul 01 05:19:07 PM PDT 24
Finished Jul 01 05:41:12 PM PDT 24
Peak memory 273396 kb
Host smart-b31a7dbc-d5fd-43d4-9d7b-bcc6021b720e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48820471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.48820471
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1779051654
Short name T104
Test name
Test status
Simulation time 24059547467 ps
CPU time 1233.64 seconds
Started Jul 01 05:19:17 PM PDT 24
Finished Jul 01 05:39:54 PM PDT 24
Peak memory 274040 kb
Host smart-2daa8f34-cf93-4271-91ce-6f4733e22fdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779051654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1779051654
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3406397547
Short name T638
Test name
Test status
Simulation time 123226311525 ps
CPU time 490.49 seconds
Started Jul 01 05:19:13 PM PDT 24
Finished Jul 01 05:27:25 PM PDT 24
Peak memory 256112 kb
Host smart-25dc6edf-3218-4df5-b026-6cb64562f04f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406397547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3406397547
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.983163528
Short name T577
Test name
Test status
Simulation time 345785444 ps
CPU time 28.77 seconds
Started Jul 01 05:19:10 PM PDT 24
Finished Jul 01 05:19:41 PM PDT 24
Peak memory 249288 kb
Host smart-097a8767-9867-460d-a6db-5d85bf741331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98316
3528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.983163528
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.31949177
Short name T700
Test name
Test status
Simulation time 563836360 ps
CPU time 17.28 seconds
Started Jul 01 05:19:12 PM PDT 24
Finished Jul 01 05:19:32 PM PDT 24
Peak memory 248848 kb
Host smart-2eb42ca6-3577-437d-bdf4-c231923f215a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31949
177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.31949177
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3987211217
Short name T23
Test name
Test status
Simulation time 3233769668 ps
CPU time 51.97 seconds
Started Jul 01 05:19:11 PM PDT 24
Finished Jul 01 05:20:06 PM PDT 24
Peak memory 249468 kb
Host smart-e8b3ea62-9475-4633-b45e-bc7a644845bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39872
11217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3987211217
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.34671156
Short name T482
Test name
Test status
Simulation time 2591111732 ps
CPU time 48.18 seconds
Started Jul 01 05:19:08 PM PDT 24
Finished Jul 01 05:19:57 PM PDT 24
Peak memory 257376 kb
Host smart-471d34d2-0d07-449e-8605-37ec135cd313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34671
156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.34671156
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3518001281
Short name T195
Test name
Test status
Simulation time 86421954561 ps
CPU time 4716.64 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 06:38:00 PM PDT 24
Peak memory 306788 kb
Host smart-9f8a580d-c25c-44fe-b3b5-54dc940deac6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518001281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3518001281
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1865421635
Short name T63
Test name
Test status
Simulation time 31900029032 ps
CPU time 2799.92 seconds
Started Jul 01 05:19:19 PM PDT 24
Finished Jul 01 06:06:04 PM PDT 24
Peak memory 323304 kb
Host smart-a5be25d7-131b-437f-b9f5-082057bf58d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865421635 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1865421635
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.968500909
Short name T108
Test name
Test status
Simulation time 25843685129 ps
CPU time 1364.69 seconds
Started Jul 01 05:19:17 PM PDT 24
Finished Jul 01 05:42:05 PM PDT 24
Peak memory 273976 kb
Host smart-27fc91e2-882d-4f63-9091-f6c732973585
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968500909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.968500909
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1775402536
Short name T565
Test name
Test status
Simulation time 257043059 ps
CPU time 20.44 seconds
Started Jul 01 05:19:20 PM PDT 24
Finished Jul 01 05:19:45 PM PDT 24
Peak memory 256804 kb
Host smart-dffda567-8307-4712-994b-3c4bf057dd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17754
02536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1775402536
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.4261908849
Short name T247
Test name
Test status
Simulation time 312034101 ps
CPU time 17.44 seconds
Started Jul 01 05:19:17 PM PDT 24
Finished Jul 01 05:19:37 PM PDT 24
Peak memory 255872 kb
Host smart-40d1ba85-39b0-46d4-a495-c825275632fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42619
08849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4261908849
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3382889047
Short name T323
Test name
Test status
Simulation time 41165741232 ps
CPU time 1908.48 seconds
Started Jul 01 05:19:19 PM PDT 24
Finished Jul 01 05:51:13 PM PDT 24
Peak memory 283580 kb
Host smart-e56a82db-8847-487c-954f-0adc6ea854ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382889047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3382889047
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.825765899
Short name T301
Test name
Test status
Simulation time 123142705879 ps
CPU time 920.78 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:34:44 PM PDT 24
Peak memory 273936 kb
Host smart-5ec6805f-d451-463d-9e8f-abb9f9efbea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825765899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.825765899
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1421639130
Short name T312
Test name
Test status
Simulation time 9360177012 ps
CPU time 377.71 seconds
Started Jul 01 05:19:17 PM PDT 24
Finished Jul 01 05:25:38 PM PDT 24
Peak memory 249480 kb
Host smart-134687ca-fa05-4007-b6f4-64558515df74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421639130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1421639130
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.501616663
Short name T558
Test name
Test status
Simulation time 1084681885 ps
CPU time 59.15 seconds
Started Jul 01 05:19:21 PM PDT 24
Finished Jul 01 05:20:24 PM PDT 24
Peak memory 257432 kb
Host smart-f3e89ac1-e1bb-4911-819f-6c550e4b12fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50161
6663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.501616663
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3081260315
Short name T186
Test name
Test status
Simulation time 726207221 ps
CPU time 26.62 seconds
Started Jul 01 05:19:20 PM PDT 24
Finished Jul 01 05:19:51 PM PDT 24
Peak memory 248608 kb
Host smart-db534b9e-0df3-4d99-94bf-02d000e99747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30812
60315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3081260315
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1510428047
Short name T224
Test name
Test status
Simulation time 1700074372 ps
CPU time 19.66 seconds
Started Jul 01 05:19:15 PM PDT 24
Finished Jul 01 05:19:37 PM PDT 24
Peak memory 255068 kb
Host smart-0ca86fa1-885f-4ee1-b209-bbc3ac9e6069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15104
28047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1510428047
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1347403418
Short name T617
Test name
Test status
Simulation time 3278811049 ps
CPU time 62.25 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:20:24 PM PDT 24
Peak memory 257652 kb
Host smart-e2155bbd-bab8-43f7-adee-3cc4610e66d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13474
03418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1347403418
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.846958844
Short name T95
Test name
Test status
Simulation time 2481038938 ps
CPU time 73.04 seconds
Started Jul 01 05:19:21 PM PDT 24
Finished Jul 01 05:20:38 PM PDT 24
Peak memory 257640 kb
Host smart-b75792ec-b087-4a09-985e-4139463169fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846958844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.846958844
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1066536960
Short name T103
Test name
Test status
Simulation time 50631327920 ps
CPU time 1533.49 seconds
Started Jul 01 05:19:20 PM PDT 24
Finished Jul 01 05:44:58 PM PDT 24
Peak memory 273888 kb
Host smart-6309855f-0b78-4f59-96e7-b28cfc0e4d39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066536960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1066536960
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3287859622
Short name T433
Test name
Test status
Simulation time 964328413 ps
CPU time 83.28 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:20:45 PM PDT 24
Peak memory 257464 kb
Host smart-106dc602-d844-4ac4-b77b-443a3403eb0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878
59622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3287859622
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2980448672
Short name T531
Test name
Test status
Simulation time 442385000 ps
CPU time 26.24 seconds
Started Jul 01 05:19:22 PM PDT 24
Finished Jul 01 05:19:52 PM PDT 24
Peak memory 248992 kb
Host smart-52087e18-8df7-490c-885c-e7e0a4bf95ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29804
48672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2980448672
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1444740462
Short name T297
Test name
Test status
Simulation time 74704453524 ps
CPU time 1630.98 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:46:34 PM PDT 24
Peak memory 289408 kb
Host smart-50f0a565-59db-4043-a6c1-8e03310fe8ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444740462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1444740462
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.214591301
Short name T512
Test name
Test status
Simulation time 7863507150 ps
CPU time 811.79 seconds
Started Jul 01 05:19:19 PM PDT 24
Finished Jul 01 05:32:55 PM PDT 24
Peak memory 273996 kb
Host smart-f2fd4194-5367-47b7-9f8a-a794eb56c46e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214591301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.214591301
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1946642717
Short name T643
Test name
Test status
Simulation time 25527492278 ps
CPU time 269.63 seconds
Started Jul 01 05:19:17 PM PDT 24
Finished Jul 01 05:23:49 PM PDT 24
Peak memory 249340 kb
Host smart-9d82abc4-4ba8-4317-8999-212bb6b7cad0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946642717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1946642717
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2457366668
Short name T672
Test name
Test status
Simulation time 2970584281 ps
CPU time 51.17 seconds
Started Jul 01 05:19:16 PM PDT 24
Finished Jul 01 05:20:10 PM PDT 24
Peak memory 257588 kb
Host smart-f9f2316f-e6ae-4cfe-a70e-df9def13a8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573
66668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2457366668
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1385117851
Short name T47
Test name
Test status
Simulation time 3008555415 ps
CPU time 14.75 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:19:38 PM PDT 24
Peak memory 248808 kb
Host smart-e7e1e737-dc48-49eb-88be-c53a96a52164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13851
17851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1385117851
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2436454147
Short name T456
Test name
Test status
Simulation time 476678559 ps
CPU time 13.87 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:19:37 PM PDT 24
Peak memory 248652 kb
Host smart-4f2f8970-266f-49f0-aaa6-5eb786ec780f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24364
54147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2436454147
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.839180224
Short name T417
Test name
Test status
Simulation time 953870709 ps
CPU time 47.8 seconds
Started Jul 01 05:19:17 PM PDT 24
Finished Jul 01 05:20:09 PM PDT 24
Peak memory 256560 kb
Host smart-ed1bd91a-7304-4686-9761-48684820bc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83918
0224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.839180224
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3833606624
Short name T560
Test name
Test status
Simulation time 15521004817 ps
CPU time 1310.54 seconds
Started Jul 01 05:19:16 PM PDT 24
Finished Jul 01 05:41:09 PM PDT 24
Peak memory 286344 kb
Host smart-96522082-c127-4544-86a7-3c1dd07d61a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833606624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3833606624
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3140059236
Short name T601
Test name
Test status
Simulation time 484897163 ps
CPU time 45.87 seconds
Started Jul 01 05:19:20 PM PDT 24
Finished Jul 01 05:20:11 PM PDT 24
Peak memory 250284 kb
Host smart-fd7a2cde-1b26-4c06-acf9-a066333bfb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31400
59236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3140059236
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3217437250
Short name T705
Test name
Test status
Simulation time 109204541 ps
CPU time 8.22 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:19:31 PM PDT 24
Peak memory 249208 kb
Host smart-67f17f6e-9019-4440-ac52-a0467942682f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174
37250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3217437250
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.148700059
Short name T18
Test name
Test status
Simulation time 42834095490 ps
CPU time 1279.19 seconds
Started Jul 01 05:19:21 PM PDT 24
Finished Jul 01 05:40:44 PM PDT 24
Peak memory 289700 kb
Host smart-533cd211-693e-414a-a90a-59116fb8bdf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148700059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.148700059
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3397144030
Short name T681
Test name
Test status
Simulation time 2313524196 ps
CPU time 97.43 seconds
Started Jul 01 05:19:16 PM PDT 24
Finished Jul 01 05:20:56 PM PDT 24
Peak memory 255212 kb
Host smart-e43c1396-a8a4-4919-9cf7-cda0690ef9ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397144030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3397144030
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.634721448
Short name T534
Test name
Test status
Simulation time 1165691850 ps
CPU time 69.59 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:20:32 PM PDT 24
Peak memory 256948 kb
Host smart-aec319e6-ba28-45a9-ac13-d45358f8fc7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63472
1448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.634721448
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3820955226
Short name T53
Test name
Test status
Simulation time 40941315 ps
CPU time 5.13 seconds
Started Jul 01 05:19:17 PM PDT 24
Finished Jul 01 05:19:24 PM PDT 24
Peak memory 248852 kb
Host smart-85a62909-5e1d-4437-b807-03a77d8f0f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209
55226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3820955226
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4205081881
Short name T277
Test name
Test status
Simulation time 232339661 ps
CPU time 15.97 seconds
Started Jul 01 05:19:18 PM PDT 24
Finished Jul 01 05:19:39 PM PDT 24
Peak memory 248840 kb
Host smart-d87710d4-1d9e-43f1-a1e7-d1d36e75317f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050
81881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4205081881
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.878128268
Short name T660
Test name
Test status
Simulation time 520300064 ps
CPU time 24.67 seconds
Started Jul 01 05:19:19 PM PDT 24
Finished Jul 01 05:19:48 PM PDT 24
Peak memory 249592 kb
Host smart-c2b0f7d9-c390-4473-bf3c-d4e9ed693952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87812
8268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.878128268
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3214773526
Short name T295
Test name
Test status
Simulation time 187221899740 ps
CPU time 2811.51 seconds
Started Jul 01 05:19:19 PM PDT 24
Finished Jul 01 06:06:15 PM PDT 24
Peak memory 290404 kb
Host smart-b2b4390c-218f-4a76-9ccc-cbfc20f64f91
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214773526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3214773526
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3623401586
Short name T474
Test name
Test status
Simulation time 42369287212 ps
CPU time 1006.92 seconds
Started Jul 01 05:19:26 PM PDT 24
Finished Jul 01 05:36:17 PM PDT 24
Peak memory 289700 kb
Host smart-ceda40a8-dc44-44b1-a0f4-61538309823e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623401586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3623401586
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1306349134
Short name T695
Test name
Test status
Simulation time 6492254122 ps
CPU time 134.64 seconds
Started Jul 01 05:19:20 PM PDT 24
Finished Jul 01 05:21:39 PM PDT 24
Peak memory 252584 kb
Host smart-16a4a3bd-f7f7-4c64-ab5b-afe725d428fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13063
49134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1306349134
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2000740235
Short name T654
Test name
Test status
Simulation time 240796721 ps
CPU time 10.96 seconds
Started Jul 01 05:19:20 PM PDT 24
Finished Jul 01 05:19:35 PM PDT 24
Peak memory 248692 kb
Host smart-35f09b53-3546-455a-9fda-7f6ed95a6b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20007
40235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2000740235
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.327347367
Short name T355
Test name
Test status
Simulation time 9724332810 ps
CPU time 803.55 seconds
Started Jul 01 05:19:28 PM PDT 24
Finished Jul 01 05:32:56 PM PDT 24
Peak memory 273952 kb
Host smart-e1dabdbe-a8c2-42f3-9c98-31b69823a63f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327347367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.327347367
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4012466889
Short name T381
Test name
Test status
Simulation time 82873207881 ps
CPU time 1240.02 seconds
Started Jul 01 05:19:26 PM PDT 24
Finished Jul 01 05:40:10 PM PDT 24
Peak memory 273660 kb
Host smart-89c8468c-9791-47d7-8a72-46521863bd10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012466889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4012466889
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2583828683
Short name T325
Test name
Test status
Simulation time 5614693214 ps
CPU time 137.03 seconds
Started Jul 01 05:19:26 PM PDT 24
Finished Jul 01 05:21:48 PM PDT 24
Peak memory 249444 kb
Host smart-58289bdc-1c98-47e6-ab4c-a585d7f96bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583828683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2583828683
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3898411950
Short name T571
Test name
Test status
Simulation time 284317779 ps
CPU time 19.26 seconds
Started Jul 01 05:19:22 PM PDT 24
Finished Jul 01 05:19:45 PM PDT 24
Peak memory 255608 kb
Host smart-dd88be0d-db7d-4a48-8e60-b3bd2e22276b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38984
11950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3898411950
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1374850571
Short name T710
Test name
Test status
Simulation time 4821356991 ps
CPU time 59.71 seconds
Started Jul 01 05:19:22 PM PDT 24
Finished Jul 01 05:20:25 PM PDT 24
Peak memory 257568 kb
Host smart-8e6e1e52-a2f4-490a-8944-ff75b94528ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13748
50571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1374850571
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.277573321
Short name T237
Test name
Test status
Simulation time 652344472 ps
CPU time 12.72 seconds
Started Jul 01 05:19:25 PM PDT 24
Finished Jul 01 05:19:41 PM PDT 24
Peak memory 249320 kb
Host smart-5e34e928-46f7-48b2-982f-7c001380c1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27757
3321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.277573321
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.478087756
Short name T399
Test name
Test status
Simulation time 202897246 ps
CPU time 12.48 seconds
Started Jul 01 05:19:21 PM PDT 24
Finished Jul 01 05:19:38 PM PDT 24
Peak memory 255552 kb
Host smart-633b299e-f34c-486f-bb8c-84ac7be08d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47808
7756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.478087756
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.309829486
Short name T608
Test name
Test status
Simulation time 31544825439 ps
CPU time 1704.21 seconds
Started Jul 01 05:19:26 PM PDT 24
Finished Jul 01 05:47:54 PM PDT 24
Peak memory 282260 kb
Host smart-985edd95-9525-42fb-ac38-b3baa74338d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309829486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.309829486
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2918105745
Short name T71
Test name
Test status
Simulation time 272618645479 ps
CPU time 1501.49 seconds
Started Jul 01 05:19:23 PM PDT 24
Finished Jul 01 05:44:28 PM PDT 24
Peak memory 273516 kb
Host smart-d194b3d0-3b36-42bc-b17f-3402d23e81cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918105745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2918105745
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.467387820
Short name T419
Test name
Test status
Simulation time 3446248576 ps
CPU time 114.49 seconds
Started Jul 01 05:19:24 PM PDT 24
Finished Jul 01 05:21:22 PM PDT 24
Peak memory 257636 kb
Host smart-8dbf5362-a3ee-483c-951e-3e99008711a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46738
7820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.467387820
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3642188167
Short name T532
Test name
Test status
Simulation time 169687460 ps
CPU time 10.94 seconds
Started Jul 01 05:19:23 PM PDT 24
Finished Jul 01 05:19:37 PM PDT 24
Peak memory 257576 kb
Host smart-d58337fc-38b7-4f95-966e-4961ee5ac2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36421
88167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3642188167
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2517004924
Short name T309
Test name
Test status
Simulation time 30254580522 ps
CPU time 1647.28 seconds
Started Jul 01 05:19:26 PM PDT 24
Finished Jul 01 05:46:57 PM PDT 24
Peak memory 274004 kb
Host smart-4334a879-8a0a-4349-9523-57162aee66d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517004924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2517004924
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.767820076
Short name T453
Test name
Test status
Simulation time 97883532608 ps
CPU time 1380.17 seconds
Started Jul 01 05:19:27 PM PDT 24
Finished Jul 01 05:42:31 PM PDT 24
Peak memory 272852 kb
Host smart-f5a8fc77-9ee3-4847-b89c-d0a499ae3cda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767820076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.767820076
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1416365055
Short name T671
Test name
Test status
Simulation time 25308474664 ps
CPU time 273.11 seconds
Started Jul 01 05:19:23 PM PDT 24
Finished Jul 01 05:23:59 PM PDT 24
Peak memory 249472 kb
Host smart-d33872f1-f232-4f92-b419-e3dfb50c4bad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416365055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1416365055
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3253319601
Short name T622
Test name
Test status
Simulation time 269155878 ps
CPU time 26.53 seconds
Started Jul 01 05:19:25 PM PDT 24
Finished Jul 01 05:19:56 PM PDT 24
Peak memory 249260 kb
Host smart-07de575b-f224-4342-b426-4363fbb829b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32533
19601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3253319601
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3339444165
Short name T641
Test name
Test status
Simulation time 901341639 ps
CPU time 33.16 seconds
Started Jul 01 05:19:26 PM PDT 24
Finished Jul 01 05:20:03 PM PDT 24
Peak memory 248464 kb
Host smart-1ce6208c-9154-4faf-8d7a-5145e96209fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33394
44165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3339444165
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2468204378
Short name T502
Test name
Test status
Simulation time 106087692 ps
CPU time 4.27 seconds
Started Jul 01 05:19:25 PM PDT 24
Finished Jul 01 05:19:32 PM PDT 24
Peak memory 252276 kb
Host smart-b44f29f8-4ca8-4e7b-8669-552126de0caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24682
04378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2468204378
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1935902044
Short name T112
Test name
Test status
Simulation time 165024369130 ps
CPU time 2803.36 seconds
Started Jul 01 05:19:23 PM PDT 24
Finished Jul 01 06:06:10 PM PDT 24
Peak memory 284680 kb
Host smart-489f181e-e31f-4995-a5f3-402d80a70e72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935902044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1935902044
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.64368060
Short name T424
Test name
Test status
Simulation time 575982822 ps
CPU time 31.3 seconds
Started Jul 01 05:19:24 PM PDT 24
Finished Jul 01 05:19:58 PM PDT 24
Peak memory 257496 kb
Host smart-31fa3865-bd8b-4f83-8e6b-c669dcbf733f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64368
060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.64368060
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1866442508
Short name T379
Test name
Test status
Simulation time 1547183665 ps
CPU time 40.66 seconds
Started Jul 01 05:19:22 PM PDT 24
Finished Jul 01 05:20:06 PM PDT 24
Peak memory 257040 kb
Host smart-eb697122-ddfc-4f92-a942-bcef8e823a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664
42508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1866442508
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.839134291
Short name T347
Test name
Test status
Simulation time 393171875294 ps
CPU time 2867.57 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 06:07:24 PM PDT 24
Peak memory 289808 kb
Host smart-301a662c-25ac-4fa5-ab65-5c028876e9a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839134291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.839134291
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3162810295
Short name T542
Test name
Test status
Simulation time 15577315743 ps
CPU time 1001.9 seconds
Started Jul 01 05:19:34 PM PDT 24
Finished Jul 01 05:36:20 PM PDT 24
Peak memory 265844 kb
Host smart-36f7379e-a0a0-44fe-9911-cfaebbed3894
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162810295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3162810295
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1016836357
Short name T337
Test name
Test status
Simulation time 38879879248 ps
CPU time 342.61 seconds
Started Jul 01 05:19:23 PM PDT 24
Finished Jul 01 05:25:09 PM PDT 24
Peak memory 248288 kb
Host smart-37e0ab91-c064-446e-9809-e8a7df7bb8a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016836357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1016836357
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.867233452
Short name T625
Test name
Test status
Simulation time 323487379 ps
CPU time 21.7 seconds
Started Jul 01 05:19:24 PM PDT 24
Finished Jul 01 05:19:49 PM PDT 24
Peak memory 249232 kb
Host smart-0e4317ea-d9ba-4549-8b4b-92a0a54282b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86723
3452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.867233452
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2754576010
Short name T24
Test name
Test status
Simulation time 1826634576 ps
CPU time 62.35 seconds
Started Jul 01 05:19:26 PM PDT 24
Finished Jul 01 05:20:32 PM PDT 24
Peak memory 249248 kb
Host smart-57cd81a1-1b93-4969-aa66-dd15fd7d983d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27545
76010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2754576010
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3333558895
Short name T439
Test name
Test status
Simulation time 3260603828 ps
CPU time 59.74 seconds
Started Jul 01 05:19:24 PM PDT 24
Finished Jul 01 05:20:27 PM PDT 24
Peak memory 250344 kb
Host smart-9eb49d73-0e88-4b1c-9628-f244b81df999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33335
58895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3333558895
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3366035587
Short name T230
Test name
Test status
Simulation time 2191256664 ps
CPU time 65.77 seconds
Started Jul 01 05:19:25 PM PDT 24
Finished Jul 01 05:20:35 PM PDT 24
Peak memory 256704 kb
Host smart-916f2353-e1fd-4e0c-b92b-0316725b2526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33660
35587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3366035587
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2845789391
Short name T271
Test name
Test status
Simulation time 13604231264 ps
CPU time 753.13 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:32:08 PM PDT 24
Peak memory 265832 kb
Host smart-460b2331-4b43-4ec4-8eb1-600e05f22bbc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845789391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2845789391
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.848190547
Short name T184
Test name
Test status
Simulation time 46210127 ps
CPU time 2.59 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:18:08 PM PDT 24
Peak memory 249524 kb
Host smart-4ee84f8d-e07d-4f6d-a8de-0de9e53abedc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=848190547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.848190547
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3309893094
Short name T586
Test name
Test status
Simulation time 131588805416 ps
CPU time 2266.67 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:55:52 PM PDT 24
Peak memory 282260 kb
Host smart-58bc8040-e985-44a0-bcb6-12e16c1d5fd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309893094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3309893094
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2826610084
Short name T451
Test name
Test status
Simulation time 821360013 ps
CPU time 31.76 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:18:36 PM PDT 24
Peak memory 249328 kb
Host smart-91bec895-ed87-42b1-8aca-435ce8aa6e89
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2826610084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2826610084
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2708011802
Short name T656
Test name
Test status
Simulation time 3375588304 ps
CPU time 131.79 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:20:20 PM PDT 24
Peak memory 257008 kb
Host smart-32cead9f-7d5e-4013-b383-bbc848345937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080
11802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2708011802
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.580120847
Short name T665
Test name
Test status
Simulation time 990736310 ps
CPU time 34.96 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:45 PM PDT 24
Peak memory 248816 kb
Host smart-ba3ec34b-baf4-44bb-b8dc-55635e45e385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58012
0847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.580120847
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1385805923
Short name T583
Test name
Test status
Simulation time 44286100708 ps
CPU time 1659.17 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:45:47 PM PDT 24
Peak memory 273920 kb
Host smart-a84e8a82-9315-4974-8d87-be2b85a5787b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385805923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1385805923
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2135600406
Short name T434
Test name
Test status
Simulation time 42778884579 ps
CPU time 2483.14 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:59:34 PM PDT 24
Peak memory 287188 kb
Host smart-99b3ac87-fc07-4d70-b507-e3ee901d1dc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135600406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2135600406
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.13893995
Short name T659
Test name
Test status
Simulation time 1095656823 ps
CPU time 68.27 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:19:16 PM PDT 24
Peak memory 249340 kb
Host smart-e01b368d-bdb7-41f7-80b5-8e6b63a0d6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13893
995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.13893995
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4283180012
Short name T413
Test name
Test status
Simulation time 155259143 ps
CPU time 17.48 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:18:22 PM PDT 24
Peak memory 257232 kb
Host smart-85041569-73bc-4fbb-8a29-a1761cba4850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42831
80012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4283180012
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2406158851
Short name T33
Test name
Test status
Simulation time 878559844 ps
CPU time 13.97 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:18:22 PM PDT 24
Peak memory 271388 kb
Host smart-1c8ff35b-c6ed-4ed3-8be9-8d6e0000b923
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2406158851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2406158851
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2797064359
Short name T46
Test name
Test status
Simulation time 1243602732 ps
CPU time 11.49 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:22 PM PDT 24
Peak memory 249336 kb
Host smart-76c4b25e-259b-458f-a118-f27f54a91d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27970
64359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2797064359
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.658652155
Short name T227
Test name
Test status
Simulation time 204411742 ps
CPU time 5.06 seconds
Started Jul 01 05:17:58 PM PDT 24
Finished Jul 01 05:18:06 PM PDT 24
Peak memory 251616 kb
Host smart-972e6790-a48e-43fd-b40d-787d5848814b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65865
2155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.658652155
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3838427631
Short name T305
Test name
Test status
Simulation time 231665747797 ps
CPU time 3369.65 seconds
Started Jul 01 05:18:05 PM PDT 24
Finished Jul 01 06:14:19 PM PDT 24
Peak memory 290204 kb
Host smart-80b6f675-83b8-4093-ba92-24df73cc703d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838427631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3838427631
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3651132252
Short name T56
Test name
Test status
Simulation time 397333472352 ps
CPU time 4741.29 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 06:37:07 PM PDT 24
Peak memory 321844 kb
Host smart-e7df2a7b-2612-4a75-9f71-8a1029fae814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651132252 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3651132252
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.149559397
Short name T537
Test name
Test status
Simulation time 558362007 ps
CPU time 19.05 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:19:55 PM PDT 24
Peak memory 254928 kb
Host smart-f7e771a9-66f1-4cf7-bc76-c409f18c6317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
9397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.149559397
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4010912664
Short name T276
Test name
Test status
Simulation time 7096030942 ps
CPU time 56.72 seconds
Started Jul 01 05:19:35 PM PDT 24
Finished Jul 01 05:20:35 PM PDT 24
Peak memory 257512 kb
Host smart-f7def7d6-da6e-4f3f-b84f-7338ab417e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
12664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4010912664
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4213303195
Short name T78
Test name
Test status
Simulation time 114230915904 ps
CPU time 1431.74 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:43:29 PM PDT 24
Peak memory 273112 kb
Host smart-4be7b8dd-65e4-4a5c-b35c-c4a87fbb3f6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213303195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4213303195
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2905594486
Short name T5
Test name
Test status
Simulation time 18172952034 ps
CPU time 1038.3 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:36:53 PM PDT 24
Peak memory 272860 kb
Host smart-233768f1-e1fc-461d-8d7f-6e0b4efd638a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905594486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2905594486
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3374666169
Short name T70
Test name
Test status
Simulation time 10314674920 ps
CPU time 426.18 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:26:42 PM PDT 24
Peak memory 255916 kb
Host smart-e8a26ac3-8abf-4a16-83c6-478a096545fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374666169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3374666169
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3319111221
Short name T12
Test name
Test status
Simulation time 3339082602 ps
CPU time 60.79 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:20:36 PM PDT 24
Peak memory 256900 kb
Host smart-773e0ff2-4928-4f0f-b5a2-55bfc916f0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33191
11221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3319111221
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.125940784
Short name T400
Test name
Test status
Simulation time 3315677892 ps
CPU time 47.15 seconds
Started Jul 01 05:19:34 PM PDT 24
Finished Jul 01 05:20:25 PM PDT 24
Peak memory 249436 kb
Host smart-16c3dffd-bbc2-4063-8127-0c68ccc0f1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12594
0784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.125940784
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1544713498
Short name T632
Test name
Test status
Simulation time 65993384 ps
CPU time 7.65 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:19:44 PM PDT 24
Peak memory 255256 kb
Host smart-38f20424-bdb6-42e0-8a27-eace8b4088aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15447
13498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1544713498
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1146176270
Short name T372
Test name
Test status
Simulation time 22645038 ps
CPU time 3.57 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:19:39 PM PDT 24
Peak memory 251320 kb
Host smart-576b54df-20f5-44cb-8138-0003ce4154a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11461
76270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1146176270
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.660341295
Short name T275
Test name
Test status
Simulation time 43395437727 ps
CPU time 2462.77 seconds
Started Jul 01 05:19:31 PM PDT 24
Finished Jul 01 06:00:36 PM PDT 24
Peak memory 290348 kb
Host smart-5552aa27-26b8-4cf8-9e4f-c0b179c8d6fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660341295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.660341295
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.366831480
Short name T60
Test name
Test status
Simulation time 6682856224 ps
CPU time 758.73 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:32:16 PM PDT 24
Peak memory 273664 kb
Host smart-5df79fec-59ca-47a1-a831-03de6b11b4fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366831480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.366831480
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1001301871
Short name T410
Test name
Test status
Simulation time 1869343272 ps
CPU time 105.62 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:21:21 PM PDT 24
Peak memory 256980 kb
Host smart-b50c4ce1-ef4a-43eb-95a4-222fb4af7fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
01871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1001301871
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1256733757
Short name T699
Test name
Test status
Simulation time 1638222130 ps
CPU time 48.45 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:20:25 PM PDT 24
Peak memory 249404 kb
Host smart-0239b4f1-ca34-4a18-90a1-8b57cfbfdb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12567
33757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1256733757
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2407024104
Short name T460
Test name
Test status
Simulation time 12543715243 ps
CPU time 1186.84 seconds
Started Jul 01 05:19:31 PM PDT 24
Finished Jul 01 05:39:20 PM PDT 24
Peak memory 284076 kb
Host smart-7c1025f0-de24-4496-bce4-2e5816b7dd48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407024104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2407024104
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1500691999
Short name T328
Test name
Test status
Simulation time 12075114967 ps
CPU time 243.83 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:23:41 PM PDT 24
Peak memory 249408 kb
Host smart-9be169ad-c9f6-4195-b45d-c7933e744c10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500691999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1500691999
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.261401356
Short name T650
Test name
Test status
Simulation time 486650143 ps
CPU time 29.82 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:20:07 PM PDT 24
Peak memory 249324 kb
Host smart-e65a02e0-b8ff-4f7a-9dcf-05964377869d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26140
1356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.261401356
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3204831439
Short name T66
Test name
Test status
Simulation time 4031528819 ps
CPU time 67.83 seconds
Started Jul 01 05:19:34 PM PDT 24
Finished Jul 01 05:20:46 PM PDT 24
Peak memory 257628 kb
Host smart-b9a7e08d-4b27-4ee0-9a46-b92a753f3b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32048
31439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3204831439
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1447051081
Short name T552
Test name
Test status
Simulation time 228952146 ps
CPU time 23.96 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:20:01 PM PDT 24
Peak memory 249404 kb
Host smart-969c4fbe-8ba4-4603-869f-6c0d9a31c120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470
51081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1447051081
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.991265121
Short name T657
Test name
Test status
Simulation time 100754041 ps
CPU time 11.44 seconds
Started Jul 01 05:19:32 PM PDT 24
Finished Jul 01 05:19:47 PM PDT 24
Peak memory 255652 kb
Host smart-5968b2a0-7d56-4dd4-94d9-f8221a6445dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99126
5121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.991265121
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.97334615
Short name T511
Test name
Test status
Simulation time 173069096703 ps
CPU time 2797.93 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 06:06:15 PM PDT 24
Peak memory 300268 kb
Host smart-3b9401a8-c1ca-41d2-9cc2-f03270e5ced2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97334615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_hand
ler_stress_all.97334615
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1762902256
Short name T291
Test name
Test status
Simulation time 427577966647 ps
CPU time 7305.59 seconds
Started Jul 01 05:19:31 PM PDT 24
Finished Jul 01 07:21:21 PM PDT 24
Peak memory 368964 kb
Host smart-2870a563-6dd8-49be-aacf-b3c024eacdde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762902256 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1762902256
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3671134792
Short name T457
Test name
Test status
Simulation time 211951507991 ps
CPU time 2708.98 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 06:04:55 PM PDT 24
Peak memory 290168 kb
Host smart-b8d5f6d4-406e-4962-80cb-4c2044cb8dde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671134792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3671134792
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3821607442
Short name T639
Test name
Test status
Simulation time 10294279373 ps
CPU time 94.17 seconds
Started Jul 01 05:19:43 PM PDT 24
Finished Jul 01 05:21:22 PM PDT 24
Peak memory 257464 kb
Host smart-051e5d31-8bcb-4187-a08a-d6b3ef6766b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38216
07442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3821607442
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3029109014
Short name T485
Test name
Test status
Simulation time 3200891082 ps
CPU time 31.24 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:20:17 PM PDT 24
Peak memory 256856 kb
Host smart-68c33c75-ea16-49fb-b9cc-cb079571ba81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
09014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3029109014
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1968646806
Short name T67
Test name
Test status
Simulation time 73781667705 ps
CPU time 1122.45 seconds
Started Jul 01 05:19:40 PM PDT 24
Finished Jul 01 05:38:27 PM PDT 24
Peak memory 274004 kb
Host smart-9a93294d-45ef-488a-9889-598a15d4491e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968646806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1968646806
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1443229666
Short name T40
Test name
Test status
Simulation time 143042795805 ps
CPU time 2048.38 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:53:54 PM PDT 24
Peak memory 289424 kb
Host smart-de499e87-7674-4a27-a100-2391836e739f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443229666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1443229666
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2991027355
Short name T380
Test name
Test status
Simulation time 189234485 ps
CPU time 19.18 seconds
Started Jul 01 05:19:43 PM PDT 24
Finished Jul 01 05:20:07 PM PDT 24
Peak memory 256600 kb
Host smart-b5c96468-9345-434d-a35b-ab6ac52c698f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29910
27355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2991027355
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.837557010
Short name T689
Test name
Test status
Simulation time 782443465 ps
CPU time 26.75 seconds
Started Jul 01 05:19:42 PM PDT 24
Finished Jul 01 05:20:14 PM PDT 24
Peak memory 249284 kb
Host smart-ec555195-6224-4880-8a18-fb41d28d636a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83755
7010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.837557010
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2400378659
Short name T673
Test name
Test status
Simulation time 1676279403 ps
CPU time 54.31 seconds
Started Jul 01 05:19:40 PM PDT 24
Finished Jul 01 05:20:38 PM PDT 24
Peak memory 256820 kb
Host smart-cecd72d7-4174-4fd2-9450-dea852cf9320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24003
78659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2400378659
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2254220099
Short name T510
Test name
Test status
Simulation time 1986951755 ps
CPU time 42.11 seconds
Started Jul 01 05:19:33 PM PDT 24
Finished Jul 01 05:20:19 PM PDT 24
Peak memory 257484 kb
Host smart-562e710a-73d6-45dc-b34c-149e150c0329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22542
20099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2254220099
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.507703525
Short name T199
Test name
Test status
Simulation time 34168773089 ps
CPU time 2527.51 seconds
Started Jul 01 05:19:47 PM PDT 24
Finished Jul 01 06:02:00 PM PDT 24
Peak memory 300484 kb
Host smart-cffe6748-2465-4307-8648-7cfc709faba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507703525 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.507703525
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3783917487
Short name T59
Test name
Test status
Simulation time 104885236525 ps
CPU time 1564.18 seconds
Started Jul 01 05:19:40 PM PDT 24
Finished Jul 01 05:45:48 PM PDT 24
Peak memory 273208 kb
Host smart-8caedf86-7709-488c-9abe-7ba83cb4a48d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783917487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3783917487
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1955759539
Short name T396
Test name
Test status
Simulation time 3888564494 ps
CPU time 260.48 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:24:06 PM PDT 24
Peak memory 257080 kb
Host smart-29b3ad23-a39a-4f7e-96a4-7db6d4571ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19557
59539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1955759539
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1147425793
Short name T623
Test name
Test status
Simulation time 19790277534 ps
CPU time 1302.69 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:41:28 PM PDT 24
Peak memory 272980 kb
Host smart-139c6c6a-3037-4e5c-8a78-e4fda9961cee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147425793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1147425793
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3364467254
Short name T314
Test name
Test status
Simulation time 57774013686 ps
CPU time 432.26 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:26:57 PM PDT 24
Peak memory 257412 kb
Host smart-0987ced9-6183-4f10-a09a-18b7b9eeba50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364467254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3364467254
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3509361928
Short name T421
Test name
Test status
Simulation time 889628102 ps
CPU time 29.76 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:20:15 PM PDT 24
Peak memory 249228 kb
Host smart-3ccbfd91-9914-4f8c-b14b-aba68babcedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35093
61928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3509361928
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1807094527
Short name T592
Test name
Test status
Simulation time 2539537461 ps
CPU time 37.51 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:20:23 PM PDT 24
Peak memory 257028 kb
Host smart-aeefaa8f-64a4-40ae-9974-078b4a9faf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070
94527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1807094527
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2577969381
Short name T41
Test name
Test status
Simulation time 761262270 ps
CPU time 19.67 seconds
Started Jul 01 05:19:39 PM PDT 24
Finished Jul 01 05:20:01 PM PDT 24
Peak memory 248404 kb
Host smart-740e5982-965b-4535-b602-4519e7bf57b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
69381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2577969381
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4259331981
Short name T603
Test name
Test status
Simulation time 2043919415 ps
CPU time 28.97 seconds
Started Jul 01 05:19:40 PM PDT 24
Finished Jul 01 05:20:12 PM PDT 24
Peak memory 249224 kb
Host smart-4b95170a-32ae-4f95-8da4-96abc4ad69b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42593
31981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4259331981
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2157866022
Short name T267
Test name
Test status
Simulation time 91132957998 ps
CPU time 2691.84 seconds
Started Jul 01 05:19:42 PM PDT 24
Finished Jul 01 06:04:39 PM PDT 24
Peak memory 289260 kb
Host smart-4baf9f14-982c-486d-8aae-151f44a64251
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157866022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2157866022
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3072391866
Short name T530
Test name
Test status
Simulation time 32790700185 ps
CPU time 1898.12 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:51:31 PM PDT 24
Peak memory 273828 kb
Host smart-e99e3b9e-332d-4760-a0de-7b6bad24a06e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072391866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3072391866
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.985446565
Short name T387
Test name
Test status
Simulation time 7102277819 ps
CPU time 278.21 seconds
Started Jul 01 05:19:42 PM PDT 24
Finished Jul 01 05:24:25 PM PDT 24
Peak memory 257684 kb
Host smart-7d0533a8-385f-4f8f-8897-df5fd7a6f3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98544
6565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.985446565
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3020542368
Short name T390
Test name
Test status
Simulation time 562633752 ps
CPU time 25.52 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:20:11 PM PDT 24
Peak memory 249392 kb
Host smart-d2b43f42-6e7f-404d-ba36-8e0c67be8446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30205
42368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3020542368
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3651707225
Short name T528
Test name
Test status
Simulation time 59927610694 ps
CPU time 1538.59 seconds
Started Jul 01 05:19:47 PM PDT 24
Finished Jul 01 05:45:30 PM PDT 24
Peak memory 289992 kb
Host smart-c235bee1-4528-4371-a67c-3259d7a25187
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651707225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3651707225
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.948569491
Short name T316
Test name
Test status
Simulation time 3184823454 ps
CPU time 145.95 seconds
Started Jul 01 05:19:45 PM PDT 24
Finished Jul 01 05:22:16 PM PDT 24
Peak memory 256200 kb
Host smart-9f01c9bf-c472-487a-a813-ff9cc31b4dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948569491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.948569491
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.471350773
Short name T26
Test name
Test status
Simulation time 6702332612 ps
CPU time 59.2 seconds
Started Jul 01 05:19:41 PM PDT 24
Finished Jul 01 05:20:44 PM PDT 24
Peak memory 257560 kb
Host smart-4fc8f3c1-1471-4ed8-98a7-4e6ff9fbc846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47135
0773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.471350773
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1251181340
Short name T119
Test name
Test status
Simulation time 1173920846 ps
CPU time 35.97 seconds
Started Jul 01 05:19:43 PM PDT 24
Finished Jul 01 05:20:23 PM PDT 24
Peak memory 248600 kb
Host smart-e2d94154-0276-4ea6-aa57-822c13b5ea45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12511
81340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1251181340
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3135723195
Short name T615
Test name
Test status
Simulation time 106617695 ps
CPU time 12.14 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:20:06 PM PDT 24
Peak memory 249332 kb
Host smart-5823c8e5-613b-4450-8c2c-2c925f64a572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
23195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3135723195
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1156343369
Short name T378
Test name
Test status
Simulation time 737253374 ps
CPU time 44.9 seconds
Started Jul 01 05:19:40 PM PDT 24
Finished Jul 01 05:20:28 PM PDT 24
Peak memory 257468 kb
Host smart-44c60d42-1852-4301-802a-4d4d025b351a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11563
43369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1156343369
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2631169462
Short name T279
Test name
Test status
Simulation time 53971654617 ps
CPU time 820.04 seconds
Started Jul 01 05:19:49 PM PDT 24
Finished Jul 01 05:33:34 PM PDT 24
Peak memory 283292 kb
Host smart-3211d920-ac13-4771-8aca-462f84fe6973
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631169462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2631169462
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.202677280
Short name T1
Test name
Test status
Simulation time 28579259185 ps
CPU time 1601.09 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:46:34 PM PDT 24
Peak memory 273856 kb
Host smart-308f339b-d688-408a-973d-452bea86df5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202677280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.202677280
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4269589177
Short name T239
Test name
Test status
Simulation time 6690997419 ps
CPU time 168.79 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:22:42 PM PDT 24
Peak memory 251484 kb
Host smart-942cc8d1-5ce6-4d14-8eb9-1116bca50536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42695
89177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4269589177
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.4000509536
Short name T268
Test name
Test status
Simulation time 874377547 ps
CPU time 46.83 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:20:39 PM PDT 24
Peak memory 249232 kb
Host smart-e5f4fec1-5a1f-4df4-8832-1d86c7b8db86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40005
09536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.4000509536
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.716417334
Short name T321
Test name
Test status
Simulation time 9513088573 ps
CPU time 713.63 seconds
Started Jul 01 05:19:47 PM PDT 24
Finished Jul 01 05:31:45 PM PDT 24
Peak memory 273408 kb
Host smart-bcb2c00a-5edf-4df6-b569-3102019653e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716417334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.716417334
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2264666326
Short name T289
Test name
Test status
Simulation time 165232954481 ps
CPU time 1830.68 seconds
Started Jul 01 05:19:46 PM PDT 24
Finished Jul 01 05:50:22 PM PDT 24
Peak memory 273692 kb
Host smart-ad2db588-abb5-4349-a740-8f9de09abc8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264666326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2264666326
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.430691825
Short name T555
Test name
Test status
Simulation time 2562127965 ps
CPU time 106.46 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:21:39 PM PDT 24
Peak memory 248272 kb
Host smart-82b946f2-6fb1-460c-8c17-b31c490c0db1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430691825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.430691825
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.648538513
Short name T637
Test name
Test status
Simulation time 321274242 ps
CPU time 5.85 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:19:59 PM PDT 24
Peak memory 251548 kb
Host smart-b7fcbdce-a6d2-49aa-a4eb-57d425b6872c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64853
8513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.648538513
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3452390247
Short name T678
Test name
Test status
Simulation time 295431943 ps
CPU time 8.75 seconds
Started Jul 01 05:19:47 PM PDT 24
Finished Jul 01 05:20:00 PM PDT 24
Peak memory 249460 kb
Host smart-447381c2-2252-4a65-ac70-88176b63901e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34523
90247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3452390247
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.178262174
Short name T589
Test name
Test status
Simulation time 2301680075 ps
CPU time 34.15 seconds
Started Jul 01 05:19:46 PM PDT 24
Finished Jul 01 05:20:25 PM PDT 24
Peak memory 249928 kb
Host smart-aaca0c8c-7c1a-4dc7-b266-6af9e87b91a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17826
2174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.178262174
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2928834038
Short name T50
Test name
Test status
Simulation time 570735565 ps
CPU time 14.97 seconds
Started Jul 01 05:19:49 PM PDT 24
Finished Jul 01 05:20:09 PM PDT 24
Peak memory 256680 kb
Host smart-8b9d9b1b-6923-4ee8-80eb-ad6e658c4dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
34038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2928834038
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3049488282
Short name T593
Test name
Test status
Simulation time 40936886209 ps
CPU time 2693.46 seconds
Started Jul 01 05:19:47 PM PDT 24
Finished Jul 01 06:04:45 PM PDT 24
Peak memory 286000 kb
Host smart-58184693-37c6-427e-99a7-284965571f25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049488282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3049488282
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1809411324
Short name T435
Test name
Test status
Simulation time 146509901003 ps
CPU time 2483.58 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 06:01:17 PM PDT 24
Peak memory 273928 kb
Host smart-adaf5b56-6d04-403f-9a7e-91b90c8a7d86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809411324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1809411324
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3201739679
Short name T394
Test name
Test status
Simulation time 179881024 ps
CPU time 12.87 seconds
Started Jul 01 05:19:45 PM PDT 24
Finished Jul 01 05:20:03 PM PDT 24
Peak memory 255332 kb
Host smart-c338de3d-2453-47c8-bb04-0e47a4a979b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017
39679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3201739679
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3229863672
Short name T454
Test name
Test status
Simulation time 301146500 ps
CPU time 20.5 seconds
Started Jul 01 05:19:46 PM PDT 24
Finished Jul 01 05:20:12 PM PDT 24
Peak memory 256496 kb
Host smart-d6228de4-6d27-4463-b6c8-4ee2d0c439a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32298
63672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3229863672
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2887402312
Short name T423
Test name
Test status
Simulation time 28222914976 ps
CPU time 2094.21 seconds
Started Jul 01 05:19:54 PM PDT 24
Finished Jul 01 05:54:53 PM PDT 24
Peak memory 285768 kb
Host smart-d6cd4734-2bfc-46b2-ac9b-aec499d2ea70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887402312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2887402312
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2197997966
Short name T8
Test name
Test status
Simulation time 56446175844 ps
CPU time 385.23 seconds
Started Jul 01 05:19:49 PM PDT 24
Finished Jul 01 05:26:19 PM PDT 24
Peak memory 249240 kb
Host smart-dbdd56c2-75d0-42e1-b2a4-e4a5fa8b8283
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197997966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2197997966
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3980069352
Short name T709
Test name
Test status
Simulation time 850566351 ps
CPU time 33.9 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:20:27 PM PDT 24
Peak memory 256780 kb
Host smart-3990bbcd-5fdc-4fca-9358-f5dc94bdb90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39800
69352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3980069352
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3201136547
Short name T16
Test name
Test status
Simulation time 259278377 ps
CPU time 7.08 seconds
Started Jul 01 05:19:49 PM PDT 24
Finished Jul 01 05:20:01 PM PDT 24
Peak memory 249364 kb
Host smart-554f5437-bc93-408a-ae3a-9faf1f733984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32011
36547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3201136547
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1379138737
Short name T483
Test name
Test status
Simulation time 1083989858 ps
CPU time 58.73 seconds
Started Jul 01 05:19:48 PM PDT 24
Finished Jul 01 05:20:51 PM PDT 24
Peak memory 248836 kb
Host smart-93a8289d-558b-42c2-978e-9d3f3a64bc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13791
38737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1379138737
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.661383224
Short name T658
Test name
Test status
Simulation time 56593633 ps
CPU time 4.94 seconds
Started Jul 01 05:19:47 PM PDT 24
Finished Jul 01 05:19:57 PM PDT 24
Peak memory 251444 kb
Host smart-f4b9aaaa-eec0-4b55-a0da-957f7c2d1e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66138
3224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.661383224
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1589749403
Short name T507
Test name
Test status
Simulation time 32335961246 ps
CPU time 2033.29 seconds
Started Jul 01 05:19:53 PM PDT 24
Finished Jul 01 05:53:52 PM PDT 24
Peak memory 290336 kb
Host smart-f1daadd2-6e35-4c68-a15a-009e3571d986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589749403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1589749403
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3022420599
Short name T602
Test name
Test status
Simulation time 969265874 ps
CPU time 35.27 seconds
Started Jul 01 05:19:53 PM PDT 24
Finished Jul 01 05:20:33 PM PDT 24
Peak memory 256988 kb
Host smart-50748b04-9ae6-413b-9857-0d75acc3d621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30224
20599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3022420599
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.342996363
Short name T375
Test name
Test status
Simulation time 240083151 ps
CPU time 9.9 seconds
Started Jul 01 05:19:54 PM PDT 24
Finished Jul 01 05:20:09 PM PDT 24
Peak memory 254180 kb
Host smart-2d9282b3-819f-40b7-aa90-8e0b6a964d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34299
6363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.342996363
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4088256814
Short name T350
Test name
Test status
Simulation time 24976096677 ps
CPU time 1178.92 seconds
Started Jul 01 05:19:56 PM PDT 24
Finished Jul 01 05:39:39 PM PDT 24
Peak memory 286620 kb
Host smart-445b655a-37cf-49bd-ab5a-e967c1385613
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088256814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4088256814
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2213982531
Short name T561
Test name
Test status
Simulation time 116147749175 ps
CPU time 1724.56 seconds
Started Jul 01 05:19:56 PM PDT 24
Finished Jul 01 05:48:45 PM PDT 24
Peak memory 273972 kb
Host smart-0e84ad08-3400-4cc3-a98d-568af6b5179b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213982531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2213982531
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2115311401
Short name T620
Test name
Test status
Simulation time 139142853 ps
CPU time 17.94 seconds
Started Jul 01 05:19:53 PM PDT 24
Finished Jul 01 05:20:16 PM PDT 24
Peak memory 249368 kb
Host smart-f0d22066-58ae-46ce-857a-dda8d92316f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21153
11401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2115311401
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.831131215
Short name T383
Test name
Test status
Simulation time 43190800 ps
CPU time 3.33 seconds
Started Jul 01 05:19:52 PM PDT 24
Finished Jul 01 05:20:00 PM PDT 24
Peak memory 240304 kb
Host smart-d046574b-0703-41c7-9ddc-4ea17c8477c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83113
1215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.831131215
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3857603815
Short name T597
Test name
Test status
Simulation time 107245810 ps
CPU time 17.45 seconds
Started Jul 01 05:19:52 PM PDT 24
Finished Jul 01 05:20:15 PM PDT 24
Peak memory 248768 kb
Host smart-afa8f89f-d5ef-4e4a-91b0-cee8d761a563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576
03815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3857603815
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.127398427
Short name T499
Test name
Test status
Simulation time 67550714 ps
CPU time 6.61 seconds
Started Jul 01 05:19:56 PM PDT 24
Finished Jul 01 05:20:07 PM PDT 24
Peak memory 249276 kb
Host smart-75bffe5c-71e2-45b7-8430-e849c37f184d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12739
8427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.127398427
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.733074227
Short name T606
Test name
Test status
Simulation time 135186993077 ps
CPU time 1283.07 seconds
Started Jul 01 05:19:56 PM PDT 24
Finished Jul 01 05:41:23 PM PDT 24
Peak memory 289360 kb
Host smart-e7c30c1d-de6e-4c69-9fef-484881f583bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733074227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.733074227
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3275749568
Short name T62
Test name
Test status
Simulation time 30671888367 ps
CPU time 1826.75 seconds
Started Jul 01 05:20:01 PM PDT 24
Finished Jul 01 05:50:31 PM PDT 24
Peak memory 273924 kb
Host smart-e567a281-46e6-457a-b7cc-5409835fdff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275749568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3275749568
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3467417936
Short name T626
Test name
Test status
Simulation time 2022499733 ps
CPU time 86.7 seconds
Started Jul 01 05:19:54 PM PDT 24
Finished Jul 01 05:21:26 PM PDT 24
Peak memory 257528 kb
Host smart-7e980c20-9da1-4055-8284-387cb1931da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674
17936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3467417936
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.397306020
Short name T84
Test name
Test status
Simulation time 798671062 ps
CPU time 35.72 seconds
Started Jul 01 05:19:52 PM PDT 24
Finished Jul 01 05:20:33 PM PDT 24
Peak memory 249332 kb
Host smart-69353ec9-72f6-482d-a24f-528d9364fb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39730
6020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.397306020
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.576948892
Short name T669
Test name
Test status
Simulation time 30288804678 ps
CPU time 1981.8 seconds
Started Jul 01 05:20:01 PM PDT 24
Finished Jul 01 05:53:07 PM PDT 24
Peak memory 285536 kb
Host smart-e9ddea76-60aa-42aa-b652-f7b75d97d318
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576948892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.576948892
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3964205562
Short name T580
Test name
Test status
Simulation time 223964826734 ps
CPU time 453.48 seconds
Started Jul 01 05:20:01 PM PDT 24
Finished Jul 01 05:27:39 PM PDT 24
Peak memory 249464 kb
Host smart-0980ecbc-e785-4d8d-b3f5-67d4a57a00d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964205562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3964205562
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.926878367
Short name T495
Test name
Test status
Simulation time 881858069 ps
CPU time 26.51 seconds
Started Jul 01 05:19:53 PM PDT 24
Finished Jul 01 05:20:24 PM PDT 24
Peak memory 256816 kb
Host smart-41deb4b5-fa4d-4550-bc18-1b884061787a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92687
8367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.926878367
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.314259968
Short name T698
Test name
Test status
Simulation time 591439586 ps
CPU time 38.64 seconds
Started Jul 01 05:19:53 PM PDT 24
Finished Jul 01 05:20:37 PM PDT 24
Peak memory 257300 kb
Host smart-d2ad4864-8fd3-4019-8804-f4b09ff950d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31425
9968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.314259968
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2968477518
Short name T250
Test name
Test status
Simulation time 2868644090 ps
CPU time 50.05 seconds
Started Jul 01 05:20:01 PM PDT 24
Finished Jul 01 05:20:56 PM PDT 24
Peak memory 257032 kb
Host smart-b182ed89-8e82-4eb0-ab8d-0a270c7a33f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29684
77518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2968477518
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1791076592
Short name T679
Test name
Test status
Simulation time 791667229 ps
CPU time 13.85 seconds
Started Jul 01 05:19:54 PM PDT 24
Finished Jul 01 05:20:13 PM PDT 24
Peak memory 255336 kb
Host smart-a9a6aae0-27e5-4fb1-a754-539488ab0059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17910
76592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1791076592
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4287760720
Short name T117
Test name
Test status
Simulation time 116831195887 ps
CPU time 1921.85 seconds
Started Jul 01 05:20:00 PM PDT 24
Finished Jul 01 05:52:05 PM PDT 24
Peak memory 306784 kb
Host smart-329b4c10-3c44-41f1-9281-1df0e2d7c161
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287760720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4287760720
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2473043998
Short name T58
Test name
Test status
Simulation time 26813703261 ps
CPU time 1947.34 seconds
Started Jul 01 05:20:01 PM PDT 24
Finished Jul 01 05:52:32 PM PDT 24
Peak memory 282156 kb
Host smart-3c850e9e-0e3f-419c-a570-f250b958a91e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473043998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2473043998
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1222789071
Short name T461
Test name
Test status
Simulation time 4254032997 ps
CPU time 89.69 seconds
Started Jul 01 05:20:01 PM PDT 24
Finished Jul 01 05:21:35 PM PDT 24
Peak memory 257108 kb
Host smart-56bfb49c-00d1-4e2d-aa2b-dfec2bfb756b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12227
89071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1222789071
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1303852521
Short name T449
Test name
Test status
Simulation time 187830719 ps
CPU time 4.48 seconds
Started Jul 01 05:20:00 PM PDT 24
Finished Jul 01 05:20:08 PM PDT 24
Peak memory 240984 kb
Host smart-530f07ee-5ce3-4aa9-9650-2d0e873bcceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13038
52521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1303852521
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1071886628
Short name T354
Test name
Test status
Simulation time 14795497382 ps
CPU time 1148.13 seconds
Started Jul 01 05:20:02 PM PDT 24
Finished Jul 01 05:39:15 PM PDT 24
Peak memory 283016 kb
Host smart-090c70e4-517e-4787-a37b-f5b5f5451ee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071886628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1071886628
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2169905078
Short name T407
Test name
Test status
Simulation time 58077211391 ps
CPU time 757.15 seconds
Started Jul 01 05:20:01 PM PDT 24
Finished Jul 01 05:32:43 PM PDT 24
Peak memory 274108 kb
Host smart-cccd8b84-4508-4e87-bfe9-4a75dfaf2dd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169905078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2169905078
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3098273380
Short name T327
Test name
Test status
Simulation time 7533903730 ps
CPU time 301.81 seconds
Started Jul 01 05:20:02 PM PDT 24
Finished Jul 01 05:25:09 PM PDT 24
Peak memory 249420 kb
Host smart-33e8ce4b-800e-4c03-9f26-481f44ef5b10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098273380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3098273380
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2105365404
Short name T54
Test name
Test status
Simulation time 3487122206 ps
CPU time 49.07 seconds
Started Jul 01 05:20:03 PM PDT 24
Finished Jul 01 05:20:56 PM PDT 24
Peak memory 256768 kb
Host smart-ee9cfd2e-17ca-482d-b6a7-e0d0a06abc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21053
65404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2105365404
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2288461472
Short name T288
Test name
Test status
Simulation time 276862809 ps
CPU time 25.3 seconds
Started Jul 01 05:20:04 PM PDT 24
Finished Jul 01 05:20:33 PM PDT 24
Peak memory 257472 kb
Host smart-2192fae6-c3cf-4695-946e-9ed2fad14f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22884
61472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2288461472
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2056945455
Short name T600
Test name
Test status
Simulation time 57582802 ps
CPU time 4.3 seconds
Started Jul 01 05:20:03 PM PDT 24
Finished Jul 01 05:20:12 PM PDT 24
Peak memory 240188 kb
Host smart-71ffbe9d-4d28-4549-8ea9-6f7e78f56ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20569
45455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2056945455
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.308367457
Short name T384
Test name
Test status
Simulation time 189684466 ps
CPU time 12.54 seconds
Started Jul 01 05:20:02 PM PDT 24
Finished Jul 01 05:20:19 PM PDT 24
Peak memory 257084 kb
Host smart-75e9800d-10a4-4400-b2e3-04a6daeb7a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30836
7457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.308367457
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.941535227
Short name T584
Test name
Test status
Simulation time 16856103114 ps
CPU time 1503.3 seconds
Started Jul 01 05:20:00 PM PDT 24
Finished Jul 01 05:45:07 PM PDT 24
Peak memory 290220 kb
Host smart-dd9f74ba-341d-44aa-9213-fbaee0cda3ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941535227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.941535227
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1396227536
Short name T49
Test name
Test status
Simulation time 72440146579 ps
CPU time 3987.28 seconds
Started Jul 01 05:20:00 PM PDT 24
Finished Jul 01 06:26:31 PM PDT 24
Peak memory 323236 kb
Host smart-3869f3d8-342d-4d81-877b-f40cb31f5b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396227536 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1396227536
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2264024668
Short name T212
Test name
Test status
Simulation time 38697621 ps
CPU time 2.68 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:18:08 PM PDT 24
Peak memory 249620 kb
Host smart-c16576ce-c92f-4dc0-87bf-7c3ba5b28172
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2264024668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2264024668
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1794150645
Short name T516
Test name
Test status
Simulation time 108964675829 ps
CPU time 1755.41 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:47:27 PM PDT 24
Peak memory 286104 kb
Host smart-881a2f61-bf07-4576-b611-63ac1931d2c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794150645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1794150645
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2793385226
Short name T551
Test name
Test status
Simulation time 362464321 ps
CPU time 18.03 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:29 PM PDT 24
Peak memory 249276 kb
Host smart-746cda5b-1b78-4226-814f-c7751f0a177a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2793385226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2793385226
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3626702016
Short name T610
Test name
Test status
Simulation time 882744000 ps
CPU time 38.65 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:49 PM PDT 24
Peak memory 256964 kb
Host smart-af807c16-3840-4eb9-85d9-4029a143c05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36267
02016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3626702016
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2624543944
Short name T76
Test name
Test status
Simulation time 1351584721 ps
CPU time 42.91 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:18:49 PM PDT 24
Peak memory 249356 kb
Host smart-43f056ae-0bce-4390-a33c-449a14cdfbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26245
43944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2624543944
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.350776247
Short name T426
Test name
Test status
Simulation time 23531629428 ps
CPU time 1358.35 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:40:46 PM PDT 24
Peak memory 273940 kb
Host smart-db23abb3-3eec-4d00-8275-67b8cc68de9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350776247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.350776247
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2249162968
Short name T334
Test name
Test status
Simulation time 38847542879 ps
CPU time 429.53 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:25:20 PM PDT 24
Peak memory 255516 kb
Host smart-bf6144ba-b695-45c7-80f2-fc668f31afed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249162968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2249162968
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.260373797
Short name T415
Test name
Test status
Simulation time 327231785 ps
CPU time 22.09 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:18:31 PM PDT 24
Peak memory 257500 kb
Host smart-9b1a6a35-dcb3-4436-b0ac-6d1aabf0cc4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26037
3797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.260373797
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2420287523
Short name T376
Test name
Test status
Simulation time 423864441 ps
CPU time 12.44 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:23 PM PDT 24
Peak memory 248828 kb
Host smart-ccd4d46e-4f68-40f1-8264-738a3ebf7ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24202
87523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2420287523
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2581515467
Short name T559
Test name
Test status
Simulation time 10724272416 ps
CPU time 47.7 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:18:52 PM PDT 24
Peak memory 249300 kb
Host smart-553e9577-0203-4dec-ae8a-9fc75dd76a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25815
15467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2581515467
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.171591015
Short name T520
Test name
Test status
Simulation time 2839652606 ps
CPU time 39.2 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:49 PM PDT 24
Peak memory 249320 kb
Host smart-69eedb75-6f7b-46b0-9a5d-d32a06377312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17159
1015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.171591015
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3140630763
Short name T115
Test name
Test status
Simulation time 54304595875 ps
CPU time 2912.38 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 06:06:39 PM PDT 24
Peak memory 289504 kb
Host smart-dbdb1a5e-19b1-4663-ad0d-998321284c39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140630763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3140630763
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.537139003
Short name T30
Test name
Test status
Simulation time 66109327784 ps
CPU time 1603.41 seconds
Started Jul 01 05:18:05 PM PDT 24
Finished Jul 01 05:44:53 PM PDT 24
Peak memory 306144 kb
Host smart-aedd3279-497e-4188-a3d6-89db5df7a505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537139003 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.537139003
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2677705007
Short name T207
Test name
Test status
Simulation time 47486816 ps
CPU time 3.29 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:18:12 PM PDT 24
Peak memory 249648 kb
Host smart-238adaaf-5da4-44d0-ab90-5577e094bb78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2677705007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2677705007
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1303165643
Short name T27
Test name
Test status
Simulation time 155951046827 ps
CPU time 2375.26 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:57:46 PM PDT 24
Peak memory 289940 kb
Host smart-a460a07d-298e-4603-a023-ab6d068ca176
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303165643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1303165643
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3641668693
Short name T425
Test name
Test status
Simulation time 486560247 ps
CPU time 7.19 seconds
Started Jul 01 05:18:05 PM PDT 24
Finished Jul 01 05:18:17 PM PDT 24
Peak memory 249236 kb
Host smart-18c6cde3-39c6-4010-9c39-f73f354c8451
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3641668693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3641668693
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2030515182
Short name T480
Test name
Test status
Simulation time 3739514806 ps
CPU time 242.8 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:22:14 PM PDT 24
Peak memory 251648 kb
Host smart-7590ce45-9f87-43ea-bea0-c903d469df5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20305
15182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2030515182
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3116511318
Short name T83
Test name
Test status
Simulation time 1691676439 ps
CPU time 36.9 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:18:42 PM PDT 24
Peak memory 256960 kb
Host smart-999fc3cf-b3e6-4a28-b2a2-1791af3ebde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
11318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3116511318
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2198350152
Short name T307
Test name
Test status
Simulation time 14797515463 ps
CPU time 1129.46 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:37:00 PM PDT 24
Peak memory 273900 kb
Host smart-de3edbf9-6fd9-42a6-b225-8d3b4349d400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198350152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2198350152
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2140290162
Short name T260
Test name
Test status
Simulation time 563207248263 ps
CPU time 1972.23 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:51:03 PM PDT 24
Peak memory 273956 kb
Host smart-ebb3d835-3539-4096-bd88-377cfbbc89de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140290162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2140290162
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1155650322
Short name T414
Test name
Test status
Simulation time 257054564 ps
CPU time 20.72 seconds
Started Jul 01 05:18:05 PM PDT 24
Finished Jul 01 05:18:30 PM PDT 24
Peak memory 256816 kb
Host smart-49a028a6-c5ed-490d-ac69-3131a58892a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11556
50322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1155650322
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1554215151
Short name T113
Test name
Test status
Simulation time 610001341 ps
CPU time 30.53 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:18:38 PM PDT 24
Peak memory 256928 kb
Host smart-dda30610-508d-46e9-a15e-3fcffcc3102a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15542
15151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1554215151
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.730712917
Short name T15
Test name
Test status
Simulation time 2331093854 ps
CPU time 45.23 seconds
Started Jul 01 05:18:03 PM PDT 24
Finished Jul 01 05:18:50 PM PDT 24
Peak memory 257460 kb
Host smart-b3cff4c6-105c-4a13-b1d5-3472933f83fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73071
2917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.730712917
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4133368634
Short name T562
Test name
Test status
Simulation time 580896822 ps
CPU time 9.28 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:18:17 PM PDT 24
Peak memory 257544 kb
Host smart-c0f3f895-71a5-4bbf-920f-c37164cb6b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41333
68634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4133368634
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1620002294
Short name T666
Test name
Test status
Simulation time 16073386858 ps
CPU time 1669.2 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:46:00 PM PDT 24
Peak memory 290120 kb
Host smart-137d1b53-96a7-4e08-b91c-2eda49d4f1fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620002294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1620002294
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3927855498
Short name T217
Test name
Test status
Simulation time 42627558 ps
CPU time 2.4 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:18:14 PM PDT 24
Peak memory 249592 kb
Host smart-0bf5cb3f-054a-439d-86cb-3aa86b136ed9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3927855498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3927855498
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1081194477
Short name T479
Test name
Test status
Simulation time 17858208507 ps
CPU time 1395.45 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:41:26 PM PDT 24
Peak memory 289252 kb
Host smart-1ff32db1-d00c-4eae-a27b-3bb789957bec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081194477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1081194477
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4006025788
Short name T523
Test name
Test status
Simulation time 153637811 ps
CPU time 9.8 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:18:21 PM PDT 24
Peak memory 249304 kb
Host smart-c83a46a6-e1b8-47dc-bc03-0b7bc3e19d7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4006025788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4006025788
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.528912229
Short name T42
Test name
Test status
Simulation time 11895993191 ps
CPU time 207.72 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:21:39 PM PDT 24
Peak memory 257152 kb
Host smart-32ea030b-759f-411c-8203-211f289b4c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52891
2229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.528912229
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2507640822
Short name T373
Test name
Test status
Simulation time 98987808 ps
CPU time 5.42 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:16 PM PDT 24
Peak memory 248836 kb
Host smart-480b9ae9-d820-4e73-9cf4-828881aa4d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25076
40822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2507640822
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3672842828
Short name T345
Test name
Test status
Simulation time 160890852027 ps
CPU time 1068.66 seconds
Started Jul 01 05:18:04 PM PDT 24
Finished Jul 01 05:35:55 PM PDT 24
Peak memory 282236 kb
Host smart-c07a4ed2-67b1-456d-83c8-59339f90b48d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672842828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3672842828
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1361962645
Short name T618
Test name
Test status
Simulation time 2214003246 ps
CPU time 48.13 seconds
Started Jul 01 05:18:05 PM PDT 24
Finished Jul 01 05:18:58 PM PDT 24
Peak memory 256968 kb
Host smart-4b8723f8-63c5-42ab-8cf9-3fe1d6293727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13619
62645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1361962645
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3728455506
Short name T536
Test name
Test status
Simulation time 2270832116 ps
CPU time 36.6 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:48 PM PDT 24
Peak memory 249256 kb
Host smart-eda40f5c-3244-40b2-9e16-8a8baff6584a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37284
55506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3728455506
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.532330923
Short name T477
Test name
Test status
Simulation time 3223337167 ps
CPU time 49.02 seconds
Started Jul 01 05:18:06 PM PDT 24
Finished Jul 01 05:18:59 PM PDT 24
Peak memory 250452 kb
Host smart-f514c8be-0eec-4db2-a314-1c0a43fce1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53233
0923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.532330923
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.842564792
Short name T694
Test name
Test status
Simulation time 59051212 ps
CPU time 4.7 seconds
Started Jul 01 05:18:05 PM PDT 24
Finished Jul 01 05:18:15 PM PDT 24
Peak memory 249216 kb
Host smart-47be577a-560b-491d-a214-f00e5d3443cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84256
4792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.842564792
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2131137822
Short name T303
Test name
Test status
Simulation time 77236262157 ps
CPU time 1601.94 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:44:53 PM PDT 24
Peak memory 290092 kb
Host smart-7dbde1a4-09e6-404d-a7be-fa2c28ed13d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131137822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2131137822
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2807632625
Short name T219
Test name
Test status
Simulation time 17243186 ps
CPU time 2.52 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:18:20 PM PDT 24
Peak memory 249620 kb
Host smart-5d7cb462-ef41-4bdf-b4a9-4eeecd96b026
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2807632625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2807632625
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.820640678
Short name T706
Test name
Test status
Simulation time 42981197000 ps
CPU time 2474.98 seconds
Started Jul 01 05:18:16 PM PDT 24
Finished Jul 01 05:59:35 PM PDT 24
Peak memory 290252 kb
Host smart-5bab2516-8cc2-4570-a5aa-13c06be422ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820640678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.820640678
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2699809850
Short name T696
Test name
Test status
Simulation time 2251623118 ps
CPU time 19.73 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:18:41 PM PDT 24
Peak memory 249428 kb
Host smart-c5689529-9157-44b6-acfe-ffbaa881cfb4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2699809850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2699809850
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.612372520
Short name T468
Test name
Test status
Simulation time 15493219100 ps
CPU time 253.15 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:22:30 PM PDT 24
Peak memory 257520 kb
Host smart-3b61c76f-b07a-4dc8-a086-2f3ab32dbcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61237
2520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.612372520
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2146170254
Short name T557
Test name
Test status
Simulation time 1700384542 ps
CPU time 37.75 seconds
Started Jul 01 05:18:11 PM PDT 24
Finished Jul 01 05:18:52 PM PDT 24
Peak memory 257068 kb
Host smart-b7d32401-40b3-4872-94b4-8615b6947e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21461
70254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2146170254
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1001696135
Short name T613
Test name
Test status
Simulation time 25610259059 ps
CPU time 1544.49 seconds
Started Jul 01 05:18:11 PM PDT 24
Finished Jul 01 05:43:59 PM PDT 24
Peak memory 273592 kb
Host smart-802915c2-fd6d-4923-8ff5-6ed22a6f5da5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001696135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1001696135
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1042875789
Short name T445
Test name
Test status
Simulation time 122083673041 ps
CPU time 2136.98 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:53:55 PM PDT 24
Peak memory 289600 kb
Host smart-49ee73d5-c329-4b6b-85f6-dcd209ee4d93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042875789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1042875789
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.819750910
Short name T322
Test name
Test status
Simulation time 12054288386 ps
CPU time 507.06 seconds
Started Jul 01 05:18:15 PM PDT 24
Finished Jul 01 05:26:46 PM PDT 24
Peak memory 248236 kb
Host smart-418cbac6-92a9-48db-a6b8-1d2dfc893bef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819750910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.819750910
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2304693814
Short name T418
Test name
Test status
Simulation time 1097453095 ps
CPU time 10.15 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:18:22 PM PDT 24
Peak memory 252872 kb
Host smart-f7effe37-aff4-4305-a9e7-eebbcce3e10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23046
93814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2304693814
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2987736135
Short name T616
Test name
Test status
Simulation time 3749986625 ps
CPU time 17.38 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:18:32 PM PDT 24
Peak memory 248924 kb
Host smart-b820b6d8-a10f-4a72-b33a-c60290645026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29877
36135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2987736135
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.571673689
Short name T462
Test name
Test status
Simulation time 239856700 ps
CPU time 5.54 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:18:21 PM PDT 24
Peak memory 240648 kb
Host smart-af257a91-0634-4f83-b7c4-c5324852be5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57167
3689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.571673689
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1760673206
Short name T443
Test name
Test status
Simulation time 370677696 ps
CPU time 24.11 seconds
Started Jul 01 05:18:07 PM PDT 24
Finished Jul 01 05:18:35 PM PDT 24
Peak memory 257464 kb
Host smart-6b00bd6c-8d5e-429b-94d1-6248947e45bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
73206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1760673206
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1962041997
Short name T395
Test name
Test status
Simulation time 8512506901 ps
CPU time 175.42 seconds
Started Jul 01 05:18:19 PM PDT 24
Finished Jul 01 05:21:19 PM PDT 24
Peak memory 257388 kb
Host smart-d87efaa7-7cfc-4bc2-9cd8-b25bfd9ed2b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962041997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1962041997
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.784185578
Short name T284
Test name
Test status
Simulation time 106329342294 ps
CPU time 2853.4 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 06:05:51 PM PDT 24
Peak memory 306920 kb
Host smart-bbd2f31f-bb27-4686-a48a-5e70d98ee3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784185578 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.784185578
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2143844833
Short name T203
Test name
Test status
Simulation time 77363704 ps
CPU time 3.07 seconds
Started Jul 01 05:18:13 PM PDT 24
Finished Jul 01 05:18:19 PM PDT 24
Peak memory 249652 kb
Host smart-0c76a120-a9b9-4f5d-bb37-cd15f59b2b42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2143844833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2143844833
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.471270101
Short name T693
Test name
Test status
Simulation time 14749388212 ps
CPU time 1626.66 seconds
Started Jul 01 05:18:15 PM PDT 24
Finished Jul 01 05:45:26 PM PDT 24
Peak memory 289932 kb
Host smart-fb038596-4050-4c2c-a39e-a2d1d922b2e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471270101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.471270101
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1182675968
Short name T385
Test name
Test status
Simulation time 2227366001 ps
CPU time 119.09 seconds
Started Jul 01 05:18:16 PM PDT 24
Finished Jul 01 05:20:20 PM PDT 24
Peak memory 257576 kb
Host smart-898e7482-0093-4a9b-b1bf-f4055ca1a190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11826
75968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1182675968
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3519734344
Short name T80
Test name
Test status
Simulation time 333994033 ps
CPU time 30.27 seconds
Started Jul 01 05:18:16 PM PDT 24
Finished Jul 01 05:18:51 PM PDT 24
Peak memory 256576 kb
Host smart-b71c367f-1978-4e79-9a05-2c8390a889ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
34344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3519734344
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1075939760
Short name T339
Test name
Test status
Simulation time 31180311171 ps
CPU time 1722.56 seconds
Started Jul 01 05:18:16 PM PDT 24
Finished Jul 01 05:47:04 PM PDT 24
Peak memory 273932 kb
Host smart-ddb69cf5-d0a3-4c22-b72b-41d6d3c4148b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075939760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1075939760
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.550335130
Short name T242
Test name
Test status
Simulation time 66058101238 ps
CPU time 1023.13 seconds
Started Jul 01 05:18:11 PM PDT 24
Finished Jul 01 05:35:17 PM PDT 24
Peak memory 273976 kb
Host smart-b86d6091-1867-4970-9fff-4e9128ae2ac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550335130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.550335130
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1154552843
Short name T336
Test name
Test status
Simulation time 54234922370 ps
CPU time 604.64 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:28:19 PM PDT 24
Peak memory 257608 kb
Host smart-93a5eb82-eb19-45c1-b9b0-7b8c00833ed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154552843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1154552843
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2360254146
Short name T484
Test name
Test status
Simulation time 851464509 ps
CPU time 16.69 seconds
Started Jul 01 05:18:14 PM PDT 24
Finished Jul 01 05:18:35 PM PDT 24
Peak memory 256840 kb
Host smart-80e26ca0-d6cb-48d5-a90f-1810c2c6f3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
54146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2360254146
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3259050978
Short name T469
Test name
Test status
Simulation time 289753636 ps
CPU time 24.19 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:18:40 PM PDT 24
Peak memory 249364 kb
Host smart-a3fdaaf2-066d-4fc8-a142-ab702798e790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
50978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3259050978
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1777041842
Short name T273
Test name
Test status
Simulation time 2095923002 ps
CPU time 50.1 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:19:11 PM PDT 24
Peak memory 257332 kb
Host smart-434688ba-eba6-4e6f-a1b6-278057c1fe35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
41842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1777041842
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1065741451
Short name T39
Test name
Test status
Simulation time 1664986068 ps
CPU time 10.65 seconds
Started Jul 01 05:18:12 PM PDT 24
Finished Jul 01 05:18:25 PM PDT 24
Peak memory 249848 kb
Host smart-7170f9ce-b8fa-41d8-90df-398dd133f697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10657
41451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1065741451
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1846985503
Short name T464
Test name
Test status
Simulation time 130199215294 ps
CPU time 2131.5 seconds
Started Jul 01 05:18:17 PM PDT 24
Finished Jul 01 05:53:53 PM PDT 24
Peak memory 288392 kb
Host smart-65456e5c-4919-42c5-a54d-57139d93cc65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846985503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1846985503
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3844471592
Short name T181
Test name
Test status
Simulation time 141703674270 ps
CPU time 2263.22 seconds
Started Jul 01 05:18:11 PM PDT 24
Finished Jul 01 05:55:58 PM PDT 24
Peak memory 290324 kb
Host smart-4a1dde86-4466-4153-af66-aee6ae9d619e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844471592 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3844471592
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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