Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	43251	1			T5	1		T6	1		T9	3
class_i[0x1]	66194	1			T4	6		T5	8		T9	9
class_i[0x2]	69089	1			T1	3		T5	5		T6	11
class_i[0x3]	65854	1			T4	10		T6	1		T16	19

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63588	1			T4	1		T5	2		T6	4
alert[0x1]	59476	1			T4	3		T5	4		T6	3
alert[0x2]	57914	1			T1	3		T4	12		T5	1
alert[0x3]	63410	1			T5	7		T6	3		T9	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

244075

1

T1

3

T4

16

T5

8

esc_ping_fail

313

1

T5

6

T6

13

T10

1

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63502	1			T4	1		T5	1		T9	13
esc_integrity_fail	alert[0x1]	59383	1			T4	3		T5	2		T9	5
esc_integrity_fail	alert[0x2]	57848	1			T1	3		T4	12		T9	3
esc_integrity_fail	alert[0x3]	63342	1			T5	5		T9	1		T7	7
esc_ping_fail	alert[0x0]	86	1			T5	1		T6	4		T10	1
esc_ping_fail	alert[0x1]	93	1			T5	2		T6	3		T234	2
esc_ping_fail	alert[0x2]	66	1			T5	1		T6	3		T14	1
esc_ping_fail	alert[0x3]	68	1			T5	2		T6	3		T14	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	43183	1			T9	3		T7	16		T18	4644
esc_integrity_fail	class_i[0x1]	66113	1			T4	6		T5	7		T9	9
esc_integrity_fail	class_i[0x2]	68981	1			T1	3		T5	1		T9	10
esc_integrity_fail	class_i[0x3]	65798	1			T4	10		T16	19		T75	9
esc_ping_fail	class_i[0x0]	68	1			T5	1		T6	1		T14	3
esc_ping_fail	class_i[0x1]	81	1			T5	1		T234	1		T36	3
esc_ping_fail	class_i[0x2]	108	1			T5	4		T6	11		T10	1
esc_ping_fail	class_i[0x3]	56	1			T6	1		T36	1		T291	1