Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	669010952	0	0	620
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	669010952	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	669010952	668836815	0	0
tb.dut.CheckAccuCntDw	0	0	620	620	0	0
tb.dut.CheckEscCntDw	0	0	620	620	0	0
tb.dut.CheckNAlerts	0	0	620	620	0	0
tb.dut.CheckNClasses	0	0	620	620	0	0
tb.dut.CheckNEscSev	0	0	620	620	0	0
tb.dut.CrashdumpKnownO_A	0	0	669010952	668836815	0	0
tb.dut.EdnKnownO_A	0	0	669010952	668836815	0	0
tb.dut.EscPKnownO_A	0	0	669010952	668836815	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	669010952	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	669010952	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	669010952	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	669010952	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	669010952	80	0	0
tb.dut.IrqAKnownO_A	0	0	669010952	668836815	0	0
tb.dut.IrqBKnownO_A	0	0	669010952	668836815	0	0
tb.dut.IrqCKnownO_A	0	0	669010952	668836815	0	0
tb.dut.IrqDKnownO_A	0	0	669010952	668836815	0	0
tb.dut.TlAReadyKnownO_A	0	0	669010952	668836815	0	0
tb.dut.TlDValidKnownO_A	0	0	669010952	668836815	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	694866744	2271475	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	694866744	20940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	694866744	21151	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	694866744	20259	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	694866744	20704	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	694866744	21477	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	694866744	21088	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	694866744	21181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	694866744	20312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	694866744	20860	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	694866744	21243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	694866744	20706	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	694866744	20823	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	694866744	21751	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	694866744	20742	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	694866744	21790	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	694866744	21456	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	694866744	21557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	694866744	20819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	694866744	19822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	694866744	20265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	694866744	21138	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	694866744	21786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	694866744	20678	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	694866744	19850	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	694866744	20951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	694866744	21009	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	694866744	20501	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	694866744	21048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	694866744	21459	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	694866744	20771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	694866744	20546	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	694866744	20998	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	694866744	21294	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	694866744	21506	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	694866744	21168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	694866744	20264	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	694866744	21534	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	694866744	19948	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	694866744	20851	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	694866744	20339	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	694866744	20989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	694866744	20505	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	694866744	20749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	694866744	21142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	694866744	21865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	694866744	20855	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	694866744	21148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	694866744	20137	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	694866744	21010	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	694866744	20840	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	694866744	20338	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	694866744	20362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	694866744	21207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	694866744	20957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	694866744	20624	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	694866744	20595	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	694866744	20136	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	694866744	21425	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	694866744	20109	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	694866744	20708	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	694866744	20463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	694866744	21111	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	694866744	20152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	694866744	20449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	694866744	20924	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	694866744	20396	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	694866744	21623	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	694866744	20069	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	694866744	21260	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	694866744	42092	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	694866744	20697	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	694866744	20176	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	694866744	21513	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	694866744	21354	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	694866744	21686	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	694866744	20580	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	694866744	20635	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	694866744	20616	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	669010952	3847	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	669010952	228253	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	669010952	359139255	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	669010952	294	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	669010952	815	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	669010952	45	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	669010952	378	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	668474116	277415421	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	669010952	899	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	669010952	882	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	669010952	864	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	669010952	850	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	669010952	928	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	669010952	98894	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	669010952	820	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	669010952	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	669010952	1458	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	669010952	1218	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	668472681	668399953	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	669010952	668836815	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	669010952	1996	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	669010952	193572	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	669010952	384328027	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	669010952	292	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	669010952	499	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	669010952	19	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	669010952	243	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	668474116	295222770	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	669010952	579	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	669010952	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	669010952	557	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	669010952	544	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	669010952	1279	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	669010952	123848	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	669010952	1186	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	669010952	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	669010952	1387	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	669010952	1147	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	668472681	668399953	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	669010952	668836815	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	669010952	2120	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	669010952	180345	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	669010952	379703785	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	669010952	258	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	669010952	471	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	669010952	12	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	669010952	199	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	668474116	296142210	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	669010952	552	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	669010952	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	669010952	539	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	669010952	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	669010952	643	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	669010952	88677	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	669010952	552	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	669010952	79	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	669010952	1417	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	669010952	1177	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	668472681	668399953	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	669010952	668836815	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	669010952	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	669010952	4305	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	669010952	230814	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	669010952	347825637	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	669010952	303	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	669010952	539	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	669010952	30	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	669010952	249	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	668474116	269946665	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	669010952	610	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	669010952	602	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	669010952	598	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	669010952	589	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	669010952	539	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	669010952	65958	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	669010952	463	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	669010952	44	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	669010952	1406	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	669010952	1166	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	668472681	668399953	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	620	620	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	669010952	668836815	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	694866744	125821851	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	694866744	694192197	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	694866744	694192197	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	694866744	181402908	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	694866744	694192197	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	694866744	694192197	0	0
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tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	825	825	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	825	825	0	0

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