Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	126	1			T9	1		T18	1		T45	1
index[0x1]	159	1			T9	1		T18	3		T46	1
index[0x2]	124	1			T31	1		T16	1		T49	2
index[0x3]	152	1			T4	1		T9	1		T18	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	171	1			T9	1		T18	1		T45	1
lens_less_than_1000[1]	96	1			T47	1		T70	2		T72	1
lens_less_than_1000[2]	93	1			T4	1		T18	2		T19	1
lens_less_than_1000[3]	68	1			T18	1		T75	1		T49	8
lens_less_than_1000[4]	47	1			T9	1		T31	1		T69	1
lens_less_than_1000[5]	30	1			T30	1		T53	1		T56	1
lens_less_than_1000[6]	23	1			T9	1		T16	1		T108	1
lens_less_than_1000[7]	14	1			T42	1		T109	1		T90	1
lens_less_than_1000[8]	13	1			T18	1		T31	2		T28	1
lens_less_than_1000[9]	1	1			T262	1		-	-		-	-
len_2	5	1			T104	1		T263	1		T244	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[len_2]	0	1	1
[index[0x1] , index[0x2] , index[0x3]]	[lens_less_than_1000[9]]	--	--	3

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	33	1			T45	1		T49	1		T26	1
index[0x0]	lens_less_than_1000[1]	15	1			T47	1		T37	1		T39	1
index[0x0]	lens_less_than_1000[2]	23	1			T16	2		T26	1		T53	1
index[0x0]	lens_less_than_1000[3]	22	1			T18	1		T102	1		T73	1
index[0x0]	lens_less_than_1000[4]	13	1			T9	1		T31	1		T264	1
index[0x0]	lens_less_than_1000[5]	5	1			T53	1		T81	1		T263	1
index[0x0]	lens_less_than_1000[6]	6	1			T108	1		T109	1		T85	1
index[0x0]	lens_less_than_1000[7]	4	1			T109	1		T90	1		T265	1
index[0x0]	lens_less_than_1000[8]	4	1			T31	1		T28	1		T266	1
index[0x0]	lens_less_than_1000[9]	1	1			T262	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	45	1			T18	1		T49	2		T26	1
index[0x1]	lens_less_than_1000[1]	33	1			T70	2		T74	1		T267	1
index[0x1]	lens_less_than_1000[2]	16	1			T18	1		T46	1		T52	1
index[0x1]	lens_less_than_1000[3]	21	1			T75	1		T49	8		T42	1
index[0x1]	lens_less_than_1000[4]	12	1			T110	1		T77	1		T243	1
index[0x1]	lens_less_than_1000[5]	10	1			T60	1		T62	3		T268	1
index[0x1]	lens_less_than_1000[6]	14	1			T9	1		T16	1		T264	1
index[0x1]	lens_less_than_1000[7]	2	1			T269	1		T270	1		-	-
index[0x1]	lens_less_than_1000[8]	4	1			T18	1		T108	1		T248	1
index[0x1]	len_2	2	1			T263	1		T271	1		-	-
index[0x2]	lens_less_than_1000[0]	44	1			T49	2		T72	1		T74	1
index[0x2]	lens_less_than_1000[1]	20	1			T52	1		T53	2		T57	1
index[0x2]	lens_less_than_1000[2]	21	1			T16	1		T74	1		T30	1
index[0x2]	lens_less_than_1000[3]	16	1			T272	1		T106	2		T63	1
index[0x2]	lens_less_than_1000[4]	8	1			T53	1		T57	1		T273	1
index[0x2]	lens_less_than_1000[5]	6	1			T56	1		T108	1		T78	1
index[0x2]	lens_less_than_1000[6]	1	1			T274	1		-	-		-	-
index[0x2]	lens_less_than_1000[7]	4	1			T241	1		T275	1		T276	1
index[0x2]	lens_less_than_1000[8]	2	1			T31	1		T85	1		-	-
index[0x2]	len_2	2	1			T104	1		T244	1		-	-
index[0x3]	lens_less_than_1000[0]	49	1			T9	1		T42	1		T55	1
index[0x3]	lens_less_than_1000[1]	28	1			T72	1		T53	1		T243	1
index[0x3]	lens_less_than_1000[2]	33	1			T4	1		T18	1		T19	1
index[0x3]	lens_less_than_1000[3]	9	1			T63	1		T24	2		T277	1
index[0x3]	lens_less_than_1000[4]	14	1			T69	1		T108	1		T242	1
index[0x3]	lens_less_than_1000[5]	9	1			T30	1		T28	1		T33	1
index[0x3]	lens_less_than_1000[6]	2	1			T256	1		T65	1		-	-
index[0x3]	lens_less_than_1000[7]	4	1			T42	1		T278	1		T279	1
index[0x3]	lens_less_than_1000[8]	3	1			T77	1		T62	2		-	-
index[0x3]	len_2	1	1			T280	1		-	-		-	-