Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T17	1		T18	1		T19	1
class_index[0x1]	69	1			T9	1		T49	1		T27	1
class_index[0x2]	79	1			T9	1		T18	1		T16	1
class_index[0x3]	44	1			T18	2		T16	1		T75	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	98	1			T18	1		T19	1		T16	1
intr_timeout_cnt[1]	66	1			T17	1		T18	1		T16	1
intr_timeout_cnt[2]	27	1			T18	2		T27	1		T74	4
intr_timeout_cnt[3]	15	1			T9	1		T75	1		T48	1
intr_timeout_cnt[4]	16	1			T47	1		T37	1		T55	1
intr_timeout_cnt[5]	9	1			T52	1		T242	1		T243	1
intr_timeout_cnt[6]	5	1			T9	1		T244	1		T245	1
intr_timeout_cnt[7]	7	1			T49	1		T32	2		T246	1
intr_timeout_cnt[8]	8	1			T75	1		T42	1		T52	1
intr_timeout_cnt[9]	3	1			T49	1		T247	1		T173	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	24	1			T19	1		T68	1		T38	1
class_index[0x0]	intr_timeout_cnt[1]	16	1			T17	1		T77	1		T58	2
class_index[0x0]	intr_timeout_cnt[2]	7	1			T18	1		T37	1		T57	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T75	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	7	1			T47	1		T37	1		T55	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T243	1		T248	1		T174	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T246	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T49	1		T249	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	31	1			T49	1		T77	3		T78	3
class_index[0x1]	intr_timeout_cnt[1]	19	1			T42	1		T78	1		T241	2
class_index[0x1]	intr_timeout_cnt[2]	6	1			T27	1		T74	4		T62	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T250	1		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T252	1		T96	1		T249	2
class_index[0x1]	intr_timeout_cnt[5]	1	1			T239	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T9	1		T245	1		T253	1
class_index[0x1]	intr_timeout_cnt[8]	2	1			T247	1		T239	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T173	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T18	1		T16	1		T49	2
class_index[0x2]	intr_timeout_cnt[1]	22	1			T52	1		T104	1		T109	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T79	1		T80	1		T244	1
class_index[0x2]	intr_timeout_cnt[3]	9	1			T9	1		T254	1		T255	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T256	1		T246	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T52	1		T242	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T244	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T32	1		T98	1		T257	1
class_index[0x2]	intr_timeout_cnt[8]	4	1			T75	1		T52	1		T64	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T49	1		T247	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	16	1			T75	1		T68	1		T53	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T18	1		T16	1		T112	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T18	1		T112	1		T78	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T48	1		T77	1		T258	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T243	1		T255	1		T259	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T260	1		T261	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T32	1		T246	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T42	1		T247	1		-	-