Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	358688	1			T1	7		T2	171		T3	13
all_values[1]	358688	1			T1	7		T2	171		T3	13
all_values[2]	358688	1			T1	7		T2	171		T3	13
all_values[3]	358688	1			T1	7		T2	171		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

714585

1

T1

17

T2

355

T3

36

auto[1]

720167

1

T1

11

T2

329

T3

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

858069

1

T1

5

T2

356

T3

28

auto[1]

576683

1

T1

23

T2

328

T3

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103138	1			T2	47		T3	5		T4	406
all_values[0]	auto[0]	auto[1]	75182	1			T1	2		T2	35		T3	4
all_values[0]	auto[1]	auto[0]	104629	1			T1	1		T2	49		T3	2
all_values[0]	auto[1]	auto[1]	75739	1			T1	4		T2	40		T3	2
all_values[1]	auto[0]	auto[0]	107099	1			T1	1		T2	51		T3	7
all_values[1]	auto[0]	auto[1]	71477	1			T1	4		T2	48		T3	6
all_values[1]	auto[1]	auto[0]	108673	1			T2	37		T4	397		T5	27
all_values[1]	auto[1]	auto[1]	71439	1			T1	2		T2	35		T4	389
all_values[2]	auto[0]	auto[0]	107731	1			T1	2		T2	43		T3	5
all_values[2]	auto[0]	auto[1]	70894	1			T1	3		T2	43		T3	4
all_values[2]	auto[1]	auto[0]	108935	1			T2	43		T3	2		T4	419
all_values[2]	auto[1]	auto[1]	71128	1			T1	2		T2	42		T3	2
all_values[3]	auto[0]	auto[0]	108390	1			T1	1		T2	44		T3	3
all_values[3]	auto[0]	auto[1]	70674	1			T1	4		T2	44		T3	2
all_values[3]	auto[1]	auto[0]	109474	1			T2	42		T3	4		T4	391
all_values[3]	auto[1]	auto[1]	70150	1			T1	2		T2	41		T3	4