Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	358688	1			T1	7		T2	171		T3	13
all_pins[1]	358688	1			T1	7		T2	171		T3	13
all_pins[2]	358688	1			T1	7		T2	171		T3	13
all_pins[3]	358688	1			T1	7		T2	171		T3	13

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1146296	1			T1	18		T2	526		T3	44
values[0x1]	288456	1			T1	10		T2	158		T3	8
transitions[0x0=>0x1]	192002	1			T1	4		T2	105		T3	7
transitions[0x1=>0x0]	192253	1			T1	5		T2	105		T3	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282949	1			T1	3		T2	131		T3	11
all_pins[0]	values[0x1]	75739	1			T1	4		T2	40		T3	2
all_pins[0]	transitions[0x0=>0x1]	75149	1			T1	2		T2	40		T3	2
all_pins[0]	transitions[0x1=>0x0]	69811	1			T1	1		T2	41		T3	4
all_pins[1]	values[0x0]	287249	1			T1	5		T2	136		T3	13
all_pins[1]	values[0x1]	71439	1			T1	2		T2	35		T4	389
all_pins[1]	transitions[0x0=>0x1]	39138	1			T2	18		T4	205		T5	6
all_pins[1]	transitions[0x1=>0x0]	43438	1			T1	2		T2	23		T3	2
all_pins[2]	values[0x0]	287560	1			T1	5		T2	129		T3	11
all_pins[2]	values[0x1]	71128	1			T1	2		T2	42		T3	2
all_pins[2]	transitions[0x0=>0x1]	39043	1			T1	1		T2	29		T3	2
all_pins[2]	transitions[0x1=>0x0]	39354	1			T1	1		T2	22		T4	170
all_pins[3]	values[0x0]	288538	1			T1	5		T2	130		T3	9
all_pins[3]	values[0x1]	70150	1			T1	2		T2	41		T3	4
all_pins[3]	transitions[0x0=>0x1]	38672	1			T1	1		T2	18		T3	3
all_pins[3]	transitions[0x1=>0x0]	39650	1			T1	1		T2	19		T3	1