Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	95839	1			T4	503		T7	484		T18	216
accum_cnt_1000	224548	1			T2	53		T4	569		T9	173
accum_cnt_100	25606	1			T2	13		T4	34		T9	73
accum_cnt_50	78359	1			T1	3		T2	11		T4	1164
accum_cnt_10	183586	1			T1	11		T2	5		T3	22
accum_cnt_0	403395	1			T1	18		T2	258		T3	26

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	264699	1			T1	8		T2	85		T3	12
class_index[0x1]	264699	1			T1	8		T2	85		T3	12
class_index[0x2]	264699	1			T1	8		T2	85		T3	12
class_index[0x3]	264699	1			T1	8		T2	85		T3	12

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25826	1			T4	503		T18	89		T21	418
class_index[0x0]	accum_cnt_1000	57573	1			T4	569		T9	127		T18	443
class_index[0x0]	accum_cnt_100	6594	1			T4	34		T9	53		T18	46
class_index[0x0]	accum_cnt_50	20871	1			T4	27		T9	160		T18	83
class_index[0x0]	accum_cnt_10	50949	1			T3	7		T4	6		T5	20
class_index[0x0]	accum_cnt_0	90251	1			T1	8		T2	85		T3	5
class_index[0x1]	accum_cnt_2000	21534	1			T16	50		T21	454		T26	579
class_index[0x1]	accum_cnt_1000	54016	1			T9	46		T18	807		T16	59
class_index[0x1]	accum_cnt_100	6545	1			T9	20		T18	72		T21	34
class_index[0x1]	accum_cnt_50	20973	1			T1	3		T4	1137		T9	35
class_index[0x1]	accum_cnt_10	47319	1			T1	5		T3	4		T4	2
class_index[0x1]	accum_cnt_0	102714	1			T2	85		T3	8		T5	23
class_index[0x2]	accum_cnt_2000	22622	1			T21	468		T25	83		T49	109
class_index[0x2]	accum_cnt_1000	55422	1			T7	1207		T18	443		T16	87
class_index[0x2]	accum_cnt_100	6137	1			T7	92		T18	58		T16	98
class_index[0x2]	accum_cnt_50	21181	1			T7	71		T18	51		T15	6
class_index[0x2]	accum_cnt_10	45203	1			T1	6		T5	15		T9	58
class_index[0x2]	accum_cnt_0	104579	1			T1	2		T2	85		T3	12
class_index[0x3]	accum_cnt_2000	25857	1			T7	484		T18	127		T26	496
class_index[0x3]	accum_cnt_1000	57537	1			T2	53		T7	830		T18	235
class_index[0x3]	accum_cnt_100	6330	1			T2	13		T7	37		T18	23
class_index[0x3]	accum_cnt_50	15334	1			T2	11		T7	38		T18	48
class_index[0x3]	accum_cnt_10	40115	1			T2	5		T3	11		T6	30
class_index[0x3]	accum_cnt_0	105851	1			T1	8		T2	3		T3	1