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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.70 100.00 100.00 100.00 99.38 99.44


Total test records in report: 825
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T769 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2133229707 Jul 02 08:07:53 AM PDT 24 Jul 02 08:09:43 AM PDT 24 873617733 ps
T770 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4086435257 Jul 02 08:08:07 AM PDT 24 Jul 02 08:08:13 AM PDT 24 11137720 ps
T771 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4224870699 Jul 02 08:08:03 AM PDT 24 Jul 02 08:08:09 AM PDT 24 95256847 ps
T136 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.660305552 Jul 02 08:07:44 AM PDT 24 Jul 02 08:26:15 AM PDT 24 16324638641 ps
T772 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3395213711 Jul 02 08:07:59 AM PDT 24 Jul 02 08:08:09 AM PDT 24 40236329 ps
T773 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.707255068 Jul 02 08:08:21 AM PDT 24 Jul 02 08:08:29 AM PDT 24 10700012 ps
T145 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3127650740 Jul 02 08:07:56 AM PDT 24 Jul 02 08:10:51 AM PDT 24 4897215932 ps
T774 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.282092176 Jul 02 08:07:50 AM PDT 24 Jul 02 08:08:10 AM PDT 24 579831299 ps
T775 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1490893924 Jul 02 08:08:03 AM PDT 24 Jul 02 08:08:33 AM PDT 24 698154162 ps
T146 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2602468824 Jul 02 08:08:02 AM PDT 24 Jul 02 08:12:50 AM PDT 24 3694749161 ps
T776 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2152564428 Jul 02 08:08:12 AM PDT 24 Jul 02 08:08:19 AM PDT 24 14728176 ps
T777 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3009195516 Jul 02 08:08:01 AM PDT 24 Jul 02 08:08:07 AM PDT 24 10185261 ps
T142 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3826099833 Jul 02 08:07:48 AM PDT 24 Jul 02 08:10:42 AM PDT 24 2470958147 ps
T778 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2377780032 Jul 02 08:08:12 AM PDT 24 Jul 02 08:08:19 AM PDT 24 7821486 ps
T779 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1522044069 Jul 02 08:08:08 AM PDT 24 Jul 02 08:08:13 AM PDT 24 14162846 ps
T332 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.969029059 Jul 02 08:07:55 AM PDT 24 Jul 02 08:13:35 AM PDT 24 8527714285 ps
T147 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3114022336 Jul 02 08:08:05 AM PDT 24 Jul 02 08:11:13 AM PDT 24 1661718247 ps
T780 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3012392372 Jul 02 08:08:04 AM PDT 24 Jul 02 08:08:19 AM PDT 24 132313085 ps
T781 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3183903429 Jul 02 08:08:06 AM PDT 24 Jul 02 08:08:14 AM PDT 24 23563670 ps
T782 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3556453073 Jul 02 08:08:13 AM PDT 24 Jul 02 08:08:20 AM PDT 24 11337584 ps
T148 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3738240646 Jul 02 08:07:58 AM PDT 24 Jul 02 08:23:48 AM PDT 24 27336512769 ps
T783 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1974573872 Jul 02 08:07:59 AM PDT 24 Jul 02 08:08:05 AM PDT 24 8591983 ps
T161 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.251353298 Jul 02 08:07:52 AM PDT 24 Jul 02 08:08:03 AM PDT 24 40672635 ps
T172 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3872037978 Jul 02 08:08:08 AM PDT 24 Jul 02 08:08:14 AM PDT 24 59813588 ps
T784 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1279045787 Jul 02 08:08:07 AM PDT 24 Jul 02 08:08:18 AM PDT 24 37170936 ps
T143 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.537148350 Jul 02 08:07:46 AM PDT 24 Jul 02 08:11:36 AM PDT 24 2252749205 ps
T785 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1448806589 Jul 02 08:08:02 AM PDT 24 Jul 02 08:08:10 AM PDT 24 25544060 ps
T786 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2057038446 Jul 02 08:07:52 AM PDT 24 Jul 02 08:08:08 AM PDT 24 211399139 ps
T787 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4133033280 Jul 02 08:08:13 AM PDT 24 Jul 02 08:08:20 AM PDT 24 7918843 ps
T788 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1527651525 Jul 02 08:08:00 AM PDT 24 Jul 02 08:08:08 AM PDT 24 19669845 ps
T144 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1859400001 Jul 02 08:08:09 AM PDT 24 Jul 02 08:18:05 AM PDT 24 28133922705 ps
T789 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1291676150 Jul 02 08:07:43 AM PDT 24 Jul 02 08:08:14 AM PDT 24 1762253093 ps
T790 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2731315121 Jul 02 08:08:00 AM PDT 24 Jul 02 08:10:46 AM PDT 24 6127221761 ps
T791 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1315557627 Jul 02 08:08:07 AM PDT 24 Jul 02 08:08:19 AM PDT 24 44512535 ps
T792 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3686333659 Jul 02 08:08:12 AM PDT 24 Jul 02 08:08:19 AM PDT 24 14743990 ps
T149 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3840388721 Jul 02 08:07:56 AM PDT 24 Jul 02 08:10:54 AM PDT 24 4712865217 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4268911125 Jul 02 08:07:51 AM PDT 24 Jul 02 08:08:07 AM PDT 24 127485524 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1853781424 Jul 02 08:08:07 AM PDT 24 Jul 02 08:08:17 AM PDT 24 77394315 ps
T795 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4255927621 Jul 02 08:08:05 AM PDT 24 Jul 02 08:08:21 AM PDT 24 310683348 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.411444334 Jul 02 08:08:03 AM PDT 24 Jul 02 08:08:14 AM PDT 24 296226288 ps
T169 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1115466734 Jul 02 08:07:44 AM PDT 24 Jul 02 08:07:55 AM PDT 24 41394260 ps
T157 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1346637668 Jul 02 08:08:04 AM PDT 24 Jul 02 08:08:34 AM PDT 24 657705749 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1204721893 Jul 02 08:08:16 AM PDT 24 Jul 02 08:08:27 AM PDT 24 79690502 ps
T798 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2923074079 Jul 02 08:08:11 AM PDT 24 Jul 02 08:08:52 AM PDT 24 3841291917 ps
T799 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1579660255 Jul 02 08:08:06 AM PDT 24 Jul 02 08:08:47 AM PDT 24 507122315 ps
T800 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.190669829 Jul 02 08:08:11 AM PDT 24 Jul 02 08:08:17 AM PDT 24 10444780 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.459258575 Jul 02 08:08:07 AM PDT 24 Jul 02 08:08:16 AM PDT 24 96771024 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4272835428 Jul 02 08:07:47 AM PDT 24 Jul 02 08:08:00 AM PDT 24 347438199 ps
T802 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1127523738 Jul 02 08:07:58 AM PDT 24 Jul 02 08:08:42 AM PDT 24 2036308411 ps
T803 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.822731047 Jul 02 08:07:57 AM PDT 24 Jul 02 08:08:04 AM PDT 24 6248509 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3610998575 Jul 02 08:07:46 AM PDT 24 Jul 02 08:08:02 AM PDT 24 182953698 ps
T333 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1154673151 Jul 02 08:07:55 AM PDT 24 Jul 02 08:15:56 AM PDT 24 11943053872 ps
T805 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.39195660 Jul 02 08:07:56 AM PDT 24 Jul 02 08:08:14 AM PDT 24 93470216 ps
T806 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3475692789 Jul 02 08:07:46 AM PDT 24 Jul 02 08:07:59 AM PDT 24 192921691 ps
T807 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3223655916 Jul 02 08:07:46 AM PDT 24 Jul 02 08:11:12 AM PDT 24 9072041030 ps
T808 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1018135015 Jul 02 08:07:45 AM PDT 24 Jul 02 08:09:35 AM PDT 24 3406419326 ps
T809 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2945429784 Jul 02 08:07:51 AM PDT 24 Jul 02 08:09:17 AM PDT 24 608846556 ps
T810 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2609249947 Jul 02 08:07:50 AM PDT 24 Jul 02 08:07:59 AM PDT 24 11574111 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4188985342 Jul 02 08:07:46 AM PDT 24 Jul 02 08:08:07 AM PDT 24 214198347 ps
T812 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3411567061 Jul 02 08:08:10 AM PDT 24 Jul 02 08:08:23 AM PDT 24 383637355 ps
T184 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3231170977 Jul 02 08:08:09 AM PDT 24 Jul 02 08:13:05 AM PDT 24 8854765608 ps
T813 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2652500975 Jul 02 08:08:09 AM PDT 24 Jul 02 08:08:25 AM PDT 24 161536269 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.893908985 Jul 02 08:07:48 AM PDT 24 Jul 02 08:08:06 AM PDT 24 135687730 ps
T815 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2118311324 Jul 02 08:08:03 AM PDT 24 Jul 02 08:08:12 AM PDT 24 660990107 ps
T816 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1798293453 Jul 02 08:07:58 AM PDT 24 Jul 02 08:08:06 AM PDT 24 50903840 ps
T331 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2915333567 Jul 02 08:08:14 AM PDT 24 Jul 02 08:19:34 AM PDT 24 17739811099 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.934177666 Jul 02 08:08:02 AM PDT 24 Jul 02 08:08:10 AM PDT 24 60728717 ps
T818 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4103368020 Jul 02 08:08:04 AM PDT 24 Jul 02 08:08:12 AM PDT 24 36563058 ps
T819 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2019099910 Jul 02 08:07:57 AM PDT 24 Jul 02 08:08:16 AM PDT 24 865166102 ps
T820 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1415093187 Jul 02 08:08:12 AM PDT 24 Jul 02 08:08:18 AM PDT 24 8616528 ps
T821 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1375104259 Jul 02 08:08:10 AM PDT 24 Jul 02 08:13:41 AM PDT 24 2446669941 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.848858897 Jul 02 08:08:02 AM PDT 24 Jul 02 08:08:08 AM PDT 24 14412660 ps
T823 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1995602360 Jul 02 08:08:00 AM PDT 24 Jul 02 08:08:06 AM PDT 24 12155033 ps
T824 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1527862882 Jul 02 08:08:05 AM PDT 24 Jul 02 08:08:24 AM PDT 24 413523246 ps
T825 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1901291515 Jul 02 08:07:59 AM PDT 24 Jul 02 08:08:10 AM PDT 24 339735624 ps

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2376853076
Short name T9
Test name
Test status
Simulation time 50829745838 ps
CPU time 1765.4 seconds
Started Jul 02 08:31:00 AM PDT 24
Finished Jul 02 09:00:26 AM PDT 24
Peak memory 290312 kb
Host smart-82fff481-1f7d-4a3f-b17a-95c27fac3bb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376853076 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2376853076
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3194343480
Short name T16
Test name
Test status
Simulation time 367495500062 ps
CPU time 2647.97 seconds
Started Jul 02 08:31:59 AM PDT 24
Finished Jul 02 09:16:07 AM PDT 24
Peak memory 289912 kb
Host smart-5ff547ea-27e5-4c7b-bf0b-240a5ecbbd6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194343480 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3194343480
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1416433993
Short name T34
Test name
Test status
Simulation time 1560016470 ps
CPU time 10.75 seconds
Started Jul 02 08:31:14 AM PDT 24
Finished Jul 02 08:31:25 AM PDT 24
Peak memory 270648 kb
Host smart-302f00fb-df94-4997-811a-e26078e5c102
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1416433993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1416433993
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1004031529
Short name T151
Test name
Test status
Simulation time 3499280902 ps
CPU time 63.46 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:09:24 AM PDT 24
Peak memory 240580 kb
Host smart-5158b28e-ba1e-4736-b16c-a5ef59c64c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1004031529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1004031529
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3852484520
Short name T26
Test name
Test status
Simulation time 394526961614 ps
CPU time 3357.35 seconds
Started Jul 02 08:32:26 AM PDT 24
Finished Jul 02 09:28:25 AM PDT 24
Peak memory 298540 kb
Host smart-23d35a16-3f8c-40ac-afa6-b8834c151bfb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852484520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3852484520
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3278110298
Short name T18
Test name
Test status
Simulation time 375313016226 ps
CPU time 5798.05 seconds
Started Jul 02 08:35:49 AM PDT 24
Finished Jul 02 10:12:28 AM PDT 24
Peak memory 354960 kb
Host smart-9e81b702-b4ce-44e1-a89e-2170719c74b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278110298 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3278110298
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.386110562
Short name T27
Test name
Test status
Simulation time 39599929640 ps
CPU time 2383.32 seconds
Started Jul 02 08:35:00 AM PDT 24
Finished Jul 02 09:14:45 AM PDT 24
Peak memory 282156 kb
Host smart-7f40a21f-cea9-47fe-8960-d4d33a567330
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386110562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.386110562
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3682377866
Short name T87
Test name
Test status
Simulation time 53492732339 ps
CPU time 1490.26 seconds
Started Jul 02 08:35:16 AM PDT 24
Finished Jul 02 09:00:07 AM PDT 24
Peak memory 273260 kb
Host smart-0ef56952-5801-49dd-9072-e28e2cd8d44c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682377866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3682377866
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3632064984
Short name T125
Test name
Test status
Simulation time 6331087850 ps
CPU time 210.53 seconds
Started Jul 02 08:08:10 AM PDT 24
Finished Jul 02 08:11:46 AM PDT 24
Peak memory 272564 kb
Host smart-f4c7c88d-2e7a-4c63-954e-c236daf611c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3632064984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3632064984
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1219511199
Short name T84
Test name
Test status
Simulation time 71075064643 ps
CPU time 1422.84 seconds
Started Jul 02 08:37:08 AM PDT 24
Finished Jul 02 09:00:52 AM PDT 24
Peak memory 290320 kb
Host smart-05dc53e0-34ce-4843-83f0-d16eb45a0c6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219511199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1219511199
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1968471168
Short name T127
Test name
Test status
Simulation time 15525485831 ps
CPU time 1163.3 seconds
Started Jul 02 08:07:53 AM PDT 24
Finished Jul 02 08:27:23 AM PDT 24
Peak memory 265592 kb
Host smart-c87f0333-eb35-4bf4-9ea2-b8f8c96c6459
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968471168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1968471168
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2602468824
Short name T146
Test name
Test status
Simulation time 3694749161 ps
CPU time 284.1 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:12:50 AM PDT 24
Peak memory 265416 kb
Host smart-d7aeb8ff-7d77-4fbc-9b5e-9e5cb7a490e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2602468824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2602468824
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.742595444
Short name T308
Test name
Test status
Simulation time 58883773946 ps
CPU time 3278.68 seconds
Started Jul 02 08:31:18 AM PDT 24
Finished Jul 02 09:25:57 AM PDT 24
Peak memory 289380 kb
Host smart-eed00af2-70bf-4cf8-b866-64745c6143a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742595444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.742595444
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2897234832
Short name T131
Test name
Test status
Simulation time 36461947643 ps
CPU time 1036.85 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:25:15 AM PDT 24
Peak memory 265392 kb
Host smart-6eb0ca00-c44e-414d-84af-f3c40fe5c651
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897234832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2897234832
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.985754841
Short name T91
Test name
Test status
Simulation time 332383749290 ps
CPU time 1791.26 seconds
Started Jul 02 08:36:21 AM PDT 24
Finished Jul 02 09:06:13 AM PDT 24
Peak memory 274264 kb
Host smart-7d602260-3def-4cd6-acbc-50b53857bdd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985754841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.985754841
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.725048640
Short name T29
Test name
Test status
Simulation time 9589251136 ps
CPU time 1040.43 seconds
Started Jul 02 08:31:52 AM PDT 24
Finished Jul 02 08:49:13 AM PDT 24
Peak memory 273616 kb
Host smart-d76f5a3d-7a11-4706-aedf-83443860c22b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725048640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.725048640
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1246023533
Short name T291
Test name
Test status
Simulation time 58147820802 ps
CPU time 563.77 seconds
Started Jul 02 08:37:18 AM PDT 24
Finished Jul 02 08:46:43 AM PDT 24
Peak memory 256468 kb
Host smart-5858b994-efde-4a56-8a1d-e30e56703453
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246023533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1246023533
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.493540890
Short name T326
Test name
Test status
Simulation time 11093003 ps
CPU time 1.47 seconds
Started Jul 02 08:08:18 AM PDT 24
Finished Jul 02 08:08:26 AM PDT 24
Peak memory 236624 kb
Host smart-39546361-2243-43f2-8848-344b01322c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=493540890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.493540890
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1963859447
Short name T132
Test name
Test status
Simulation time 4083227726 ps
CPU time 307.57 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:13:05 AM PDT 24
Peak memory 265472 kb
Host smart-51fbd77a-3e66-458a-b464-2b9c6b0d088d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1963859447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1963859447
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3802951892
Short name T39
Test name
Test status
Simulation time 28229695757 ps
CPU time 1751.62 seconds
Started Jul 02 08:37:32 AM PDT 24
Finished Jul 02 09:06:45 AM PDT 24
Peak memory 273320 kb
Host smart-93b67f2f-8458-407a-97f8-4f1deaf89a4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802951892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3802951892
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.606737408
Short name T53
Test name
Test status
Simulation time 17919052480 ps
CPU time 1644.38 seconds
Started Jul 02 08:31:01 AM PDT 24
Finished Jul 02 08:58:26 AM PDT 24
Peak memory 298260 kb
Host smart-94c43fa1-6499-40fe-b18e-cb5b5027ef7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606737408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.606737408
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.214636659
Short name T121
Test name
Test status
Simulation time 14619299675 ps
CPU time 989.61 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:24:37 AM PDT 24
Peak memory 273596 kb
Host smart-5858b8c7-1b58-4e75-b9aa-cadea2b948ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214636659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.214636659
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3466076319
Short name T43
Test name
Test status
Simulation time 70446420173 ps
CPU time 2237.56 seconds
Started Jul 02 08:31:32 AM PDT 24
Finished Jul 02 09:08:51 AM PDT 24
Peak memory 273408 kb
Host smart-03af6fab-b3f2-4054-9ad4-7a3e89dbfb77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466076319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3466076319
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2344659358
Short name T287
Test name
Test status
Simulation time 13387780818 ps
CPU time 523.57 seconds
Started Jul 02 08:32:03 AM PDT 24
Finished Jul 02 08:40:47 AM PDT 24
Peak memory 249212 kb
Host smart-c5e9a96e-d9f5-4e5b-a0f2-48f4f99b6962
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344659358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2344659358
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3075276453
Short name T74
Test name
Test status
Simulation time 149756138494 ps
CPU time 1779.61 seconds
Started Jul 02 08:35:16 AM PDT 24
Finished Jul 02 09:04:57 AM PDT 24
Peak memory 284200 kb
Host smart-c6ef8f5b-ad37-437d-9822-3e87cfcb7400
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075276453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3075276453
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2638853468
Short name T289
Test name
Test status
Simulation time 46841745459 ps
CPU time 508.85 seconds
Started Jul 02 08:34:23 AM PDT 24
Finished Jul 02 08:42:53 AM PDT 24
Peak memory 249372 kb
Host smart-ab4e6e9f-93be-49f4-a2de-2fe8d0df1471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638853468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2638853468
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2021620275
Short name T128
Test name
Test status
Simulation time 17111855855 ps
CPU time 1290.88 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:29:38 AM PDT 24
Peak memory 265372 kb
Host smart-a2e87006-aeb7-466e-b046-d26fb3f1c265
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021620275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2021620275
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1950468425
Short name T234
Test name
Test status
Simulation time 29264542102 ps
CPU time 380.81 seconds
Started Jul 02 08:33:34 AM PDT 24
Finished Jul 02 08:39:55 AM PDT 24
Peak memory 249396 kb
Host smart-63ff5cee-4986-4400-b06d-30a18b2b92e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950468425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1950468425
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3989235055
Short name T244
Test name
Test status
Simulation time 48554573191 ps
CPU time 2440.38 seconds
Started Jul 02 08:36:22 AM PDT 24
Finished Jul 02 09:17:03 AM PDT 24
Peak memory 290020 kb
Host smart-c41fedeb-2d09-4f09-9f2c-f65baa304390
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989235055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3989235055
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1210693332
Short name T314
Test name
Test status
Simulation time 37367509043 ps
CPU time 1193.67 seconds
Started Jul 02 08:33:42 AM PDT 24
Finished Jul 02 08:53:37 AM PDT 24
Peak memory 273836 kb
Host smart-23e34ea7-dbb6-4965-a8c5-8ec28073a367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210693332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1210693332
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1134266210
Short name T137
Test name
Test status
Simulation time 68414290673 ps
CPU time 1188.53 seconds
Started Jul 02 08:07:42 AM PDT 24
Finished Jul 02 08:27:39 AM PDT 24
Peak memory 273588 kb
Host smart-1f7d95c9-85c0-4c54-8dfe-2c1312160fb6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134266210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1134266210
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2280734477
Short name T98
Test name
Test status
Simulation time 204319762351 ps
CPU time 3691.57 seconds
Started Jul 02 08:34:53 AM PDT 24
Finished Jul 02 09:36:27 AM PDT 24
Peak memory 306740 kb
Host smart-cb41c5f4-d331-4e5d-9480-e9d17b264e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280734477 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2280734477
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.952323140
Short name T133
Test name
Test status
Simulation time 22686548039 ps
CPU time 196.14 seconds
Started Jul 02 08:07:58 AM PDT 24
Finished Jul 02 08:11:19 AM PDT 24
Peak memory 265436 kb
Host smart-b7b25f0d-1fc1-4c70-b4a3-8a50ebdd22da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=952323140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.952323140
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1205300926
Short name T52
Test name
Test status
Simulation time 221306764676 ps
CPU time 3883.07 seconds
Started Jul 02 08:32:18 AM PDT 24
Finished Jul 02 09:37:03 AM PDT 24
Peak memory 306172 kb
Host smart-3fa47dfd-5fa6-4a4d-823b-b40c4cd61462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205300926 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1205300926
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3903590648
Short name T323
Test name
Test status
Simulation time 8317462 ps
CPU time 1.4 seconds
Started Jul 02 08:08:13 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 236644 kb
Host smart-6decd6d2-f818-4020-9ca2-ee26f19d31f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3903590648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3903590648
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4001304802
Short name T286
Test name
Test status
Simulation time 130816397243 ps
CPU time 713.14 seconds
Started Jul 02 08:35:01 AM PDT 24
Finished Jul 02 08:46:56 AM PDT 24
Peak memory 249256 kb
Host smart-29c2d7db-0585-43a0-a033-f9c2b36c2dc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001304802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4001304802
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3473203460
Short name T49
Test name
Test status
Simulation time 496461316839 ps
CPU time 1897.05 seconds
Started Jul 02 08:32:50 AM PDT 24
Finished Jul 02 09:04:28 AM PDT 24
Peak memory 282776 kb
Host smart-19eeaafe-90fa-4b7c-b672-e12de07b3c12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473203460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3473203460
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.444595428
Short name T309
Test name
Test status
Simulation time 317386204769 ps
CPU time 2946.11 seconds
Started Jul 02 08:35:31 AM PDT 24
Finished Jul 02 09:24:39 AM PDT 24
Peak memory 282160 kb
Host smart-e4decf8d-e1ac-4518-8d29-f6a5348ee874
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444595428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.444595428
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3738240646
Short name T148
Test name
Test status
Simulation time 27336512769 ps
CPU time 945.59 seconds
Started Jul 02 08:07:58 AM PDT 24
Finished Jul 02 08:23:48 AM PDT 24
Peak memory 265384 kb
Host smart-49412268-9086-4098-b680-4c4cdf81ea73
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738240646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3738240646
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.4264572871
Short name T306
Test name
Test status
Simulation time 26183010795 ps
CPU time 1441.34 seconds
Started Jul 02 08:35:55 AM PDT 24
Finished Jul 02 08:59:57 AM PDT 24
Peak memory 265724 kb
Host smart-3d45427d-ca87-435d-a999-d5e5f3ee4eae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264572871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4264572871
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1895764594
Short name T277
Test name
Test status
Simulation time 54726548295 ps
CPU time 4804.94 seconds
Started Jul 02 08:36:34 AM PDT 24
Finished Jul 02 09:56:40 AM PDT 24
Peak memory 355552 kb
Host smart-86008431-d0f2-46cc-9079-3b0d3c34d3df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895764594 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1895764594
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2520480438
Short name T78
Test name
Test status
Simulation time 193866798928 ps
CPU time 3005.58 seconds
Started Jul 02 08:32:32 AM PDT 24
Finished Jul 02 09:22:39 AM PDT 24
Peak memory 300656 kb
Host smart-f7ae75b2-c08a-4d31-96a9-deb8c4fb4a03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520480438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2520480438
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2285006735
Short name T118
Test name
Test status
Simulation time 837364962 ps
CPU time 99.71 seconds
Started Jul 02 08:08:06 AM PDT 24
Finished Jul 02 08:09:51 AM PDT 24
Peak memory 266536 kb
Host smart-d76c1fc6-663e-4686-bc09-7b29b08036f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2285006735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2285006735
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.4248807557
Short name T304
Test name
Test status
Simulation time 45431671510 ps
CPU time 459.59 seconds
Started Jul 02 08:32:06 AM PDT 24
Finished Jul 02 08:39:47 AM PDT 24
Peak memory 249356 kb
Host smart-82f0bfd3-931d-4271-9585-20bb9b77d819
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248807557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.4248807557
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3114784349
Short name T299
Test name
Test status
Simulation time 260508956366 ps
CPU time 605.14 seconds
Started Jul 02 08:32:35 AM PDT 24
Finished Jul 02 08:42:41 AM PDT 24
Peak memory 248944 kb
Host smart-fd23589e-e6f6-40f6-b665-fcfa566d120e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114784349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3114784349
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2945365682
Short name T246
Test name
Test status
Simulation time 980203557 ps
CPU time 60.78 seconds
Started Jul 02 08:34:49 AM PDT 24
Finished Jul 02 08:35:52 AM PDT 24
Peak memory 257092 kb
Host smart-3cc93496-9ea3-458e-ad6c-ab3c0893e227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
65682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2945365682
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.41085215
Short name T313
Test name
Test status
Simulation time 54950680086 ps
CPU time 2991.6 seconds
Started Jul 02 08:31:33 AM PDT 24
Finished Jul 02 09:21:25 AM PDT 24
Peak memory 290260 kb
Host smart-cbe73cf4-f6ef-49cd-b9e9-c93277cc296c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41085215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.41085215
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3437456924
Short name T181
Test name
Test status
Simulation time 34167306 ps
CPU time 5.94 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:13 AM PDT 24
Peak memory 240428 kb
Host smart-23bd0b52-ac60-4a8d-9852-0e891e7dc269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3437456924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3437456924
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3855197757
Short name T85
Test name
Test status
Simulation time 1844453473128 ps
CPU time 9154.83 seconds
Started Jul 02 08:32:36 AM PDT 24
Finished Jul 02 11:05:13 AM PDT 24
Peak memory 323108 kb
Host smart-5492077d-d13f-49b8-8ac7-202b5c4c394e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855197757 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3855197757
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1859400001
Short name T144
Test name
Test status
Simulation time 28133922705 ps
CPU time 590.05 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:18:05 AM PDT 24
Peak memory 269440 kb
Host smart-861187a8-49d6-4e1a-ba87-78e546ef045b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859400001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1859400001
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1115466734
Short name T169
Test name
Test status
Simulation time 41394260 ps
CPU time 3.74 seconds
Started Jul 02 08:07:44 AM PDT 24
Finished Jul 02 08:07:55 AM PDT 24
Peak memory 237828 kb
Host smart-dfc02f1e-8458-4ae5-9c15-493bf904c88c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1115466734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1115466734
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3008224731
Short name T203
Test name
Test status
Simulation time 254601601 ps
CPU time 3.19 seconds
Started Jul 02 08:31:02 AM PDT 24
Finished Jul 02 08:31:06 AM PDT 24
Peak memory 249452 kb
Host smart-a92b911c-fae7-4d41-bc6f-4c5da61df685
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3008224731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3008224731
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.429026830
Short name T193
Test name
Test status
Simulation time 64455502 ps
CPU time 3.42 seconds
Started Jul 02 08:31:01 AM PDT 24
Finished Jul 02 08:31:05 AM PDT 24
Peak memory 249588 kb
Host smart-2c5fa1c9-6c83-4c71-90e0-7f5aa2a4fbf4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=429026830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.429026830
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.478169402
Short name T196
Test name
Test status
Simulation time 21665680 ps
CPU time 2.76 seconds
Started Jul 02 08:32:03 AM PDT 24
Finished Jul 02 08:32:06 AM PDT 24
Peak memory 249588 kb
Host smart-794e4eb2-352c-45a2-8828-91497d9dcf7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=478169402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.478169402
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.4157539350
Short name T186
Test name
Test status
Simulation time 114185363 ps
CPU time 3.23 seconds
Started Jul 02 08:32:13 AM PDT 24
Finished Jul 02 08:32:17 AM PDT 24
Peak memory 249504 kb
Host smart-0bffe1f2-47f2-49ca-8442-04d0469c34ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4157539350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.4157539350
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.215254171
Short name T42
Test name
Test status
Simulation time 89945207176 ps
CPU time 1488.93 seconds
Started Jul 02 08:32:02 AM PDT 24
Finished Jul 02 08:56:52 AM PDT 24
Peak memory 290736 kb
Host smart-aa34034a-cc0f-41ea-aac1-8c7bf5a88391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215254171 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.215254171
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2546643055
Short name T311
Test name
Test status
Simulation time 20732585954 ps
CPU time 1834.4 seconds
Started Jul 02 08:32:17 AM PDT 24
Finished Jul 02 09:02:52 AM PDT 24
Peak memory 290340 kb
Host smart-e4703b18-7dc2-4646-9c02-f22c29bd72da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546643055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2546643055
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3943739800
Short name T262
Test name
Test status
Simulation time 131169597634 ps
CPU time 2230.48 seconds
Started Jul 02 08:31:10 AM PDT 24
Finished Jul 02 09:08:21 AM PDT 24
Peak memory 282088 kb
Host smart-0d886078-60da-4557-97e0-8011e308e9c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943739800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3943739800
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.214499449
Short name T243
Test name
Test status
Simulation time 148811925685 ps
CPU time 2318 seconds
Started Jul 02 08:33:14 AM PDT 24
Finished Jul 02 09:11:53 AM PDT 24
Peak memory 289992 kb
Host smart-8d8ec306-dc2f-4673-9572-3d2b3590ac70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214499449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.214499449
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.4069625687
Short name T62
Test name
Test status
Simulation time 186013656670 ps
CPU time 2920.96 seconds
Started Jul 02 08:33:28 AM PDT 24
Finished Jul 02 09:22:10 AM PDT 24
Peak memory 300280 kb
Host smart-c2d19650-6cf0-4d5f-a9f2-7ae20fbb551a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069625687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.4069625687
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1622475714
Short name T239
Test name
Test status
Simulation time 1242540907044 ps
CPU time 7789.8 seconds
Started Jul 02 08:33:51 AM PDT 24
Finished Jul 02 10:43:42 AM PDT 24
Peak memory 354644 kb
Host smart-2e0481e1-9249-4e6d-ae18-09306e0ea895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622475714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1622475714
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2655184428
Short name T260
Test name
Test status
Simulation time 30563085903 ps
CPU time 1789.26 seconds
Started Jul 02 08:37:07 AM PDT 24
Finished Jul 02 09:06:57 AM PDT 24
Peak memory 290136 kb
Host smart-7025cc54-9239-4a8f-abc3-c49aaf6f3593
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655184428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2655184428
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2167365987
Short name T141
Test name
Test status
Simulation time 8058456074 ps
CPU time 554.25 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:17:07 AM PDT 24
Peak memory 266564 kb
Host smart-15a5848a-78f3-404f-906b-6644eb0ea876
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167365987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2167365987
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3148895567
Short name T168
Test name
Test status
Simulation time 1804995491 ps
CPU time 65.75 seconds
Started Jul 02 08:08:08 AM PDT 24
Finished Jul 02 08:09:18 AM PDT 24
Peak memory 240484 kb
Host smart-907381c5-a3fd-45d0-9e1b-c844a7dafb49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3148895567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3148895567
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3759735986
Short name T163
Test name
Test status
Simulation time 302207428 ps
CPU time 22.44 seconds
Started Jul 02 08:07:45 AM PDT 24
Finished Jul 02 08:08:15 AM PDT 24
Peak memory 240540 kb
Host smart-32c59769-5297-4763-8915-31db3ab27513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3759735986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3759735986
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2411160662
Short name T281
Test name
Test status
Simulation time 192157884970 ps
CPU time 1484.21 seconds
Started Jul 02 08:31:50 AM PDT 24
Finished Jul 02 08:56:35 AM PDT 24
Peak memory 290200 kb
Host smart-17476446-a26e-4fd3-a56a-811d35700d53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411160662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2411160662
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.317117575
Short name T734
Test name
Test status
Simulation time 65168418 ps
CPU time 1.44 seconds
Started Jul 02 08:07:45 AM PDT 24
Finished Jul 02 08:07:54 AM PDT 24
Peak memory 236644 kb
Host smart-fe12ee20-2c63-4006-b139-3d2684cd973c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=317117575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.317117575
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1499030973
Short name T140
Test name
Test status
Simulation time 6057019600 ps
CPU time 446.93 seconds
Started Jul 02 08:08:06 AM PDT 24
Finished Jul 02 08:15:38 AM PDT 24
Peak memory 265352 kb
Host smart-b8170a4f-d79b-46c6-8af8-4346a3188384
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499030973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1499030973
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3312323647
Short name T270
Test name
Test status
Simulation time 53605691755 ps
CPU time 2849.89 seconds
Started Jul 02 08:30:58 AM PDT 24
Finished Jul 02 09:18:29 AM PDT 24
Peak memory 290212 kb
Host smart-cab7b3c2-8da1-43b6-8571-8c66229f96c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312323647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3312323647
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1122014899
Short name T258
Test name
Test status
Simulation time 91887899482 ps
CPU time 2392.64 seconds
Started Jul 02 08:31:04 AM PDT 24
Finished Jul 02 09:10:57 AM PDT 24
Peak memory 306440 kb
Host smart-aa711012-a775-44e0-92c0-f40bcd6afd5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122014899 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1122014899
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2843543134
Short name T274
Test name
Test status
Simulation time 316716558 ps
CPU time 20.75 seconds
Started Jul 02 08:31:01 AM PDT 24
Finished Jul 02 08:31:23 AM PDT 24
Peak memory 248912 kb
Host smart-23fc02d9-ae84-4fbd-85e3-0766daae7db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28435
43134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2843543134
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3082820471
Short name T63
Test name
Test status
Simulation time 70173763219 ps
CPU time 1265.74 seconds
Started Jul 02 08:32:04 AM PDT 24
Finished Jul 02 08:53:11 AM PDT 24
Peak memory 290404 kb
Host smart-08226584-8d4d-4ada-8b3f-3fe4a33b48f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082820471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3082820471
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4022758866
Short name T256
Test name
Test status
Simulation time 44336716444 ps
CPU time 2191.52 seconds
Started Jul 02 08:33:06 AM PDT 24
Finished Jul 02 09:09:38 AM PDT 24
Peak memory 298668 kb
Host smart-049147c5-03cf-4524-9b23-218e145d4cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022758866 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4022758866
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2667195789
Short name T280
Test name
Test status
Simulation time 1123404871 ps
CPU time 64.1 seconds
Started Jul 02 08:33:10 AM PDT 24
Finished Jul 02 08:34:14 AM PDT 24
Peak memory 257456 kb
Host smart-fa67a753-8fca-400b-af44-b254744fe9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671
95789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2667195789
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1805219421
Short name T75
Test name
Test status
Simulation time 725446657 ps
CPU time 52.35 seconds
Started Jul 02 08:33:37 AM PDT 24
Finished Jul 02 08:34:30 AM PDT 24
Peak memory 257384 kb
Host smart-28abd29d-cb69-4691-9c56-7ac21d7314b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18052
19421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1805219421
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2135044399
Short name T251
Test name
Test status
Simulation time 50775972074 ps
CPU time 1633.64 seconds
Started Jul 02 08:34:19 AM PDT 24
Finished Jul 02 09:01:33 AM PDT 24
Peak memory 300680 kb
Host smart-49e660d1-3d2e-4f00-9431-e1ebfea4f287
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135044399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2135044399
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2690093436
Short name T249
Test name
Test status
Simulation time 235360836 ps
CPU time 29.99 seconds
Started Jul 02 08:34:32 AM PDT 24
Finished Jul 02 08:35:04 AM PDT 24
Peak memory 249164 kb
Host smart-85a6c77b-e6ae-44cf-ab08-55ed3ba51367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26900
93436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2690093436
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2861405558
Short name T31
Test name
Test status
Simulation time 2510685119 ps
CPU time 39.23 seconds
Started Jul 02 08:34:48 AM PDT 24
Finished Jul 02 08:35:28 AM PDT 24
Peak memory 249268 kb
Host smart-1c4a9c99-085d-4008-b516-36dd8d20da6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28614
05558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2861405558
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.308847230
Short name T271
Test name
Test status
Simulation time 11159466377 ps
CPU time 70.14 seconds
Started Jul 02 08:36:17 AM PDT 24
Finished Jul 02 08:37:28 AM PDT 24
Peak memory 256840 kb
Host smart-2d8504c1-d8cc-45bc-ad79-257f9f22d915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30884
7230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.308847230
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.4175402403
Short name T173
Test name
Test status
Simulation time 25285648856 ps
CPU time 2670.69 seconds
Started Jul 02 08:37:11 AM PDT 24
Finished Jul 02 09:21:42 AM PDT 24
Peak memory 322864 kb
Host smart-fed6f362-24e9-446b-955a-8f1f20cf280d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175402403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.4175402403
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2188931388
Short name T158
Test name
Test status
Simulation time 207515676 ps
CPU time 4.35 seconds
Started Jul 02 08:07:49 AM PDT 24
Finished Jul 02 08:08:00 AM PDT 24
Peak memory 237568 kb
Host smart-52a44fb9-ee8a-428a-93a4-47603e4a9700
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2188931388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2188931388
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.459258575
Short name T159
Test name
Test status
Simulation time 96771024 ps
CPU time 4.18 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:16 AM PDT 24
Peak memory 237744 kb
Host smart-b7c20fed-801d-4b66-9bfe-dd4555faa8c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=459258575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.459258575
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.251353298
Short name T161
Test name
Test status
Simulation time 40672635 ps
CPU time 3.49 seconds
Started Jul 02 08:07:52 AM PDT 24
Finished Jul 02 08:08:03 AM PDT 24
Peak memory 237528 kb
Host smart-71718498-e710-4cb7-9f0c-a8fd834e99df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=251353298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.251353298
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3429078270
Short name T162
Test name
Test status
Simulation time 156693619 ps
CPU time 25.03 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:08:27 AM PDT 24
Peak memory 240556 kb
Host smart-b241817a-1e4e-42e2-bb12-b5125707ccf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3429078270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3429078270
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1081346009
Short name T166
Test name
Test status
Simulation time 35806732 ps
CPU time 2.14 seconds
Started Jul 02 08:07:58 AM PDT 24
Finished Jul 02 08:08:05 AM PDT 24
Peak memory 237492 kb
Host smart-8c2a4c28-40d6-49c9-b291-08cbd52b3b01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1081346009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1081346009
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1346637668
Short name T157
Test name
Test status
Simulation time 657705749 ps
CPU time 25.48 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:08:34 AM PDT 24
Peak memory 237680 kb
Host smart-81de8756-2a52-4c07-b0ea-73a84236fa7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1346637668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1346637668
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2564515167
Short name T164
Test name
Test status
Simulation time 2361012974 ps
CPU time 47.13 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:53 AM PDT 24
Peak memory 239636 kb
Host smart-e6782adb-61c8-4a7e-a9f9-bc3d6c1e0b4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2564515167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2564515167
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2355226102
Short name T150
Test name
Test status
Simulation time 3553845669 ps
CPU time 69.27 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:09:16 AM PDT 24
Peak memory 238940 kb
Host smart-ee49c36a-df27-42f5-8d33-eb75f3146dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2355226102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2355226102
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3244380687
Short name T165
Test name
Test status
Simulation time 597044656 ps
CPU time 39.16 seconds
Started Jul 02 08:08:06 AM PDT 24
Finished Jul 02 08:08:49 AM PDT 24
Peak memory 245764 kb
Host smart-2a0f1c8d-41ab-428c-879a-783fe7a570bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3244380687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3244380687
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3872037978
Short name T172
Test name
Test status
Simulation time 59813588 ps
CPU time 2.2 seconds
Started Jul 02 08:08:08 AM PDT 24
Finished Jul 02 08:08:14 AM PDT 24
Peak memory 238728 kb
Host smart-2afe5967-c307-49da-9176-ee2bb72705c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3872037978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3872037978
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3043283736
Short name T156
Test name
Test status
Simulation time 100140343 ps
CPU time 2.5 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:08:16 AM PDT 24
Peak memory 237588 kb
Host smart-d415467c-e96e-49d3-9fa1-004cfa392377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3043283736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3043283736
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1133076779
Short name T167
Test name
Test status
Simulation time 4719810947 ps
CPU time 89.19 seconds
Started Jul 02 08:08:11 AM PDT 24
Finished Jul 02 08:09:45 AM PDT 24
Peak memory 246212 kb
Host smart-87a14f57-5770-47f6-ac5b-741f5cbbb337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1133076779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1133076779
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1145779277
Short name T171
Test name
Test status
Simulation time 305184490 ps
CPU time 22.32 seconds
Started Jul 02 08:07:55 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 239604 kb
Host smart-821a0263-eaac-49d4-a3aa-2c23f6779a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1145779277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1145779277
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3016671159
Short name T152
Test name
Test status
Simulation time 51418478 ps
CPU time 3.37 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:08:05 AM PDT 24
Peak memory 237432 kb
Host smart-2d88c09b-dd39-45b8-8298-474e796b2078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3016671159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3016671159
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2379895165
Short name T160
Test name
Test status
Simulation time 331781447 ps
CPU time 43.96 seconds
Started Jul 02 08:08:00 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 240484 kb
Host smart-2285398b-489b-4843-9ae4-e48eb95a2747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2379895165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2379895165
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1856016772
Short name T22
Test name
Test status
Simulation time 9138951808 ps
CPU time 196.24 seconds
Started Jul 02 08:32:30 AM PDT 24
Finished Jul 02 08:35:47 AM PDT 24
Peak memory 249372 kb
Host smart-9f9fe1c0-dcb7-42e5-80f1-9c41ebe643d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856016772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1856016772
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3898914840
Short name T24
Test name
Test status
Simulation time 579593845 ps
CPU time 19.24 seconds
Started Jul 02 08:32:31 AM PDT 24
Finished Jul 02 08:32:51 AM PDT 24
Peak memory 256996 kb
Host smart-2434a712-404e-4577-a8f6-3b880cf783ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38989
14840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3898914840
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.963461746
Short name T23
Test name
Test status
Simulation time 8096383427 ps
CPU time 29.95 seconds
Started Jul 02 08:36:16 AM PDT 24
Finished Jul 02 08:36:47 AM PDT 24
Peak memory 255952 kb
Host smart-ba88bc46-c009-4512-b8fb-620627a0d3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96346
1746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.963461746
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2167585197
Short name T183
Test name
Test status
Simulation time 1131382972 ps
CPU time 67.2 seconds
Started Jul 02 08:07:44 AM PDT 24
Finished Jul 02 08:09:00 AM PDT 24
Peak memory 237604 kb
Host smart-ad1c9f17-0a43-4e3c-aab6-08e1b489f1fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2167585197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2167585197
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3223655916
Short name T807
Test name
Test status
Simulation time 9072041030 ps
CPU time 198.72 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 237672 kb
Host smart-25fbc0c9-a7aa-4336-a9c9-31636614de31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3223655916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3223655916
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1716633222
Short name T766
Test name
Test status
Simulation time 160437469 ps
CPU time 6.2 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:08:00 AM PDT 24
Peak memory 248696 kb
Host smart-aa17e265-3340-4741-b93b-3ab744d8be9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1716633222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1716633222
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.893908985
Short name T814
Test name
Test status
Simulation time 135687730 ps
CPU time 10.15 seconds
Started Jul 02 08:07:48 AM PDT 24
Finished Jul 02 08:08:06 AM PDT 24
Peak memory 239940 kb
Host smart-088653a3-9844-41a0-86e3-bb9657134b42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893908985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.893908985
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3610998575
Short name T804
Test name
Test status
Simulation time 182953698 ps
CPU time 8.49 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:08:02 AM PDT 24
Peak memory 240508 kb
Host smart-4269b1df-859a-45ac-b38b-706d7ca78dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3610998575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3610998575
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2465926699
Short name T733
Test name
Test status
Simulation time 556445820 ps
CPU time 41.54 seconds
Started Jul 02 08:07:48 AM PDT 24
Finished Jul 02 08:08:37 AM PDT 24
Peak memory 248716 kb
Host smart-149d0fb9-5212-490f-a724-42942dad6434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2465926699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2465926699
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.184457978
Short name T124
Test name
Test status
Simulation time 1964274662 ps
CPU time 142.85 seconds
Started Jul 02 08:07:50 AM PDT 24
Finished Jul 02 08:10:20 AM PDT 24
Peak memory 267640 kb
Host smart-2f85927a-cc89-4bb0-9c6d-bee8be366238
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=184457978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.184457978
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4188985342
Short name T811
Test name
Test status
Simulation time 214198347 ps
CPU time 13.08 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:08:07 AM PDT 24
Peak memory 247704 kb
Host smart-359bfdf9-3568-4651-afaf-b0ddef2ea134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4188985342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4188985342
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1321608655
Short name T176
Test name
Test status
Simulation time 7527889238 ps
CPU time 122.2 seconds
Started Jul 02 08:07:47 AM PDT 24
Finished Jul 02 08:09:57 AM PDT 24
Peak memory 237668 kb
Host smart-7fc7fa7d-bf52-4275-94f2-5dc546e0f69f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1321608655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1321608655
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1018135015
Short name T808
Test name
Test status
Simulation time 3406419326 ps
CPU time 102.12 seconds
Started Jul 02 08:07:45 AM PDT 24
Finished Jul 02 08:09:35 AM PDT 24
Peak memory 240624 kb
Host smart-ad13f5b4-35c9-4d3c-9812-188c10cd4f60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1018135015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1018135015
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4272835428
Short name T801
Test name
Test status
Simulation time 347438199 ps
CPU time 4.72 seconds
Started Jul 02 08:07:47 AM PDT 24
Finished Jul 02 08:08:00 AM PDT 24
Peak memory 248696 kb
Host smart-68698de7-cd00-4e61-b75b-c6a8b464bf3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4272835428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4272835428
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.858103479
Short name T757
Test name
Test status
Simulation time 297074866 ps
CPU time 11.37 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:08:10 AM PDT 24
Peak memory 255528 kb
Host smart-b979ab8f-b7e1-44d3-8e6e-93e667b0abf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858103479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.858103479
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3475692789
Short name T806
Test name
Test status
Simulation time 192921691 ps
CPU time 4.75 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:07:59 AM PDT 24
Peak memory 237604 kb
Host smart-74756278-973e-40ad-a8c9-2509641780fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3475692789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3475692789
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3316503248
Short name T707
Test name
Test status
Simulation time 22829155 ps
CPU time 1.33 seconds
Started Jul 02 08:07:50 AM PDT 24
Finished Jul 02 08:07:59 AM PDT 24
Peak memory 235684 kb
Host smart-5c5147a2-3061-460b-b529-1f92eb087621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3316503248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3316503248
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1550608013
Short name T730
Test name
Test status
Simulation time 1219872043 ps
CPU time 17.9 seconds
Started Jul 02 08:07:47 AM PDT 24
Finished Jul 02 08:08:13 AM PDT 24
Peak memory 244832 kb
Host smart-b8722de9-3c96-427b-b6f7-d5400cf83b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1550608013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1550608013
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3826099833
Short name T142
Test name
Test status
Simulation time 2470958147 ps
CPU time 165.7 seconds
Started Jul 02 08:07:48 AM PDT 24
Finished Jul 02 08:10:42 AM PDT 24
Peak memory 264536 kb
Host smart-02b8df36-bf18-4685-a54e-ec6d7a1f352c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3826099833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3826099833
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1291676150
Short name T789
Test name
Test status
Simulation time 1762253093 ps
CPU time 22.73 seconds
Started Jul 02 08:07:43 AM PDT 24
Finished Jul 02 08:08:14 AM PDT 24
Peak memory 248616 kb
Host smart-e32a162b-cdb7-4994-9c44-b6442d86ac50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1291676150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1291676150
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.411444334
Short name T796
Test name
Test status
Simulation time 296226288 ps
CPU time 7.49 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:08:14 AM PDT 24
Peak memory 240576 kb
Host smart-9a53ce54-f0b8-40e3-acd2-39ee91dbed0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411444334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.411444334
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1527651525
Short name T788
Test name
Test status
Simulation time 19669845 ps
CPU time 3.32 seconds
Started Jul 02 08:08:00 AM PDT 24
Finished Jul 02 08:08:08 AM PDT 24
Peak memory 236588 kb
Host smart-a1fd6530-39f5-4074-beac-e138ad0c5476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1527651525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1527651525
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.848858897
Short name T822
Test name
Test status
Simulation time 14412660 ps
CPU time 1.35 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:08 AM PDT 24
Peak memory 235604 kb
Host smart-5e1e58bc-da43-4ac0-b8d9-6cb6d40cd7b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=848858897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.848858897
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3335436137
Short name T764
Test name
Test status
Simulation time 1301814918 ps
CPU time 45.85 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:52 AM PDT 24
Peak memory 245772 kb
Host smart-e29dca1c-4793-420e-a076-16c1269e2026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3335436137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3335436137
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4234885902
Short name T704
Test name
Test status
Simulation time 764762206 ps
CPU time 7.94 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:08:17 AM PDT 24
Peak memory 249836 kb
Host smart-c5f5282e-4102-402a-b693-020f6edcf868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4234885902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4234885902
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1853781424
Short name T794
Test name
Test status
Simulation time 77394315 ps
CPU time 5.56 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:17 AM PDT 24
Peak memory 240288 kb
Host smart-fb86799f-27e5-49b3-bbb6-575e3019d385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853781424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1853781424
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.934177666
Short name T817
Test name
Test status
Simulation time 60728717 ps
CPU time 4.73 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:10 AM PDT 24
Peak memory 236620 kb
Host smart-5ebb1bbf-f723-494e-807d-a948d1e63134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=934177666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.934177666
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1995602360
Short name T823
Test name
Test status
Simulation time 12155033 ps
CPU time 1.37 seconds
Started Jul 02 08:08:00 AM PDT 24
Finished Jul 02 08:08:06 AM PDT 24
Peak memory 236628 kb
Host smart-1f291e79-d411-418f-8906-ae59d1f60a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1995602360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1995602360
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1490893924
Short name T775
Test name
Test status
Simulation time 698154162 ps
CPU time 26.2 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:08:33 AM PDT 24
Peak memory 248744 kb
Host smart-43ee55c4-c865-4fd3-997a-cbf14d21b3de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1490893924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1490893924
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.59008342
Short name T135
Test name
Test status
Simulation time 8667383902 ps
CPU time 170.89 seconds
Started Jul 02 08:08:00 AM PDT 24
Finished Jul 02 08:10:55 AM PDT 24
Peak memory 265468 kb
Host smart-d2108d1e-ebfa-480e-a666-a8a388778950
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59008342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_error
s.59008342
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2410204745
Short name T751
Test name
Test status
Simulation time 347500869 ps
CPU time 24.39 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:08:32 AM PDT 24
Peak memory 256136 kb
Host smart-d6d89640-0571-44bd-977f-01a6eb288082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2410204745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2410204745
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2118311324
Short name T815
Test name
Test status
Simulation time 660990107 ps
CPU time 4.32 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:08:12 AM PDT 24
Peak memory 237548 kb
Host smart-2944d3de-bf8c-4d4d-819c-6d7baa912fe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118311324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2118311324
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3009195516
Short name T777
Test name
Test status
Simulation time 10185261 ps
CPU time 1.55 seconds
Started Jul 02 08:08:01 AM PDT 24
Finished Jul 02 08:08:07 AM PDT 24
Peak memory 237592 kb
Host smart-dddbffe3-20e5-4df4-b198-c336f3f67d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3009195516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3009195516
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2099479012
Short name T741
Test name
Test status
Simulation time 1260370021 ps
CPU time 19.3 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:26 AM PDT 24
Peak memory 245816 kb
Host smart-dec7d0cf-4148-4c07-a0bd-4a5571fe53b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2099479012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2099479012
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1189995455
Short name T120
Test name
Test status
Simulation time 6959243548 ps
CPU time 227.86 seconds
Started Jul 02 08:08:01 AM PDT 24
Finished Jul 02 08:11:53 AM PDT 24
Peak memory 265476 kb
Host smart-ba589e7c-b9c6-4fd0-87d1-048691b4744e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1189995455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1189995455
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4256889472
Short name T138
Test name
Test status
Simulation time 66732113173 ps
CPU time 1163.98 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:27:32 AM PDT 24
Peak memory 265392 kb
Host smart-313798b8-75a5-4f70-8dc8-154820d57e6b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256889472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4256889472
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1448806589
Short name T785
Test name
Test status
Simulation time 25544060 ps
CPU time 3.96 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:10 AM PDT 24
Peak memory 252304 kb
Host smart-95d32206-7825-4ad3-b9a4-1a8fb9ef1b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1448806589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1448806589
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4224870699
Short name T771
Test name
Test status
Simulation time 95256847 ps
CPU time 2.29 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:08:09 AM PDT 24
Peak memory 237612 kb
Host smart-666e18d7-960c-47f1-9365-703bfb043b36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4224870699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4224870699
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1888870655
Short name T755
Test name
Test status
Simulation time 146028969 ps
CPU time 10.8 seconds
Started Jul 02 08:08:08 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 251844 kb
Host smart-01cd2ea7-a131-441c-a9b5-e5accbbbf361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888870655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1888870655
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3464874444
Short name T710
Test name
Test status
Simulation time 126831599 ps
CPU time 5.36 seconds
Started Jul 02 08:08:06 AM PDT 24
Finished Jul 02 08:08:16 AM PDT 24
Peak memory 237572 kb
Host smart-d3603e8e-1a18-44d2-bdb7-3e2509a6acda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3464874444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3464874444
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1974573872
Short name T783
Test name
Test status
Simulation time 8591983 ps
CPU time 1.54 seconds
Started Jul 02 08:07:59 AM PDT 24
Finished Jul 02 08:08:05 AM PDT 24
Peak memory 236636 kb
Host smart-b26c1a6d-00da-45b5-811f-aa00a999bd9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1974573872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1974573872
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1527862882
Short name T824
Test name
Test status
Simulation time 413523246 ps
CPU time 14.43 seconds
Started Jul 02 08:08:05 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 240512 kb
Host smart-7c73aa73-2bf3-4629-8379-918bd7e353f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1527862882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1527862882
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2731315121
Short name T790
Test name
Test status
Simulation time 6127221761 ps
CPU time 160.94 seconds
Started Jul 02 08:08:00 AM PDT 24
Finished Jul 02 08:10:46 AM PDT 24
Peak memory 265408 kb
Host smart-d4c26983-e15d-4743-83c3-892d708f3096
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2731315121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2731315121
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1166274190
Short name T712
Test name
Test status
Simulation time 337994594 ps
CPU time 8.31 seconds
Started Jul 02 08:08:03 AM PDT 24
Finished Jul 02 08:08:15 AM PDT 24
Peak memory 248820 kb
Host smart-88a09179-475f-463d-9219-f4dab924607d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1166274190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1166274190
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1660386205
Short name T725
Test name
Test status
Simulation time 667893586 ps
CPU time 11.36 seconds
Started Jul 02 08:08:05 AM PDT 24
Finished Jul 02 08:08:21 AM PDT 24
Peak memory 249836 kb
Host smart-5de6099f-d548-4b2d-ab67-b1cbfd22a2c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660386205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1660386205
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4103368020
Short name T818
Test name
Test status
Simulation time 36563058 ps
CPU time 3.43 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:08:12 AM PDT 24
Peak memory 236632 kb
Host smart-0b6f4c3c-4547-412e-946c-52be5f51d49f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4103368020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4103368020
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4086435257
Short name T770
Test name
Test status
Simulation time 11137720 ps
CPU time 1.56 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:13 AM PDT 24
Peak memory 237404 kb
Host smart-c8bda276-bc83-46c2-b37f-53656a793afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4086435257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4086435257
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1579660255
Short name T799
Test name
Test status
Simulation time 507122315 ps
CPU time 37 seconds
Started Jul 02 08:08:06 AM PDT 24
Finished Jul 02 08:08:47 AM PDT 24
Peak memory 245768 kb
Host smart-91c2f7ff-f627-4bd7-b6a8-4da2d9eff685
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1579660255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1579660255
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1291605572
Short name T116
Test name
Test status
Simulation time 41409191545 ps
CPU time 188.43 seconds
Started Jul 02 08:08:08 AM PDT 24
Finished Jul 02 08:11:21 AM PDT 24
Peak memory 265432 kb
Host smart-d2e62f8d-b9d5-4b53-b0ac-99e4108701a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1291605572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1291605572
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.159641511
Short name T117
Test name
Test status
Simulation time 13383475691 ps
CPU time 340.46 seconds
Started Jul 02 08:08:08 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 265384 kb
Host smart-ad03efb3-db62-469e-9cfb-5e9044b00372
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159641511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.159641511
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.782251739
Short name T759
Test name
Test status
Simulation time 145324312 ps
CPU time 5.15 seconds
Started Jul 02 08:08:05 AM PDT 24
Finished Jul 02 08:08:14 AM PDT 24
Peak memory 250312 kb
Host smart-ebc74f78-449b-48ce-82f9-54b9da8f37c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=782251739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.782251739
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3411567061
Short name T812
Test name
Test status
Simulation time 383637355 ps
CPU time 8.26 seconds
Started Jul 02 08:08:10 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 238264 kb
Host smart-2fed4969-5ac7-4b00-8989-22925e172982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411567061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3411567061
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3183903429
Short name T781
Test name
Test status
Simulation time 23563670 ps
CPU time 3.44 seconds
Started Jul 02 08:08:06 AM PDT 24
Finished Jul 02 08:08:14 AM PDT 24
Peak memory 237596 kb
Host smart-f3486716-8400-42de-a76c-05ff093d6d8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3183903429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3183903429
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1522044069
Short name T779
Test name
Test status
Simulation time 14162846 ps
CPU time 1.26 seconds
Started Jul 02 08:08:08 AM PDT 24
Finished Jul 02 08:08:13 AM PDT 24
Peak memory 237612 kb
Host smart-54ae4a72-9ada-40fe-9dfb-498b29f39265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1522044069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1522044069
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.907777418
Short name T745
Test name
Test status
Simulation time 1541040415 ps
CPU time 11.53 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 245672 kb
Host smart-b509d958-a763-4e8d-98a1-b26f38901d05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=907777418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.907777418
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.868459708
Short name T727
Test name
Test status
Simulation time 85740169 ps
CPU time 5.49 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:17 AM PDT 24
Peak memory 252512 kb
Host smart-78a3ba91-3b77-45e1-b2e2-582fda680482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=868459708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.868459708
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1279045787
Short name T784
Test name
Test status
Simulation time 37170936 ps
CPU time 6.18 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:18 AM PDT 24
Peak memory 253944 kb
Host smart-e1b4b1d2-f57b-4947-832a-e55ce76674cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279045787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1279045787
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2686169005
Short name T758
Test name
Test status
Simulation time 37678598 ps
CPU time 3.62 seconds
Started Jul 02 08:08:08 AM PDT 24
Finished Jul 02 08:08:16 AM PDT 24
Peak memory 237600 kb
Host smart-87a3166e-5643-45b4-bf2d-696e46d6256f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2686169005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2686169005
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2652953393
Short name T754
Test name
Test status
Simulation time 12226062 ps
CPU time 1.65 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:13 AM PDT 24
Peak memory 236756 kb
Host smart-f9f0941a-2e37-4ef0-9d04-57dd406acafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2652953393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2652953393
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2652500975
Short name T813
Test name
Test status
Simulation time 161536269 ps
CPU time 11.34 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:08:25 AM PDT 24
Peak memory 244844 kb
Host smart-adb5155c-9910-4d63-839d-c857f5ee3598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2652500975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2652500975
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3114022336
Short name T147
Test name
Test status
Simulation time 1661718247 ps
CPU time 183.36 seconds
Started Jul 02 08:08:05 AM PDT 24
Finished Jul 02 08:11:13 AM PDT 24
Peak memory 265388 kb
Host smart-0919e65a-6c02-490c-bb9e-81fad7cd451a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3114022336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3114022336
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1868216593
Short name T129
Test name
Test status
Simulation time 12146882481 ps
CPU time 306.58 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 265420 kb
Host smart-63c00432-6686-4c90-9494-2a08981ee421
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868216593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1868216593
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.4255927621
Short name T795
Test name
Test status
Simulation time 310683348 ps
CPU time 11.2 seconds
Started Jul 02 08:08:05 AM PDT 24
Finished Jul 02 08:08:21 AM PDT 24
Peak memory 255276 kb
Host smart-ecaf2ea7-714a-49bf-bb3e-ba8430056101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4255927621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.4255927621
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1315557627
Short name T791
Test name
Test status
Simulation time 44512535 ps
CPU time 6.99 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 252984 kb
Host smart-767206a3-ebf5-4dec-9aa6-a1ecfde595cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315557627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1315557627
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1137209114
Short name T767
Test name
Test status
Simulation time 289724956 ps
CPU time 10.11 seconds
Started Jul 02 08:08:07 AM PDT 24
Finished Jul 02 08:08:22 AM PDT 24
Peak memory 240528 kb
Host smart-a5ae4f51-9ae9-4f6e-a337-adcd1e6693cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1137209114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1137209114
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3379967936
Short name T324
Test name
Test status
Simulation time 17766402 ps
CPU time 1.27 seconds
Started Jul 02 08:08:11 AM PDT 24
Finished Jul 02 08:08:18 AM PDT 24
Peak memory 237612 kb
Host smart-bd661a66-837c-4286-99e5-b8b0bd8d8586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3379967936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3379967936
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2003082818
Short name T713
Test name
Test status
Simulation time 1052209502 ps
CPU time 39.86 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:08:54 AM PDT 24
Peak memory 245796 kb
Host smart-c71592db-170d-434b-86d3-55b2155950e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2003082818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2003082818
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1375104259
Short name T821
Test name
Test status
Simulation time 2446669941 ps
CPU time 325.88 seconds
Started Jul 02 08:08:10 AM PDT 24
Finished Jul 02 08:13:41 AM PDT 24
Peak memory 265396 kb
Host smart-00c61b8b-8f17-41c7-a4c7-fec92e87e45d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375104259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1375104259
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2472881777
Short name T749
Test name
Test status
Simulation time 1754179321 ps
CPU time 32.49 seconds
Started Jul 02 08:08:10 AM PDT 24
Finished Jul 02 08:08:48 AM PDT 24
Peak memory 255428 kb
Host smart-e3594f09-9fd8-40b3-86ac-1117d44181be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2472881777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2472881777
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2389920385
Short name T723
Test name
Test status
Simulation time 57015224 ps
CPU time 4.99 seconds
Started Jul 02 08:08:15 AM PDT 24
Finished Jul 02 08:08:25 AM PDT 24
Peak memory 240336 kb
Host smart-7246f3ae-ea57-44eb-9c7b-b8ed1b9e7128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389920385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2389920385
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2607459059
Short name T718
Test name
Test status
Simulation time 20679538 ps
CPU time 3.79 seconds
Started Jul 02 08:08:10 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 237732 kb
Host smart-19953bb1-2bd5-4617-8f9a-4e70af996788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2607459059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2607459059
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2923074079
Short name T798
Test name
Test status
Simulation time 3841291917 ps
CPU time 34.96 seconds
Started Jul 02 08:08:11 AM PDT 24
Finished Jul 02 08:08:52 AM PDT 24
Peak memory 244896 kb
Host smart-02d13f64-ea67-4f06-a0ec-1f6a594aed5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2923074079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2923074079
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3231170977
Short name T184
Test name
Test status
Simulation time 8854765608 ps
CPU time 290.19 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:13:05 AM PDT 24
Peak memory 272972 kb
Host smart-a631c6fb-b2a1-4c6f-8900-dba0a8b418f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3231170977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3231170977
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1233268257
Short name T123
Test name
Test status
Simulation time 9297349754 ps
CPU time 324.16 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:13:38 AM PDT 24
Peak memory 265420 kb
Host smart-61968ba7-d287-47d3-9dcd-fec9ea0ff119
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233268257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1233268257
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3930934426
Short name T705
Test name
Test status
Simulation time 231006449 ps
CPU time 16.96 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:08:32 AM PDT 24
Peak memory 249944 kb
Host smart-a9321f63-fd2f-4d86-b587-31be64d1d904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3930934426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3930934426
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1204721893
Short name T797
Test name
Test status
Simulation time 79690502 ps
CPU time 6.1 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:08:27 AM PDT 24
Peak memory 240516 kb
Host smart-221f365a-79bc-413d-86a7-48d734029c44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204721893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1204721893
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4204574103
Short name T170
Test name
Test status
Simulation time 68540219 ps
CPU time 5.59 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:08:27 AM PDT 24
Peak memory 240500 kb
Host smart-6732a2fe-6369-4aba-8b3b-9d14ad4e946a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4204574103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4204574103
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.729343136
Short name T720
Test name
Test status
Simulation time 7705336 ps
CPU time 1.51 seconds
Started Jul 02 08:08:14 AM PDT 24
Finished Jul 02 08:08:21 AM PDT 24
Peak memory 235476 kb
Host smart-e04d6ba3-9b3c-4041-938a-23d85cf8cdb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=729343136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.729343136
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4028762830
Short name T177
Test name
Test status
Simulation time 2566970512 ps
CPU time 47.03 seconds
Started Jul 02 08:08:14 AM PDT 24
Finished Jul 02 08:09:07 AM PDT 24
Peak memory 248676 kb
Host smart-a6db8646-71b2-4d58-9ca4-30a085464cc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4028762830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4028762830
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4054002240
Short name T126
Test name
Test status
Simulation time 863695487 ps
CPU time 87.95 seconds
Started Jul 02 08:08:13 AM PDT 24
Finished Jul 02 08:09:46 AM PDT 24
Peak memory 257196 kb
Host smart-73f8affc-58b3-4612-be17-53e6a0047243
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4054002240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4054002240
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2915333567
Short name T331
Test name
Test status
Simulation time 17739811099 ps
CPU time 675.14 seconds
Started Jul 02 08:08:14 AM PDT 24
Finished Jul 02 08:19:34 AM PDT 24
Peak memory 265416 kb
Host smart-1d0365ba-d33b-4082-bfee-4a02c7f910c2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915333567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2915333567
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3078527461
Short name T709
Test name
Test status
Simulation time 110902754 ps
CPU time 9.16 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:27 AM PDT 24
Peak memory 248852 kb
Host smart-8d1b0676-472f-4d35-beb8-fa3688c907de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3078527461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3078527461
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1395586980
Short name T719
Test name
Test status
Simulation time 4044124080 ps
CPU time 275.58 seconds
Started Jul 02 08:07:53 AM PDT 24
Finished Jul 02 08:12:35 AM PDT 24
Peak memory 241836 kb
Host smart-c4b4a055-37af-48cd-8503-e8cbcea53b47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1395586980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1395586980
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3460836189
Short name T330
Test name
Test status
Simulation time 10186122733 ps
CPU time 455.54 seconds
Started Jul 02 08:07:53 AM PDT 24
Finished Jul 02 08:15:35 AM PDT 24
Peak memory 237668 kb
Host smart-e795e374-54f5-4f21-a9b9-3003dbad55cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3460836189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3460836189
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1429184694
Short name T726
Test name
Test status
Simulation time 54547006 ps
CPU time 5.39 seconds
Started Jul 02 08:07:50 AM PDT 24
Finished Jul 02 08:08:03 AM PDT 24
Peak memory 248700 kb
Host smart-60e18cb1-85c6-4132-b6d1-c757e9b39e17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1429184694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1429184694
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3193465661
Short name T750
Test name
Test status
Simulation time 241554076 ps
CPU time 6.62 seconds
Started Jul 02 08:07:50 AM PDT 24
Finished Jul 02 08:08:04 AM PDT 24
Peak memory 256808 kb
Host smart-67295b49-2023-46eb-91d9-a3d898ad1a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193465661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3193465661
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3919236066
Short name T714
Test name
Test status
Simulation time 27701911 ps
CPU time 3.89 seconds
Started Jul 02 08:07:54 AM PDT 24
Finished Jul 02 08:08:04 AM PDT 24
Peak memory 237604 kb
Host smart-2b941e03-92c8-4386-b0c7-60c7afa35bc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3919236066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3919236066
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2455616684
Short name T753
Test name
Test status
Simulation time 26705080 ps
CPU time 1.52 seconds
Started Jul 02 08:07:53 AM PDT 24
Finished Jul 02 08:08:01 AM PDT 24
Peak memory 236652 kb
Host smart-3d351364-b123-458b-9738-4b0559cbe976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2455616684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2455616684
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3746285734
Short name T742
Test name
Test status
Simulation time 248578015 ps
CPU time 21.37 seconds
Started Jul 02 08:07:53 AM PDT 24
Finished Jul 02 08:08:21 AM PDT 24
Peak memory 245708 kb
Host smart-ca4f2272-eb28-40ce-81cf-0a528f0eabb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3746285734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3746285734
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.537148350
Short name T143
Test name
Test status
Simulation time 2252749205 ps
CPU time 221.64 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:11:36 AM PDT 24
Peak memory 265516 kb
Host smart-cf00e690-0055-477f-8389-64712ed586ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=537148350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.537148350
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.660305552
Short name T136
Test name
Test status
Simulation time 16324638641 ps
CPU time 1102.9 seconds
Started Jul 02 08:07:44 AM PDT 24
Finished Jul 02 08:26:15 AM PDT 24
Peak memory 273328 kb
Host smart-e43a9522-fe43-49d5-b260-ede9cb5e320e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660305552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.660305552
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1192643538
Short name T706
Test name
Test status
Simulation time 113477375 ps
CPU time 4.91 seconds
Started Jul 02 08:07:46 AM PDT 24
Finished Jul 02 08:07:59 AM PDT 24
Peak memory 248736 kb
Host smart-e732319b-99ef-41ae-b684-3ca36c295815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1192643538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1192643538
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3556453073
Short name T782
Test name
Test status
Simulation time 11337584 ps
CPU time 1.41 seconds
Started Jul 02 08:08:13 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 237616 kb
Host smart-a344d626-0a87-4e3c-a1b0-d96b439b6b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3556453073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3556453073
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3668144294
Short name T728
Test name
Test status
Simulation time 23520351 ps
CPU time 2.24 seconds
Started Jul 02 08:08:09 AM PDT 24
Finished Jul 02 08:08:16 AM PDT 24
Peak memory 236620 kb
Host smart-ad08919a-0be7-43fd-b2a9-300b5360f468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3668144294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3668144294
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2810571509
Short name T322
Test name
Test status
Simulation time 7511520 ps
CPU time 1.58 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 237596 kb
Host smart-2abb739d-2381-427b-a717-fc5a0b331558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2810571509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2810571509
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2551056663
Short name T737
Test name
Test status
Simulation time 7855403 ps
CPU time 1.46 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 236672 kb
Host smart-2e6d24dd-dd55-412d-9c69-ca42a0a91d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2551056663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2551056663
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.16307587
Short name T327
Test name
Test status
Simulation time 8564752 ps
CPU time 1.45 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 236668 kb
Host smart-35402af2-f3bf-4161-a603-1679960e811c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=16307587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.16307587
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1786458910
Short name T762
Test name
Test status
Simulation time 8389428 ps
CPU time 1.44 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 236612 kb
Host smart-ca40d741-9613-43c9-9e03-44461ce4bdae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1786458910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1786458910
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2161494318
Short name T729
Test name
Test status
Simulation time 6378030 ps
CPU time 1.41 seconds
Started Jul 02 08:08:10 AM PDT 24
Finished Jul 02 08:08:17 AM PDT 24
Peak memory 237624 kb
Host smart-2e47ec40-42b4-4c05-9805-94f5627a1747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161494318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2161494318
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4133033280
Short name T787
Test name
Test status
Simulation time 7918843 ps
CPU time 1.39 seconds
Started Jul 02 08:08:13 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 236556 kb
Host smart-ff7da71c-29e3-463f-9023-3ed4f651a4ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4133033280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4133033280
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2051606579
Short name T748
Test name
Test status
Simulation time 13200149 ps
CPU time 1.35 seconds
Started Jul 02 08:08:13 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 237608 kb
Host smart-18bfa841-3ea5-478d-bf03-58fde1786691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2051606579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2051606579
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2956828574
Short name T735
Test name
Test status
Simulation time 10027639 ps
CPU time 1.72 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 237616 kb
Host smart-c4d1c3ea-f3aa-49d0-a984-1d5eef0fea1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2956828574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2956828574
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2945429784
Short name T809
Test name
Test status
Simulation time 608846556 ps
CPU time 79.75 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:09:17 AM PDT 24
Peak memory 240532 kb
Host smart-eb849474-e986-4b46-9fd7-86f6dde770a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2945429784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2945429784
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2133229707
Short name T769
Test name
Test status
Simulation time 873617733 ps
CPU time 103.57 seconds
Started Jul 02 08:07:53 AM PDT 24
Finished Jul 02 08:09:43 AM PDT 24
Peak memory 240508 kb
Host smart-6ef76a7d-c691-420f-aeee-ef3ce4095c86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2133229707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2133229707
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3912402172
Short name T743
Test name
Test status
Simulation time 261056627 ps
CPU time 10.26 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:08:09 AM PDT 24
Peak memory 240524 kb
Host smart-d4b9e876-3e02-4a23-b800-40260922bf8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3912402172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3912402172
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4195907248
Short name T334
Test name
Test status
Simulation time 73878266 ps
CPU time 6.2 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:08:05 AM PDT 24
Peak memory 240056 kb
Host smart-ea518d0a-8f1f-45ce-bcfe-ddbc3f79a921
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195907248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4195907248
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3961781042
Short name T335
Test name
Test status
Simulation time 113314932 ps
CPU time 5.42 seconds
Started Jul 02 08:07:54 AM PDT 24
Finished Jul 02 08:08:05 AM PDT 24
Peak memory 236652 kb
Host smart-01d5b29f-a6d4-4355-a262-7da3037ad182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3961781042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3961781042
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2609249947
Short name T810
Test name
Test status
Simulation time 11574111 ps
CPU time 1.4 seconds
Started Jul 02 08:07:50 AM PDT 24
Finished Jul 02 08:07:59 AM PDT 24
Peak memory 235616 kb
Host smart-84cc2c44-bb10-4926-8253-919df3b46b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2609249947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2609249947
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.984773415
Short name T182
Test name
Test status
Simulation time 178178787 ps
CPU time 11.62 seconds
Started Jul 02 08:07:52 AM PDT 24
Finished Jul 02 08:08:11 AM PDT 24
Peak memory 244844 kb
Host smart-e4e62593-7b0a-41e3-97f7-93ba139f1147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=984773415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.984773415
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3127650740
Short name T145
Test name
Test status
Simulation time 4897215932 ps
CPU time 169.85 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 265448 kb
Host smart-71487a5a-f974-443f-807e-73f3f12beb30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3127650740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3127650740
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2057038446
Short name T786
Test name
Test status
Simulation time 211399139 ps
CPU time 9.57 seconds
Started Jul 02 08:07:52 AM PDT 24
Finished Jul 02 08:08:08 AM PDT 24
Peak memory 254816 kb
Host smart-82b0b0e3-14e2-45a3-92e1-6b5065254d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2057038446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2057038446
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3049975337
Short name T731
Test name
Test status
Simulation time 8721929 ps
CPU time 1.42 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 236772 kb
Host smart-8f1891ee-be48-4f2f-bfa8-649ce6c0acee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3049975337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3049975337
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.794534236
Short name T233
Test name
Test status
Simulation time 11537948 ps
CPU time 1.41 seconds
Started Jul 02 08:08:14 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 237568 kb
Host smart-f03891e0-4d8c-46be-8b43-20d1bd865cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=794534236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.794534236
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2152564428
Short name T776
Test name
Test status
Simulation time 14728176 ps
CPU time 1.53 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 236636 kb
Host smart-8e59eb25-65fd-40dd-81a9-b2f160bb0c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2152564428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2152564428
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2377780032
Short name T778
Test name
Test status
Simulation time 7821486 ps
CPU time 1.52 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 237584 kb
Host smart-a7bd1398-ad2b-4fd5-88f3-a1275b431208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2377780032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2377780032
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1499903549
Short name T325
Test name
Test status
Simulation time 7648665 ps
CPU time 1.43 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 237608 kb
Host smart-8048f770-1f50-4bc4-bac7-d081eac7fe7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1499903549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1499903549
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1193776873
Short name T711
Test name
Test status
Simulation time 9001369 ps
CPU time 1.52 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 236668 kb
Host smart-9d2eadfe-509c-4c2b-a8c2-6ff9d4301188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1193776873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1193776873
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1415093187
Short name T820
Test name
Test status
Simulation time 8616528 ps
CPU time 1.52 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:18 AM PDT 24
Peak memory 236628 kb
Host smart-3959ac71-c5e3-4f58-aa59-d9f6a3db7792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1415093187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1415093187
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.928831136
Short name T232
Test name
Test status
Simulation time 11374419 ps
CPU time 1.44 seconds
Started Jul 02 08:08:11 AM PDT 24
Finished Jul 02 08:08:18 AM PDT 24
Peak memory 237588 kb
Host smart-8ef0ffc6-53d5-4c90-a288-70a01c476f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=928831136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.928831136
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3686333659
Short name T792
Test name
Test status
Simulation time 14743990 ps
CPU time 1.42 seconds
Started Jul 02 08:08:12 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 236636 kb
Host smart-3145b7e2-50e0-4335-9803-0ddc5bfdbcb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3686333659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3686333659
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3542320328
Short name T717
Test name
Test status
Simulation time 7200262 ps
CPU time 1.48 seconds
Started Jul 02 08:08:13 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 236668 kb
Host smart-cc7f3cb2-be84-4978-b1c1-e23f73d363da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3542320328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3542320328
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.9230874
Short name T178
Test name
Test status
Simulation time 1875962304 ps
CPU time 117.02 seconds
Started Jul 02 08:07:50 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 237624 kb
Host smart-79b367fa-230d-485c-96b5-165836c74ef8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=9230874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.9230874
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3499764276
Short name T722
Test name
Test status
Simulation time 6533247272 ps
CPU time 221.77 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:11:40 AM PDT 24
Peak memory 237648 kb
Host smart-7d7687dc-855f-4e26-854e-f39963102e21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3499764276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3499764276
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1471344392
Short name T153
Test name
Test status
Simulation time 41445553 ps
CPU time 3.96 seconds
Started Jul 02 08:07:52 AM PDT 24
Finished Jul 02 08:08:03 AM PDT 24
Peak memory 248700 kb
Host smart-ad5e8815-ead3-4d5a-9f5e-8b0d8eb05cb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1471344392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1471344392
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3589947061
Short name T740
Test name
Test status
Simulation time 225313400 ps
CPU time 8.6 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:08:10 AM PDT 24
Peak memory 252676 kb
Host smart-e7aebba5-6deb-4dfc-9eb8-41c936ffea8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589947061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3589947061
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4268911125
Short name T793
Test name
Test status
Simulation time 127485524 ps
CPU time 8.46 seconds
Started Jul 02 08:07:51 AM PDT 24
Finished Jul 02 08:08:07 AM PDT 24
Peak memory 237556 kb
Host smart-d3f6b904-a03e-49d5-b1f1-ecd3d1485cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4268911125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4268911125
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4181977034
Short name T154
Test name
Test status
Simulation time 8901565 ps
CPU time 1.28 seconds
Started Jul 02 08:07:53 AM PDT 24
Finished Jul 02 08:08:01 AM PDT 24
Peak memory 237528 kb
Host smart-9021f37c-b938-4263-aeaf-a9b5157ab547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4181977034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4181977034
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3997261826
Short name T756
Test name
Test status
Simulation time 164379166 ps
CPU time 23.45 seconds
Started Jul 02 08:07:49 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 248680 kb
Host smart-60d23693-44d8-4a33-8a11-028f92998ac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3997261826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3997261826
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.364925684
Short name T130
Test name
Test status
Simulation time 7575327934 ps
CPU time 152.38 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:10:33 AM PDT 24
Peak memory 257400 kb
Host smart-169a5745-10d3-4cc1-bf79-b8b4f46384fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=364925684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.364925684
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.282092176
Short name T774
Test name
Test status
Simulation time 579831299 ps
CPU time 12.44 seconds
Started Jul 02 08:07:50 AM PDT 24
Finished Jul 02 08:08:10 AM PDT 24
Peak memory 255248 kb
Host smart-2042076e-4b95-45f1-8867-c34216f54739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282092176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.282092176
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.190669829
Short name T800
Test name
Test status
Simulation time 10444780 ps
CPU time 1.3 seconds
Started Jul 02 08:08:11 AM PDT 24
Finished Jul 02 08:08:17 AM PDT 24
Peak memory 235620 kb
Host smart-4a6c7c64-2d55-4719-9e56-c12a564d68ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=190669829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.190669829
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3669760130
Short name T155
Test name
Test status
Simulation time 10571306 ps
CPU time 1.34 seconds
Started Jul 02 08:08:17 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 236580 kb
Host smart-7a8a75db-4a5b-406d-aa74-39d1f319a933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3669760130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3669760130
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4023152030
Short name T716
Test name
Test status
Simulation time 10434799 ps
CPU time 1.53 seconds
Started Jul 02 08:08:17 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 237588 kb
Host smart-46c31b06-9ca7-4d94-884c-70deb8454722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4023152030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4023152030
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2427039545
Short name T738
Test name
Test status
Simulation time 19606118 ps
CPU time 1.41 seconds
Started Jul 02 08:08:19 AM PDT 24
Finished Jul 02 08:08:26 AM PDT 24
Peak memory 237628 kb
Host smart-563b2bc4-a7b3-4268-9045-90bdec5e6003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2427039545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2427039545
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4209230978
Short name T765
Test name
Test status
Simulation time 16522887 ps
CPU time 1.34 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 237616 kb
Host smart-979d08a5-bbde-4fc0-b14c-7c099be8fcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4209230978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.4209230978
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.325589494
Short name T746
Test name
Test status
Simulation time 9836339 ps
CPU time 1.61 seconds
Started Jul 02 08:08:18 AM PDT 24
Finished Jul 02 08:08:27 AM PDT 24
Peak memory 236580 kb
Host smart-d8465c7c-fb35-4361-b942-c02a57ff9af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=325589494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.325589494
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3219084565
Short name T732
Test name
Test status
Simulation time 11170325 ps
CPU time 1.33 seconds
Started Jul 02 08:08:18 AM PDT 24
Finished Jul 02 08:08:25 AM PDT 24
Peak memory 236644 kb
Host smart-d8fb0539-76ca-4ff8-9f2b-a6a7fc5c0ae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219084565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3219084565
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3229644878
Short name T747
Test name
Test status
Simulation time 17155378 ps
CPU time 1.36 seconds
Started Jul 02 08:08:16 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 236664 kb
Host smart-31f2ccec-c58b-46a0-9bae-773702d90aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3229644878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3229644878
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.707255068
Short name T773
Test name
Test status
Simulation time 10700012 ps
CPU time 1.64 seconds
Started Jul 02 08:08:21 AM PDT 24
Finished Jul 02 08:08:29 AM PDT 24
Peak memory 235564 kb
Host smart-9e3d9ca2-c544-430d-bdd9-2a01a715289d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=707255068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.707255068
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.811939445
Short name T768
Test name
Test status
Simulation time 38091718 ps
CPU time 6.36 seconds
Started Jul 02 08:07:55 AM PDT 24
Finished Jul 02 08:08:07 AM PDT 24
Peak memory 248808 kb
Host smart-b57aa277-32dd-49f1-a03f-37d1c1a9f8ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811939445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.811939445
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1155457596
Short name T721
Test name
Test status
Simulation time 48876015 ps
CPU time 5.45 seconds
Started Jul 02 08:07:54 AM PDT 24
Finished Jul 02 08:08:06 AM PDT 24
Peak memory 237516 kb
Host smart-eff6d882-96be-4ed4-b9df-e8341539a7f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1155457596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1155457596
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2776507894
Short name T761
Test name
Test status
Simulation time 7470373 ps
CPU time 1.52 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:03 AM PDT 24
Peak memory 235728 kb
Host smart-54e1b47e-8548-414b-b83e-2e5d7ac7d9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2776507894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2776507894
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1127523738
Short name T802
Test name
Test status
Simulation time 2036308411 ps
CPU time 38.86 seconds
Started Jul 02 08:07:58 AM PDT 24
Finished Jul 02 08:08:42 AM PDT 24
Peak memory 248648 kb
Host smart-cc5281ce-1058-42a3-aa79-bac85e6b2165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1127523738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1127523738
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.969029059
Short name T332
Test name
Test status
Simulation time 8527714285 ps
CPU time 334.57 seconds
Started Jul 02 08:07:55 AM PDT 24
Finished Jul 02 08:13:35 AM PDT 24
Peak memory 268724 kb
Host smart-c623e724-d8f0-4498-86d0-3efc008e9753
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969029059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.969029059
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.555101070
Short name T708
Test name
Test status
Simulation time 554059585 ps
CPU time 18.34 seconds
Started Jul 02 08:08:01 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 248704 kb
Host smart-024c28af-a22c-49d4-8a40-8f0dcdea452a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=555101070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.555101070
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3786393593
Short name T236
Test name
Test status
Simulation time 1379893427 ps
CPU time 11.11 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:08:13 AM PDT 24
Peak memory 239664 kb
Host smart-528da45d-f601-4e49-aa26-5383cfa5a1fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786393593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3786393593
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2297503
Short name T736
Test name
Test status
Simulation time 99376239 ps
CPU time 4.83 seconds
Started Jul 02 08:07:55 AM PDT 24
Finished Jul 02 08:08:06 AM PDT 24
Peak memory 237592 kb
Host smart-73cd6e7a-b4ee-4792-94b1-eb264bad290d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2297503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2297503
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2371359090
Short name T328
Test name
Test status
Simulation time 30008301 ps
CPU time 1.5 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:04 AM PDT 24
Peak memory 236660 kb
Host smart-a73f72a0-2d08-408d-b9de-ecad5ec5d59a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2371359090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2371359090
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.39195660
Short name T805
Test name
Test status
Simulation time 93470216 ps
CPU time 12.45 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:08:14 AM PDT 24
Peak memory 248752 kb
Host smart-0c6d10f5-63a1-4bff-84b2-088b8e235549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=39195660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outst
anding.39195660
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1220206261
Short name T134
Test name
Test status
Simulation time 6719387251 ps
CPU time 141.33 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:10:29 AM PDT 24
Peak memory 257212 kb
Host smart-2cbcea1e-a184-4dba-b101-57a0a0826596
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1220206261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1220206261
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1154673151
Short name T333
Test name
Test status
Simulation time 11943053872 ps
CPU time 475.85 seconds
Started Jul 02 08:07:55 AM PDT 24
Finished Jul 02 08:15:56 AM PDT 24
Peak memory 265352 kb
Host smart-3cb6bc28-b791-4380-adb7-6eb28ddc7486
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154673151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1154673151
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2593061515
Short name T715
Test name
Test status
Simulation time 933625683 ps
CPU time 19.46 seconds
Started Jul 02 08:07:55 AM PDT 24
Finished Jul 02 08:08:20 AM PDT 24
Peak memory 249808 kb
Host smart-ea5290b2-387b-4b31-bac3-0d1263e86257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2593061515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2593061515
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1901291515
Short name T825
Test name
Test status
Simulation time 339735624 ps
CPU time 7.24 seconds
Started Jul 02 08:07:59 AM PDT 24
Finished Jul 02 08:08:10 AM PDT 24
Peak memory 239836 kb
Host smart-9d138b14-267c-4c72-bfa2-736e230c0cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901291515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1901291515
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1798293453
Short name T816
Test name
Test status
Simulation time 50903840 ps
CPU time 3.17 seconds
Started Jul 02 08:07:58 AM PDT 24
Finished Jul 02 08:08:06 AM PDT 24
Peak memory 237492 kb
Host smart-679d0ae9-7156-4374-abe5-da34d2b77735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1798293453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1798293453
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2083121623
Short name T763
Test name
Test status
Simulation time 19141155 ps
CPU time 1.25 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:04 AM PDT 24
Peak memory 237508 kb
Host smart-5402af13-7fe9-42dd-ac40-81e63fc386df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2083121623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2083121623
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3911942251
Short name T180
Test name
Test status
Simulation time 2709509523 ps
CPU time 18.51 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:21 AM PDT 24
Peak memory 245748 kb
Host smart-1f35337f-5b85-40d5-9b21-a8970c97a2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3911942251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3911942251
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3840388721
Short name T149
Test name
Test status
Simulation time 4712865217 ps
CPU time 173.01 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:10:54 AM PDT 24
Peak memory 265480 kb
Host smart-8095ff56-84c3-44c2-afd0-f679e0febbbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3840388721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3840388721
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.930503698
Short name T139
Test name
Test status
Simulation time 20342385170 ps
CPU time 422.15 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:15:03 AM PDT 24
Peak memory 265396 kb
Host smart-4ca7cac7-1ebf-4abc-bab6-cbb110c212c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930503698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.930503698
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2019099910
Short name T819
Test name
Test status
Simulation time 865166102 ps
CPU time 13.97 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:16 AM PDT 24
Peak memory 248824 kb
Host smart-47c738ce-b754-4701-a0f8-42c467821677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2019099910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2019099910
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3395213711
Short name T772
Test name
Test status
Simulation time 40236329 ps
CPU time 5.4 seconds
Started Jul 02 08:07:59 AM PDT 24
Finished Jul 02 08:08:09 AM PDT 24
Peak memory 242328 kb
Host smart-d87b0db9-0949-4d31-8ce0-d2ab378cdf9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395213711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3395213711
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1160708149
Short name T752
Test name
Test status
Simulation time 63518892 ps
CPU time 6.51 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:08:15 AM PDT 24
Peak memory 240428 kb
Host smart-651d0078-7bb1-4834-8ee5-783941c66ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1160708149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1160708149
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.822731047
Short name T803
Test name
Test status
Simulation time 6248509 ps
CPU time 1.48 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:04 AM PDT 24
Peak memory 237624 kb
Host smart-9a20b0f0-a5e2-4536-8e65-88ecce1df0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=822731047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.822731047
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3077923579
Short name T179
Test name
Test status
Simulation time 1516518510 ps
CPU time 22.13 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:24 AM PDT 24
Peak memory 248652 kb
Host smart-ce4b89dc-3874-403a-a2bd-6fd8e97477f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3077923579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3077923579
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2329671006
Short name T122
Test name
Test status
Simulation time 25366646999 ps
CPU time 498.1 seconds
Started Jul 02 08:07:55 AM PDT 24
Finished Jul 02 08:16:19 AM PDT 24
Peak memory 269532 kb
Host smart-9fa3c202-00cb-4e51-a023-985531ecaf77
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329671006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2329671006
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.328622101
Short name T739
Test name
Test status
Simulation time 100176270 ps
CPU time 14.78 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:08:23 AM PDT 24
Peak memory 254544 kb
Host smart-f30c77ff-d405-449f-a290-46ab9b882e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=328622101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.328622101
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3234696369
Short name T724
Test name
Test status
Simulation time 113332774 ps
CPU time 8.45 seconds
Started Jul 02 08:08:02 AM PDT 24
Finished Jul 02 08:08:15 AM PDT 24
Peak memory 256900 kb
Host smart-a773e922-8fa7-4728-b0f0-abdf4cd080e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234696369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3234696369
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.949542953
Short name T175
Test name
Test status
Simulation time 64903426 ps
CPU time 3.39 seconds
Started Jul 02 08:07:57 AM PDT 24
Finished Jul 02 08:08:06 AM PDT 24
Peak memory 240572 kb
Host smart-48146bf0-bd59-4e90-945f-1f8c1e4ae90f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=949542953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.949542953
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2321407084
Short name T744
Test name
Test status
Simulation time 19138472 ps
CPU time 1.32 seconds
Started Jul 02 08:07:59 AM PDT 24
Finished Jul 02 08:08:05 AM PDT 24
Peak memory 235660 kb
Host smart-7d4c67d7-624b-4193-98dc-f756b2490e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321407084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2321407084
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.76447485
Short name T760
Test name
Test status
Simulation time 9665233955 ps
CPU time 51.91 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:09:00 AM PDT 24
Peak memory 245680 kb
Host smart-0ae88434-c1d8-4351-98b9-4b471c0ed0d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=76447485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outst
anding.76447485
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1993143268
Short name T119
Test name
Test status
Simulation time 18839533276 ps
CPU time 209.42 seconds
Started Jul 02 08:07:56 AM PDT 24
Finished Jul 02 08:11:31 AM PDT 24
Peak memory 271588 kb
Host smart-f8f997ad-b6a7-4203-a876-e4d8d256801a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1993143268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1993143268
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3012392372
Short name T780
Test name
Test status
Simulation time 132313085 ps
CPU time 10.9 seconds
Started Jul 02 08:08:04 AM PDT 24
Finished Jul 02 08:08:19 AM PDT 24
Peak memory 254276 kb
Host smart-5fed977e-7b41-4476-b7b0-e45b07fbdf11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3012392372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3012392372
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2012370106
Short name T648
Test name
Test status
Simulation time 36197902122 ps
CPU time 773.92 seconds
Started Jul 02 08:30:58 AM PDT 24
Finished Jul 02 08:43:52 AM PDT 24
Peak memory 273428 kb
Host smart-b2efed6a-2de5-4df6-86ee-7ef088cf7e58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012370106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2012370106
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1756416455
Short name T113
Test name
Test status
Simulation time 362056010 ps
CPU time 17.15 seconds
Started Jul 02 08:30:59 AM PDT 24
Finished Jul 02 08:31:17 AM PDT 24
Peak memory 249244 kb
Host smart-3650786a-0d6a-4c82-8384-5bed33f159b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1756416455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1756416455
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.739861863
Short name T423
Test name
Test status
Simulation time 2064467385 ps
CPU time 117.51 seconds
Started Jul 02 08:30:57 AM PDT 24
Finished Jul 02 08:32:55 AM PDT 24
Peak memory 256604 kb
Host smart-cc010b53-1fa3-41a7-aa94-459dbaabd8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73986
1863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.739861863
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3037819602
Short name T597
Test name
Test status
Simulation time 2574773263 ps
CPU time 39.42 seconds
Started Jul 02 08:30:56 AM PDT 24
Finished Jul 02 08:31:36 AM PDT 24
Peak memory 249264 kb
Host smart-d6b2a96f-19c3-410d-8fcf-44b54d1c9af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30378
19602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3037819602
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4115624361
Short name T583
Test name
Test status
Simulation time 32142649368 ps
CPU time 1649.35 seconds
Started Jul 02 08:30:56 AM PDT 24
Finished Jul 02 08:58:27 AM PDT 24
Peak memory 287896 kb
Host smart-6de3e4be-abbe-4e98-9bf9-52de89b381b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115624361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4115624361
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3133816268
Short name T295
Test name
Test status
Simulation time 9726281446 ps
CPU time 99.1 seconds
Started Jul 02 08:30:57 AM PDT 24
Finished Jul 02 08:32:37 AM PDT 24
Peak memory 248400 kb
Host smart-cf645e09-7c94-4ef2-af9c-21c9b84f6f06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133816268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3133816268
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1275328643
Short name T442
Test name
Test status
Simulation time 1521410873 ps
CPU time 50.4 seconds
Started Jul 02 08:30:59 AM PDT 24
Finished Jul 02 08:31:50 AM PDT 24
Peak memory 256652 kb
Host smart-55378de7-d98b-4f76-8ed2-9fa2c1db4099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12753
28643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1275328643
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.290367901
Short name T30
Test name
Test status
Simulation time 602110725 ps
CPU time 37.92 seconds
Started Jul 02 08:30:59 AM PDT 24
Finished Jul 02 08:31:38 AM PDT 24
Peak memory 257020 kb
Host smart-c56fbbf1-2248-401d-b2b5-aa144d79ef5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29036
7901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.290367901
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2139291500
Short name T11
Test name
Test status
Simulation time 1297692292 ps
CPU time 21.05 seconds
Started Jul 02 08:31:01 AM PDT 24
Finished Jul 02 08:31:23 AM PDT 24
Peak memory 271300 kb
Host smart-7c28ccef-82fe-457b-94c3-36a8df412678
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2139291500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2139291500
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1916965169
Short name T693
Test name
Test status
Simulation time 161341831 ps
CPU time 19.87 seconds
Started Jul 02 08:30:58 AM PDT 24
Finished Jul 02 08:31:19 AM PDT 24
Peak memory 248800 kb
Host smart-6a38e0de-ffc9-49bf-a125-ae22caf70b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
65169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1916965169
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2661572113
Short name T455
Test name
Test status
Simulation time 56430540 ps
CPU time 7.59 seconds
Started Jul 02 08:30:58 AM PDT 24
Finished Jul 02 08:31:06 AM PDT 24
Peak memory 255348 kb
Host smart-4414049e-3af9-42bf-8a8f-be24992a0b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26615
72113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2661572113
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3768986868
Short name T620
Test name
Test status
Simulation time 100936848887 ps
CPU time 1508.47 seconds
Started Jul 02 08:31:01 AM PDT 24
Finished Jul 02 08:56:10 AM PDT 24
Peak memory 289832 kb
Host smart-002622b2-01d5-4b43-a2ca-0573ec1f0e51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768986868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3768986868
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1175242550
Short name T541
Test name
Test status
Simulation time 41114118697 ps
CPU time 2774.38 seconds
Started Jul 02 08:31:08 AM PDT 24
Finished Jul 02 09:17:23 AM PDT 24
Peak memory 289480 kb
Host smart-e5eb1ddf-3aad-4099-99cc-42a9362ec4a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175242550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1175242550
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.137271813
Short name T411
Test name
Test status
Simulation time 185759581 ps
CPU time 9.12 seconds
Started Jul 02 08:31:03 AM PDT 24
Finished Jul 02 08:31:12 AM PDT 24
Peak memory 249432 kb
Host smart-7278dd7c-7738-46cc-84c8-132db53b464c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=137271813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.137271813
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3502189940
Short name T396
Test name
Test status
Simulation time 20366823757 ps
CPU time 97.44 seconds
Started Jul 02 08:31:03 AM PDT 24
Finished Jul 02 08:32:41 AM PDT 24
Peak memory 257004 kb
Host smart-c8f059c0-7f1e-49e7-bec4-1c635de87c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35021
89940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3502189940
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.33482876
Short name T665
Test name
Test status
Simulation time 1148116317 ps
CPU time 63.3 seconds
Started Jul 02 08:31:03 AM PDT 24
Finished Jul 02 08:32:07 AM PDT 24
Peak memory 249248 kb
Host smart-d415ed86-74d5-4e21-b865-c4ce65f8b684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33482
876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.33482876
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1088072926
Short name T598
Test name
Test status
Simulation time 40461518766 ps
CPU time 2341.21 seconds
Started Jul 02 08:31:01 AM PDT 24
Finished Jul 02 09:10:03 AM PDT 24
Peak memory 273920 kb
Host smart-a2ecda7c-65e9-42a1-b4d3-496ff7195714
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088072926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1088072926
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1350528687
Short name T566
Test name
Test status
Simulation time 57395416007 ps
CPU time 1594.92 seconds
Started Jul 02 08:31:04 AM PDT 24
Finished Jul 02 08:57:40 AM PDT 24
Peak memory 290068 kb
Host smart-2a564d28-950b-4ca9-a9fd-71402d306730
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350528687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1350528687
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.194546405
Short name T540
Test name
Test status
Simulation time 7506123256 ps
CPU time 309.33 seconds
Started Jul 02 08:31:04 AM PDT 24
Finished Jul 02 08:36:14 AM PDT 24
Peak memory 249408 kb
Host smart-7c6ed5b1-2829-40a9-a743-35b78d972003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194546405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.194546405
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2908614446
Short name T211
Test name
Test status
Simulation time 1064382824 ps
CPU time 24.04 seconds
Started Jul 02 08:31:03 AM PDT 24
Finished Jul 02 08:31:28 AM PDT 24
Peak memory 256556 kb
Host smart-c6130cbc-ecab-4d9a-bff3-64b9ffd56836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
14446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2908614446
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1679593899
Short name T13
Test name
Test status
Simulation time 300210615 ps
CPU time 15.97 seconds
Started Jul 02 08:31:05 AM PDT 24
Finished Jul 02 08:31:22 AM PDT 24
Peak memory 270832 kb
Host smart-07b95b34-a97a-4a8d-8b81-1e2ccfcfb17c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1679593899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1679593899
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.719570250
Short name T47
Test name
Test status
Simulation time 211199219 ps
CPU time 23.69 seconds
Started Jul 02 08:31:08 AM PDT 24
Finished Jul 02 08:31:32 AM PDT 24
Peak memory 249224 kb
Host smart-039ef40c-9da0-47b6-af70-dc4f3f7dbdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71957
0250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.719570250
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2258572267
Short name T643
Test name
Test status
Simulation time 564371160 ps
CPU time 38.3 seconds
Started Jul 02 08:31:03 AM PDT 24
Finished Jul 02 08:31:42 AM PDT 24
Peak memory 257392 kb
Host smart-eb3644ff-f8cc-4abd-9196-4c8ab4bcf39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22585
72267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2258572267
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2628835277
Short name T190
Test name
Test status
Simulation time 24298720 ps
CPU time 2.61 seconds
Started Jul 02 08:31:51 AM PDT 24
Finished Jul 02 08:31:54 AM PDT 24
Peak memory 249704 kb
Host smart-6fffd49a-3469-4fc0-9241-cd2437ad8136
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2628835277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2628835277
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2476429652
Short name T426
Test name
Test status
Simulation time 2222535659 ps
CPU time 49.85 seconds
Started Jul 02 08:31:53 AM PDT 24
Finished Jul 02 08:32:44 AM PDT 24
Peak memory 249412 kb
Host smart-86dfa6d8-e0b7-4ce3-bed9-afe899d6bf2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2476429652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2476429652
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.853582313
Short name T237
Test name
Test status
Simulation time 2893690338 ps
CPU time 161.51 seconds
Started Jul 02 08:31:51 AM PDT 24
Finished Jul 02 08:34:34 AM PDT 24
Peak memory 257612 kb
Host smart-3159217c-7d0e-4bbf-8690-6bfd4660dbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85358
2313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.853582313
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2374482707
Short name T613
Test name
Test status
Simulation time 855777792 ps
CPU time 18.02 seconds
Started Jul 02 08:31:54 AM PDT 24
Finished Jul 02 08:32:13 AM PDT 24
Peak memory 249252 kb
Host smart-7a1c52ac-5d14-4d6a-a1b8-ad1f5e72051d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23744
82707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2374482707
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2052565520
Short name T275
Test name
Test status
Simulation time 273053254277 ps
CPU time 1976.1 seconds
Started Jul 02 08:31:52 AM PDT 24
Finished Jul 02 09:04:49 AM PDT 24
Peak memory 269920 kb
Host smart-0a7e9653-1d92-40c4-a300-1c29ae4b75c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052565520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2052565520
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1129239087
Short name T559
Test name
Test status
Simulation time 20397867443 ps
CPU time 135.32 seconds
Started Jul 02 08:31:51 AM PDT 24
Finished Jul 02 08:34:07 AM PDT 24
Peak memory 249352 kb
Host smart-1b97139d-5875-4dff-a33d-483611d01826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129239087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1129239087
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2262639593
Short name T475
Test name
Test status
Simulation time 281104989 ps
CPU time 8.31 seconds
Started Jul 02 08:31:48 AM PDT 24
Finished Jul 02 08:31:57 AM PDT 24
Peak memory 255208 kb
Host smart-aaf2bbe4-2547-4296-99c6-e884685e8a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22626
39593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2262639593
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4120366873
Short name T592
Test name
Test status
Simulation time 1987648307 ps
CPU time 29.94 seconds
Started Jul 02 08:31:49 AM PDT 24
Finished Jul 02 08:32:19 AM PDT 24
Peak memory 257184 kb
Host smart-24af50c7-ee3d-4f11-9b02-20db58aaa236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41203
66873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4120366873
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2129738471
Short name T73
Test name
Test status
Simulation time 4647657707 ps
CPU time 29.58 seconds
Started Jul 02 08:31:54 AM PDT 24
Finished Jul 02 08:32:25 AM PDT 24
Peak memory 248416 kb
Host smart-7d1b58f9-f1f4-4bc7-85e5-c6ddab08b906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21297
38471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2129738471
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3542830895
Short name T337
Test name
Test status
Simulation time 4053397064 ps
CPU time 56.55 seconds
Started Jul 02 08:31:49 AM PDT 24
Finished Jul 02 08:32:46 AM PDT 24
Peak memory 256596 kb
Host smart-b02e44d4-3996-43b9-a140-0e65b008da06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
30895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3542830895
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1355748769
Short name T238
Test name
Test status
Simulation time 95350512321 ps
CPU time 2035.23 seconds
Started Jul 02 08:31:52 AM PDT 24
Finished Jul 02 09:05:48 AM PDT 24
Peak memory 302812 kb
Host smart-88730d22-ece3-4597-9b96-85ea62dee700
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355748769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1355748769
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1807569056
Short name T416
Test name
Test status
Simulation time 43318191115 ps
CPU time 2656.69 seconds
Started Jul 02 08:32:01 AM PDT 24
Finished Jul 02 09:16:18 AM PDT 24
Peak memory 285664 kb
Host smart-18e2a5e6-76da-4a13-a8e3-ac2b0b7b24d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807569056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1807569056
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3194067871
Short name T439
Test name
Test status
Simulation time 5568325164 ps
CPU time 56.95 seconds
Started Jul 02 08:32:01 AM PDT 24
Finished Jul 02 08:32:59 AM PDT 24
Peak memory 249400 kb
Host smart-f2394994-e0c5-49a1-a4cc-ff076368b68c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3194067871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3194067871
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3458065288
Short name T628
Test name
Test status
Simulation time 8380623959 ps
CPU time 264.34 seconds
Started Jul 02 08:31:57 AM PDT 24
Finished Jul 02 08:36:22 AM PDT 24
Peak memory 257108 kb
Host smart-610d13db-2950-43cf-9244-6a95c6a5ca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34580
65288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3458065288
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3062510637
Short name T496
Test name
Test status
Simulation time 4471680992 ps
CPU time 48.97 seconds
Started Jul 02 08:32:00 AM PDT 24
Finished Jul 02 08:32:49 AM PDT 24
Peak memory 249816 kb
Host smart-01205da6-5e7e-4b8c-ad21-c0f8fa37ca8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30625
10637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3062510637
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.25353537
Short name T301
Test name
Test status
Simulation time 12726974807 ps
CPU time 1423.38 seconds
Started Jul 02 08:32:02 AM PDT 24
Finished Jul 02 08:55:46 AM PDT 24
Peak memory 282064 kb
Host smart-878d47bd-7a12-4e79-aaa6-6063df829128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25353537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.25353537
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2410834060
Short name T651
Test name
Test status
Simulation time 10867861790 ps
CPU time 744.51 seconds
Started Jul 02 08:32:02 AM PDT 24
Finished Jul 02 08:44:28 AM PDT 24
Peak memory 273588 kb
Host smart-ae78e220-87e3-42f5-b3ed-47c02b282c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410834060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2410834060
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1547505262
Short name T661
Test name
Test status
Simulation time 1557952768 ps
CPU time 54.61 seconds
Started Jul 02 08:31:59 AM PDT 24
Finished Jul 02 08:32:54 AM PDT 24
Peak memory 256560 kb
Host smart-5e3e10d0-87c6-4e04-bd8e-d3a33ec3931a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
05262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1547505262
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2403572798
Short name T589
Test name
Test status
Simulation time 470757034 ps
CPU time 44.49 seconds
Started Jul 02 08:31:57 AM PDT 24
Finished Jul 02 08:32:43 AM PDT 24
Peak memory 257432 kb
Host smart-04aacb25-ef52-401e-9d8b-234b999c8a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
72798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2403572798
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3722433305
Short name T253
Test name
Test status
Simulation time 4462316717 ps
CPU time 31.8 seconds
Started Jul 02 08:31:56 AM PDT 24
Finished Jul 02 08:32:29 AM PDT 24
Peak memory 255448 kb
Host smart-16f2b209-4a55-4f6c-9533-2cff267f1266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37224
33305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3722433305
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1171545541
Short name T374
Test name
Test status
Simulation time 855585232 ps
CPU time 49.8 seconds
Started Jul 02 08:31:58 AM PDT 24
Finished Jul 02 08:32:48 AM PDT 24
Peak memory 249672 kb
Host smart-60437616-bd5e-4773-8c26-842b0060cb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
45541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1171545541
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3547866919
Short name T489
Test name
Test status
Simulation time 20115133871 ps
CPU time 827.41 seconds
Started Jul 02 08:32:06 AM PDT 24
Finished Jul 02 08:45:55 AM PDT 24
Peak memory 267940 kb
Host smart-69fab5a1-6b45-4cd2-b5e3-54b779fc82ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547866919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3547866919
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.826254749
Short name T356
Test name
Test status
Simulation time 1017303375 ps
CPU time 22.49 seconds
Started Jul 02 08:32:05 AM PDT 24
Finished Jul 02 08:32:29 AM PDT 24
Peak memory 249292 kb
Host smart-04f94a8c-0c9b-4229-be27-73fd515dd399
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=826254749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.826254749
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2717429094
Short name T663
Test name
Test status
Simulation time 2184860256 ps
CPU time 139.08 seconds
Started Jul 02 08:32:06 AM PDT 24
Finished Jul 02 08:34:26 AM PDT 24
Peak memory 257096 kb
Host smart-e09057d3-cad5-407d-9ecc-79de9843f19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27174
29094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2717429094
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3619773265
Short name T418
Test name
Test status
Simulation time 57467914 ps
CPU time 7.47 seconds
Started Jul 02 08:32:05 AM PDT 24
Finished Jul 02 08:32:14 AM PDT 24
Peak memory 253904 kb
Host smart-3363bff8-a7c3-4891-8bc5-93a45efc6bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
73265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3619773265
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2003929580
Short name T318
Test name
Test status
Simulation time 22649272023 ps
CPU time 845.26 seconds
Started Jul 02 08:32:06 AM PDT 24
Finished Jul 02 08:46:13 AM PDT 24
Peak memory 274028 kb
Host smart-68ed45c9-58b8-46fa-b368-07676015a8d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003929580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2003929580
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1149856280
Short name T210
Test name
Test status
Simulation time 50874547005 ps
CPU time 3187.93 seconds
Started Jul 02 08:32:05 AM PDT 24
Finished Jul 02 09:25:15 AM PDT 24
Peak memory 290320 kb
Host smart-14634beb-508e-4d5d-8f93-f03c5d062027
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149856280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1149856280
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.4163235520
Short name T430
Test name
Test status
Simulation time 630960521 ps
CPU time 37.85 seconds
Started Jul 02 08:32:01 AM PDT 24
Finished Jul 02 08:32:40 AM PDT 24
Peak memory 257404 kb
Host smart-fd338eca-5dd6-444e-a5ee-732d95c5b8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41632
35520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.4163235520
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3526895845
Short name T69
Test name
Test status
Simulation time 488118918 ps
CPU time 8.36 seconds
Started Jul 02 08:32:02 AM PDT 24
Finished Jul 02 08:32:12 AM PDT 24
Peak memory 249328 kb
Host smart-73207077-276b-425a-8c8e-3426c80a51d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35268
95845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3526895845
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3159385054
Short name T32
Test name
Test status
Simulation time 1114116863 ps
CPU time 64.58 seconds
Started Jul 02 08:32:05 AM PDT 24
Finished Jul 02 08:33:10 AM PDT 24
Peak memory 257492 kb
Host smart-56e903c7-8a5a-4381-ab3a-1403d9344f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31593
85054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3159385054
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.4219209125
Short name T567
Test name
Test status
Simulation time 769599264 ps
CPU time 28.93 seconds
Started Jul 02 08:32:04 AM PDT 24
Finished Jul 02 08:32:34 AM PDT 24
Peak memory 256960 kb
Host smart-b9f9cdc1-03cd-4386-83ca-114f2ac79801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42192
09125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.4219209125
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4219562553
Short name T516
Test name
Test status
Simulation time 28634651535 ps
CPU time 1720.82 seconds
Started Jul 02 08:32:05 AM PDT 24
Finished Jul 02 09:00:46 AM PDT 24
Peak memory 290312 kb
Host smart-2c690bf0-a2ed-4b64-a4c0-720210dfddc2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219562553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4219562553
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4251947922
Short name T200
Test name
Test status
Simulation time 48818214 ps
CPU time 3.79 seconds
Started Jul 02 08:32:17 AM PDT 24
Finished Jul 02 08:32:22 AM PDT 24
Peak memory 249552 kb
Host smart-90ac678c-bd1e-442c-a477-48596d4b420a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4251947922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4251947922
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1041235730
Short name T107
Test name
Test status
Simulation time 87534768632 ps
CPU time 1569.38 seconds
Started Jul 02 08:32:11 AM PDT 24
Finished Jul 02 08:58:22 AM PDT 24
Peak memory 273512 kb
Host smart-584471f8-7307-4b42-a5b9-12d31bc56900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041235730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1041235730
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.309134503
Short name T662
Test name
Test status
Simulation time 4555008804 ps
CPU time 14.23 seconds
Started Jul 02 08:32:16 AM PDT 24
Finished Jul 02 08:32:31 AM PDT 24
Peak memory 249396 kb
Host smart-c66db161-5e1a-4070-b7a6-fb8f6280a909
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=309134503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.309134503
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2841010364
Short name T649
Test name
Test status
Simulation time 2566508305 ps
CPU time 39.17 seconds
Started Jul 02 08:32:10 AM PDT 24
Finished Jul 02 08:32:50 AM PDT 24
Peak memory 256896 kb
Host smart-eea39884-129e-4caf-9f58-dc8d5b09f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
10364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2841010364
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2610180359
Short name T600
Test name
Test status
Simulation time 2456565406 ps
CPU time 73.57 seconds
Started Jul 02 08:32:12 AM PDT 24
Finished Jul 02 08:33:27 AM PDT 24
Peak memory 249344 kb
Host smart-29c301f7-1d09-4961-9e74-55875352f3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26101
80359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2610180359
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3233231470
Short name T321
Test name
Test status
Simulation time 78948688815 ps
CPU time 2295.75 seconds
Started Jul 02 08:32:16 AM PDT 24
Finished Jul 02 09:10:33 AM PDT 24
Peak memory 273900 kb
Host smart-a6a160cd-49cb-4806-a562-6a852e9f76cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233231470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3233231470
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.813904220
Short name T357
Test name
Test status
Simulation time 169376225929 ps
CPU time 2263.75 seconds
Started Jul 02 08:32:16 AM PDT 24
Finished Jul 02 09:10:01 AM PDT 24
Peak memory 283468 kb
Host smart-e6f2caf9-d9e1-4643-a090-09421a9a7ba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813904220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.813904220
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.768688461
Short name T36
Test name
Test status
Simulation time 24615216561 ps
CPU time 258.83 seconds
Started Jul 02 08:32:14 AM PDT 24
Finished Jul 02 08:36:34 AM PDT 24
Peak memory 248220 kb
Host smart-b58d28a4-a885-4d33-b611-e5fc67727d11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768688461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.768688461
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.135603258
Short name T565
Test name
Test status
Simulation time 376303004 ps
CPU time 8.57 seconds
Started Jul 02 08:32:13 AM PDT 24
Finished Jul 02 08:32:23 AM PDT 24
Peak memory 249300 kb
Host smart-a9e67b73-d7e1-4a40-8ba1-970260761604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
3258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.135603258
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.481931800
Short name T701
Test name
Test status
Simulation time 2572656726 ps
CPU time 37.28 seconds
Started Jul 02 08:32:13 AM PDT 24
Finished Jul 02 08:32:52 AM PDT 24
Peak memory 256776 kb
Host smart-45fdca0d-ccc0-4624-b93a-97fb312accad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48193
1800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.481931800
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3075518766
Short name T1
Test name
Test status
Simulation time 995926155 ps
CPU time 18.17 seconds
Started Jul 02 08:32:13 AM PDT 24
Finished Jul 02 08:32:32 AM PDT 24
Peak memory 248804 kb
Host smart-71212cba-a71f-4ac8-85e1-0255d1f3b9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30755
18766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3075518766
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3040683339
Short name T421
Test name
Test status
Simulation time 3102933459 ps
CPU time 20.01 seconds
Started Jul 02 08:32:11 AM PDT 24
Finished Jul 02 08:32:32 AM PDT 24
Peak memory 257212 kb
Host smart-3350b444-6a82-4baa-bfb2-182f02c7b000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30406
83339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3040683339
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3948417276
Short name T25
Test name
Test status
Simulation time 22521271959 ps
CPU time 856.13 seconds
Started Jul 02 08:32:18 AM PDT 24
Finished Jul 02 08:46:35 AM PDT 24
Peak memory 273964 kb
Host smart-47037bd9-cbfe-437c-b5d6-7b42cc1cc12a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948417276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3948417276
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2407727860
Short name T188
Test name
Test status
Simulation time 69574127 ps
CPU time 3.66 seconds
Started Jul 02 08:32:23 AM PDT 24
Finished Jul 02 08:32:27 AM PDT 24
Peak memory 249520 kb
Host smart-6d96bf02-9e1a-4cfa-90ad-a24838b9de2f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2407727860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2407727860
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3048885206
Short name T459
Test name
Test status
Simulation time 108399486158 ps
CPU time 2047.85 seconds
Started Jul 02 08:32:17 AM PDT 24
Finished Jul 02 09:06:26 AM PDT 24
Peak memory 286236 kb
Host smart-e74e3de5-da19-4f23-86a2-0edf710e8364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048885206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3048885206
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3664540678
Short name T360
Test name
Test status
Simulation time 3520057356 ps
CPU time 45.56 seconds
Started Jul 02 08:32:20 AM PDT 24
Finished Jul 02 08:33:06 AM PDT 24
Peak memory 249372 kb
Host smart-3faf2633-2db3-401e-8f06-9a011b6ac8b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3664540678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3664540678
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.4212436208
Short name T208
Test name
Test status
Simulation time 17131331278 ps
CPU time 167.35 seconds
Started Jul 02 08:32:17 AM PDT 24
Finished Jul 02 08:35:05 AM PDT 24
Peak memory 257612 kb
Host smart-0a411aa9-629f-4270-9e1f-f8a753e57a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
36208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.4212436208
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.804383107
Short name T254
Test name
Test status
Simulation time 4592050061 ps
CPU time 65.73 seconds
Started Jul 02 08:32:16 AM PDT 24
Finished Jul 02 08:33:22 AM PDT 24
Peak memory 257156 kb
Host smart-ac09022e-d354-4b1a-9194-5d65d9743334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80438
3107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.804383107
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3950419967
Short name T272
Test name
Test status
Simulation time 34812216117 ps
CPU time 1761.71 seconds
Started Jul 02 08:32:16 AM PDT 24
Finished Jul 02 09:01:39 AM PDT 24
Peak memory 283984 kb
Host smart-89769d22-6c31-4b22-a5e0-f0c24ebb2144
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950419967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3950419967
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1815782219
Short name T646
Test name
Test status
Simulation time 14168802409 ps
CPU time 300.67 seconds
Started Jul 02 08:32:17 AM PDT 24
Finished Jul 02 08:37:19 AM PDT 24
Peak memory 256084 kb
Host smart-3d50e822-557a-4b35-a4fa-971dd4bddb77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815782219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1815782219
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.920864394
Short name T389
Test name
Test status
Simulation time 358493357 ps
CPU time 14.85 seconds
Started Jul 02 08:32:18 AM PDT 24
Finished Jul 02 08:32:34 AM PDT 24
Peak memory 249300 kb
Host smart-2a84a82f-cd5b-41a9-b937-d962cf482875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92086
4394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.920864394
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2079663967
Short name T520
Test name
Test status
Simulation time 2376778308 ps
CPU time 29.73 seconds
Started Jul 02 08:32:16 AM PDT 24
Finished Jul 02 08:32:47 AM PDT 24
Peak memory 249288 kb
Host smart-01efe2be-e3eb-4788-83f8-763f6df36b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20796
63967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2079663967
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2378283836
Short name T415
Test name
Test status
Simulation time 152053785 ps
CPU time 13.47 seconds
Started Jul 02 08:32:18 AM PDT 24
Finished Jul 02 08:32:32 AM PDT 24
Peak memory 256480 kb
Host smart-71b80952-7e64-4da2-87db-e6f5c6f54b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23782
83836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2378283836
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4052551151
Short name T506
Test name
Test status
Simulation time 53653182728 ps
CPU time 2805.13 seconds
Started Jul 02 08:32:21 AM PDT 24
Finished Jul 02 09:19:07 AM PDT 24
Peak memory 289792 kb
Host smart-cd5b0b3d-0ad8-4015-ba15-174f32d85c6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052551151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4052551151
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1509528420
Short name T194
Test name
Test status
Simulation time 35743281 ps
CPU time 3.56 seconds
Started Jul 02 08:32:31 AM PDT 24
Finished Jul 02 08:32:35 AM PDT 24
Peak memory 249552 kb
Host smart-5822843b-ffda-4b4a-b907-8e56ef91c0e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1509528420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1509528420
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.959782979
Short name T111
Test name
Test status
Simulation time 20074030624 ps
CPU time 1049.56 seconds
Started Jul 02 08:32:26 AM PDT 24
Finished Jul 02 08:49:56 AM PDT 24
Peak memory 290368 kb
Host smart-9010a074-5edb-4215-87e4-e76ac92ec6dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959782979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.959782979
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1424741015
Short name T375
Test name
Test status
Simulation time 1226947816 ps
CPU time 30.25 seconds
Started Jul 02 08:32:24 AM PDT 24
Finished Jul 02 08:32:55 AM PDT 24
Peak memory 249244 kb
Host smart-a8b4990a-f06d-49cd-9790-dec0dbb55505
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1424741015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1424741015
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3315286899
Short name T505
Test name
Test status
Simulation time 525017153 ps
CPU time 34.8 seconds
Started Jul 02 08:32:23 AM PDT 24
Finished Jul 02 08:32:58 AM PDT 24
Peak memory 256980 kb
Host smart-c4f3b65a-ba01-4758-a9d8-116647461740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33152
86899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3315286899
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1069032869
Short name T599
Test name
Test status
Simulation time 955244160 ps
CPU time 45.81 seconds
Started Jul 02 08:32:22 AM PDT 24
Finished Jul 02 08:33:09 AM PDT 24
Peak memory 249224 kb
Host smart-4d3239f1-182b-4052-8029-88dad0d24845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690
32869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1069032869
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2030453417
Short name T669
Test name
Test status
Simulation time 78094007410 ps
CPU time 1783.99 seconds
Started Jul 02 08:32:25 AM PDT 24
Finished Jul 02 09:02:10 AM PDT 24
Peak memory 290328 kb
Host smart-578950b5-43a0-4206-abe1-8c7d94b935c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030453417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2030453417
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.112494807
Short name T90
Test name
Test status
Simulation time 66894891716 ps
CPU time 1718.01 seconds
Started Jul 02 08:32:27 AM PDT 24
Finished Jul 02 09:01:06 AM PDT 24
Peak memory 273396 kb
Host smart-0dd7982b-bba8-4cf0-a560-2292f06cab8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112494807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.112494807
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3795566167
Short name T611
Test name
Test status
Simulation time 14776415966 ps
CPU time 180.99 seconds
Started Jul 02 08:32:26 AM PDT 24
Finished Jul 02 08:35:28 AM PDT 24
Peak memory 248204 kb
Host smart-ce39a053-dc96-48de-a7e8-87b82f875fd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795566167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3795566167
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2090149605
Short name T82
Test name
Test status
Simulation time 1186695846 ps
CPU time 42.9 seconds
Started Jul 02 08:32:21 AM PDT 24
Finished Jul 02 08:33:05 AM PDT 24
Peak memory 256804 kb
Host smart-4ec225e0-fc3e-4311-a0b8-23fe24ceb32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20901
49605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2090149605
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1096862733
Short name T216
Test name
Test status
Simulation time 1722907650 ps
CPU time 78.42 seconds
Started Jul 02 08:32:22 AM PDT 24
Finished Jul 02 08:33:42 AM PDT 24
Peak memory 257040 kb
Host smart-6df0a92b-3eac-497e-8645-9fdabf2d112a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968
62733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1096862733
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.262467213
Short name T618
Test name
Test status
Simulation time 369312215 ps
CPU time 4.99 seconds
Started Jul 02 08:32:21 AM PDT 24
Finished Jul 02 08:32:27 AM PDT 24
Peak memory 241028 kb
Host smart-556de106-8a81-4da3-937b-dd167e3ebeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
7213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.262467213
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1634529421
Short name T650
Test name
Test status
Simulation time 622079786 ps
CPU time 9.43 seconds
Started Jul 02 08:32:21 AM PDT 24
Finished Jul 02 08:32:31 AM PDT 24
Peak memory 252136 kb
Host smart-4cb8e1f3-2f1e-4964-ba3f-d8528ac38e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16345
29421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1634529421
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3286613701
Short name T429
Test name
Test status
Simulation time 298946006296 ps
CPU time 7759.03 seconds
Started Jul 02 08:32:28 AM PDT 24
Finished Jul 02 10:41:49 AM PDT 24
Peak memory 370936 kb
Host smart-f30709a3-3854-40d2-821a-c0a38a5e4428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286613701 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3286613701
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2936552364
Short name T195
Test name
Test status
Simulation time 115001359 ps
CPU time 3.14 seconds
Started Jul 02 08:32:36 AM PDT 24
Finished Jul 02 08:32:40 AM PDT 24
Peak memory 249516 kb
Host smart-d3a78ac4-8183-474d-9eea-8117f47cb874
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2936552364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2936552364
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2541027599
Short name T428
Test name
Test status
Simulation time 29557613496 ps
CPU time 1703.97 seconds
Started Jul 02 08:32:32 AM PDT 24
Finished Jul 02 09:00:57 AM PDT 24
Peak memory 273716 kb
Host smart-2d3090c1-f3bb-4119-b679-478c8629c870
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541027599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2541027599
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1654314271
Short name T329
Test name
Test status
Simulation time 234959855 ps
CPU time 12.03 seconds
Started Jul 02 08:32:31 AM PDT 24
Finished Jul 02 08:32:44 AM PDT 24
Peak memory 249264 kb
Host smart-6eab5a79-6510-45b0-a7e8-0431d9e0d8a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1654314271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1654314271
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2901435350
Short name T477
Test name
Test status
Simulation time 18612532933 ps
CPU time 270.8 seconds
Started Jul 02 08:32:28 AM PDT 24
Finished Jul 02 08:37:00 AM PDT 24
Peak memory 257260 kb
Host smart-1a46faaf-e8ba-4dc0-82c6-c13107dd9b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29014
35350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2901435350
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1964860953
Short name T500
Test name
Test status
Simulation time 1806432080 ps
CPU time 22.9 seconds
Started Jul 02 08:32:27 AM PDT 24
Finished Jul 02 08:32:51 AM PDT 24
Peak memory 256592 kb
Host smart-7d5390d7-f370-44cb-a648-e980dab7b850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19648
60953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1964860953
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.511780725
Short name T610
Test name
Test status
Simulation time 14615195641 ps
CPU time 1371.44 seconds
Started Jul 02 08:32:31 AM PDT 24
Finished Jul 02 08:55:23 AM PDT 24
Peak memory 286896 kb
Host smart-72d4c0af-55a1-4b11-bd9b-7baabc02f791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511780725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.511780725
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1025354382
Short name T494
Test name
Test status
Simulation time 25599623801 ps
CPU time 631.6 seconds
Started Jul 02 08:32:33 AM PDT 24
Finished Jul 02 08:43:05 AM PDT 24
Peak memory 273824 kb
Host smart-5c327e6d-b7df-49ca-b57a-8e02cd7629c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025354382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1025354382
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.561141040
Short name T336
Test name
Test status
Simulation time 294047795 ps
CPU time 33.11 seconds
Started Jul 02 08:32:32 AM PDT 24
Finished Jul 02 08:33:06 AM PDT 24
Peak memory 256768 kb
Host smart-928639f6-5ee5-4cbc-871a-b7343f700fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56114
1040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.561141040
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.613410486
Short name T436
Test name
Test status
Simulation time 235834261 ps
CPU time 16.54 seconds
Started Jul 02 08:32:31 AM PDT 24
Finished Jul 02 08:32:49 AM PDT 24
Peak memory 248568 kb
Host smart-66199848-3d78-4be9-b5ac-ae6b78f19cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61341
0486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.613410486
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1703351766
Short name T572
Test name
Test status
Simulation time 1074556263 ps
CPU time 62.5 seconds
Started Jul 02 08:32:26 AM PDT 24
Finished Jul 02 08:33:30 AM PDT 24
Peak memory 249292 kb
Host smart-73b6f464-3559-4efc-b913-0b09e0c64d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
51766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1703351766
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2321266406
Short name T185
Test name
Test status
Simulation time 120257315 ps
CPU time 2.65 seconds
Started Jul 02 08:32:39 AM PDT 24
Finished Jul 02 08:32:42 AM PDT 24
Peak memory 249776 kb
Host smart-5452bf2e-c0f4-4062-8661-1a2dcb010d13
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2321266406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2321266406
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.133430733
Short name T612
Test name
Test status
Simulation time 21505461018 ps
CPU time 1313.16 seconds
Started Jul 02 08:32:34 AM PDT 24
Finished Jul 02 08:54:28 AM PDT 24
Peak memory 274000 kb
Host smart-87ca9955-1bcb-4608-9ef5-8dfcb50be26c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133430733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.133430733
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3907445523
Short name T381
Test name
Test status
Simulation time 1128060350 ps
CPU time 22.53 seconds
Started Jul 02 08:32:44 AM PDT 24
Finished Jul 02 08:33:07 AM PDT 24
Peak memory 249288 kb
Host smart-ccbcd058-25ec-43f1-afbc-8e3089366f71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3907445523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3907445523
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.4180520934
Short name T214
Test name
Test status
Simulation time 9187893890 ps
CPU time 121.07 seconds
Started Jul 02 08:32:38 AM PDT 24
Finished Jul 02 08:34:40 AM PDT 24
Peak memory 257580 kb
Host smart-4c28fdcb-751c-478a-b7ce-154e6843ab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
20934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.4180520934
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1049530455
Short name T377
Test name
Test status
Simulation time 313821253 ps
CPU time 9.63 seconds
Started Jul 02 08:32:38 AM PDT 24
Finished Jul 02 08:32:49 AM PDT 24
Peak memory 248808 kb
Host smart-0570d39e-2787-4c9c-8243-88325d90def6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10495
30455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1049530455
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.4179898391
Short name T320
Test name
Test status
Simulation time 19742849464 ps
CPU time 1601.56 seconds
Started Jul 02 08:32:37 AM PDT 24
Finished Jul 02 08:59:19 AM PDT 24
Peak memory 282164 kb
Host smart-b5b47e5f-da9d-4eee-8005-362396cc4ed7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179898391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.4179898391
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3960681965
Short name T512
Test name
Test status
Simulation time 188692555398 ps
CPU time 2780.38 seconds
Started Jul 02 08:32:35 AM PDT 24
Finished Jul 02 09:18:57 AM PDT 24
Peak memory 287144 kb
Host smart-49d6305b-4684-4846-a9e2-3775267bf75e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960681965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3960681965
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2372491556
Short name T400
Test name
Test status
Simulation time 421332941 ps
CPU time 25.79 seconds
Started Jul 02 08:32:37 AM PDT 24
Finished Jul 02 08:33:03 AM PDT 24
Peak memory 256832 kb
Host smart-8aacc4c7-3a7a-41a8-af3e-d0cc2df69557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23724
91556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2372491556
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.230432968
Short name T580
Test name
Test status
Simulation time 242523554 ps
CPU time 24.92 seconds
Started Jul 02 08:32:34 AM PDT 24
Finished Jul 02 08:33:00 AM PDT 24
Peak memory 248772 kb
Host smart-385d4ccb-68e6-4d2b-bcd5-9e8ce881bd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23043
2968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.230432968
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.975019646
Short name T694
Test name
Test status
Simulation time 330132669 ps
CPU time 21.25 seconds
Started Jul 02 08:32:38 AM PDT 24
Finished Jul 02 08:33:00 AM PDT 24
Peak memory 248984 kb
Host smart-dcabbb46-f194-42ac-a4fb-d0404d45bd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97501
9646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.975019646
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.953218622
Short name T370
Test name
Test status
Simulation time 320475417 ps
CPU time 14.39 seconds
Started Jul 02 08:32:36 AM PDT 24
Finished Jul 02 08:32:51 AM PDT 24
Peak memory 255388 kb
Host smart-a03a6837-f4c7-489d-b243-5ead4b16cccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95321
8622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.953218622
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4000315265
Short name T393
Test name
Test status
Simulation time 11209473129 ps
CPU time 296.74 seconds
Started Jul 02 08:32:40 AM PDT 24
Finished Jul 02 08:37:37 AM PDT 24
Peak memory 257768 kb
Host smart-8bd382c4-8c15-4e3c-90f6-924e51ab080b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000315265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4000315265
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1833695965
Short name T192
Test name
Test status
Simulation time 65782856 ps
CPU time 2.54 seconds
Started Jul 02 08:32:45 AM PDT 24
Finished Jul 02 08:32:48 AM PDT 24
Peak memory 249500 kb
Host smart-f6c5ac1c-646a-43a4-bd24-3aef0bf4cb10
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1833695965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1833695965
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3090115833
Short name T38
Test name
Test status
Simulation time 9345749323 ps
CPU time 721.21 seconds
Started Jul 02 08:32:45 AM PDT 24
Finished Jul 02 08:44:47 AM PDT 24
Peak memory 268908 kb
Host smart-496ad3b9-95b2-4ab4-af80-83f712dac7f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090115833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3090115833
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1593303333
Short name T115
Test name
Test status
Simulation time 6378767750 ps
CPU time 70.64 seconds
Started Jul 02 08:32:44 AM PDT 24
Finished Jul 02 08:33:55 AM PDT 24
Peak memory 249408 kb
Host smart-1430e8a2-7b28-4fdd-aafb-05f6db30c7c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1593303333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1593303333
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3923682539
Short name T569
Test name
Test status
Simulation time 7082792433 ps
CPU time 144.85 seconds
Started Jul 02 08:32:41 AM PDT 24
Finished Jul 02 08:35:07 AM PDT 24
Peak memory 257740 kb
Host smart-3acfb0c3-4269-47b9-a33a-4f7b3ba9d849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
82539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3923682539
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2151145583
Short name T66
Test name
Test status
Simulation time 2946986026 ps
CPU time 49.58 seconds
Started Jul 02 08:32:40 AM PDT 24
Finished Jul 02 08:33:30 AM PDT 24
Peak memory 257580 kb
Host smart-07e0f82b-4829-4ca7-89d5-882b59d94893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21511
45583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2151145583
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1980614653
Short name T491
Test name
Test status
Simulation time 37451621086 ps
CPU time 902.88 seconds
Started Jul 02 08:32:45 AM PDT 24
Finished Jul 02 08:47:49 AM PDT 24
Peak memory 274032 kb
Host smart-6deb05f0-2122-4ad8-96d8-dd452127630f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980614653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1980614653
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1021691583
Short name T547
Test name
Test status
Simulation time 35452966343 ps
CPU time 2325.06 seconds
Started Jul 02 08:32:45 AM PDT 24
Finished Jul 02 09:11:31 AM PDT 24
Peak memory 273996 kb
Host smart-00ebf9d4-b846-471f-8e8a-b893a679f0b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021691583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1021691583
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2229069046
Short name T642
Test name
Test status
Simulation time 18067841227 ps
CPU time 363.51 seconds
Started Jul 02 08:32:45 AM PDT 24
Finished Jul 02 08:38:50 AM PDT 24
Peak memory 256088 kb
Host smart-6f619e02-f58a-408d-8574-72c56fa81dfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229069046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2229069046
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2643124217
Short name T338
Test name
Test status
Simulation time 1562161937 ps
CPU time 28.65 seconds
Started Jul 02 08:32:40 AM PDT 24
Finished Jul 02 08:33:09 AM PDT 24
Peak memory 257180 kb
Host smart-8074c5d8-020f-45d7-b339-3c17acf31200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26431
24217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2643124217
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1718289642
Short name T616
Test name
Test status
Simulation time 454025659 ps
CPU time 17.94 seconds
Started Jul 02 08:32:40 AM PDT 24
Finished Jul 02 08:32:58 AM PDT 24
Peak memory 249292 kb
Host smart-d6bc8ac6-2901-4432-9df7-0ec2e8204f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17182
89642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1718289642
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3701302641
Short name T240
Test name
Test status
Simulation time 96036488 ps
CPU time 7.05 seconds
Started Jul 02 08:32:40 AM PDT 24
Finished Jul 02 08:32:47 AM PDT 24
Peak memory 249256 kb
Host smart-2bebb2f7-cbbb-44a7-90ec-3f8e070ddedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
02641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3701302641
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3687087239
Short name T690
Test name
Test status
Simulation time 548099149 ps
CPU time 36.02 seconds
Started Jul 02 08:32:42 AM PDT 24
Finished Jul 02 08:33:19 AM PDT 24
Peak memory 249624 kb
Host smart-dfb33948-8b42-4720-b0cc-69a625dc2031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
87239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3687087239
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3281570570
Short name T584
Test name
Test status
Simulation time 2213061004 ps
CPU time 128.41 seconds
Started Jul 02 08:32:49 AM PDT 24
Finished Jul 02 08:34:58 AM PDT 24
Peak memory 257608 kb
Host smart-64221205-1c54-4e9a-a280-ff95e9dfcbaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281570570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3281570570
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1517700017
Short name T204
Test name
Test status
Simulation time 109646430 ps
CPU time 3.12 seconds
Started Jul 02 08:32:56 AM PDT 24
Finished Jul 02 08:33:00 AM PDT 24
Peak memory 249564 kb
Host smart-888ce18e-e845-4318-85f1-e80d80df4208
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1517700017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1517700017
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3857771913
Short name T529
Test name
Test status
Simulation time 71351734724 ps
CPU time 1944.69 seconds
Started Jul 02 08:32:49 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 290140 kb
Host smart-cc36ac57-0da9-48f4-af4f-d8854f7ea404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857771913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3857771913
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1347983471
Short name T656
Test name
Test status
Simulation time 3389459521 ps
CPU time 76.3 seconds
Started Jul 02 08:32:49 AM PDT 24
Finished Jul 02 08:34:07 AM PDT 24
Peak memory 249312 kb
Host smart-6603c865-74b3-4256-bbca-6ba123fca76d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1347983471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1347983471
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2139882312
Short name T543
Test name
Test status
Simulation time 5087027256 ps
CPU time 319.55 seconds
Started Jul 02 08:32:48 AM PDT 24
Finished Jul 02 08:38:08 AM PDT 24
Peak memory 257556 kb
Host smart-8b915410-f25c-4d10-84f8-2b331ec43d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21398
82312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2139882312
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.235353764
Short name T15
Test name
Test status
Simulation time 445359167 ps
CPU time 14.95 seconds
Started Jul 02 08:32:48 AM PDT 24
Finished Jul 02 08:33:03 AM PDT 24
Peak memory 257484 kb
Host smart-92f21956-cd3a-4858-9ac6-52723e788af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23535
3764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.235353764
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1077814546
Short name T550
Test name
Test status
Simulation time 105995738054 ps
CPU time 2904.09 seconds
Started Jul 02 08:32:51 AM PDT 24
Finished Jul 02 09:21:16 AM PDT 24
Peak memory 287804 kb
Host smart-ea338f63-fac1-416b-927f-e452736ab6dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077814546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1077814546
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2208079166
Short name T626
Test name
Test status
Simulation time 20225232698 ps
CPU time 1193.39 seconds
Started Jul 02 08:32:50 AM PDT 24
Finished Jul 02 08:52:44 AM PDT 24
Peak memory 290160 kb
Host smart-5a764a15-0dc1-4519-86e9-57e4bc87b7bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208079166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2208079166
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3711172882
Short name T294
Test name
Test status
Simulation time 23467629140 ps
CPU time 498.3 seconds
Started Jul 02 08:32:50 AM PDT 24
Finished Jul 02 08:41:10 AM PDT 24
Peak memory 249408 kb
Host smart-63e7f0dd-c896-432b-8b0d-77d22c6043a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711172882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3711172882
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2966118263
Short name T212
Test name
Test status
Simulation time 777979991 ps
CPU time 11.19 seconds
Started Jul 02 08:32:47 AM PDT 24
Finished Jul 02 08:32:59 AM PDT 24
Peak memory 249324 kb
Host smart-f23b9a02-6166-4116-bb80-4095ad874f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29661
18263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2966118263
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1139620298
Short name T340
Test name
Test status
Simulation time 815650815 ps
CPU time 16.81 seconds
Started Jul 02 08:32:45 AM PDT 24
Finished Jul 02 08:33:03 AM PDT 24
Peak memory 248588 kb
Host smart-3a2977a7-81d0-4f5d-83c0-daa0b6d6be3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11396
20298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1139620298
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2955679225
Short name T573
Test name
Test status
Simulation time 75441724 ps
CPU time 3.6 seconds
Started Jul 02 08:32:49 AM PDT 24
Finished Jul 02 08:32:54 AM PDT 24
Peak memory 240368 kb
Host smart-92e6bafb-71fd-4536-b1db-b3ebe080dccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556
79225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2955679225
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.296151066
Short name T267
Test name
Test status
Simulation time 623960785 ps
CPU time 33.5 seconds
Started Jul 02 08:32:49 AM PDT 24
Finished Jul 02 08:33:22 AM PDT 24
Peak memory 249468 kb
Host smart-3f7ee0f8-dfeb-4c4f-abaa-2f4ead4da3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29615
1066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.296151066
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3067088642
Short name T189
Test name
Test status
Simulation time 165002349 ps
CPU time 3.55 seconds
Started Jul 02 08:31:07 AM PDT 24
Finished Jul 02 08:31:11 AM PDT 24
Peak memory 249592 kb
Host smart-1c564bcb-d786-46e2-9940-1dde3a4118ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3067088642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3067088642
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2768970590
Short name T479
Test name
Test status
Simulation time 46535194959 ps
CPU time 2660.46 seconds
Started Jul 02 08:31:08 AM PDT 24
Finished Jul 02 09:15:29 AM PDT 24
Peak memory 289704 kb
Host smart-965865cc-9e4c-4260-b72e-5a2b461a44df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768970590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2768970590
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.4045507889
Short name T684
Test name
Test status
Simulation time 2725832590 ps
CPU time 12.62 seconds
Started Jul 02 08:31:07 AM PDT 24
Finished Jul 02 08:31:20 AM PDT 24
Peak memory 249428 kb
Host smart-147f9682-5503-4c3b-8ced-53d7e87fc931
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4045507889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.4045507889
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1825396982
Short name T577
Test name
Test status
Simulation time 44872342358 ps
CPU time 331.43 seconds
Started Jul 02 08:31:06 AM PDT 24
Finished Jul 02 08:36:38 AM PDT 24
Peak memory 257612 kb
Host smart-57806c73-1b80-41bf-aa79-a037afb3532a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18253
96982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1825396982
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2197615572
Short name T609
Test name
Test status
Simulation time 3348707912 ps
CPU time 28.94 seconds
Started Jul 02 08:31:05 AM PDT 24
Finished Jul 02 08:31:35 AM PDT 24
Peak memory 257556 kb
Host smart-a3983194-7fec-437a-a225-d99ac21378be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21976
15572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2197615572
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3791561043
Short name T114
Test name
Test status
Simulation time 34166508524 ps
CPU time 1471.72 seconds
Started Jul 02 08:31:08 AM PDT 24
Finished Jul 02 08:55:41 AM PDT 24
Peak memory 273948 kb
Host smart-a52d2d56-4e24-4b10-8e3c-6b6a6a89e864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791561043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3791561043
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3001485773
Short name T674
Test name
Test status
Simulation time 25249664456 ps
CPU time 501.9 seconds
Started Jul 02 08:31:09 AM PDT 24
Finished Jul 02 08:39:31 AM PDT 24
Peak memory 249408 kb
Host smart-83c8fdae-5431-4254-a14a-a21eb9fd84d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001485773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3001485773
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3072821080
Short name T399
Test name
Test status
Simulation time 239701898 ps
CPU time 24.74 seconds
Started Jul 02 08:31:07 AM PDT 24
Finished Jul 02 08:31:33 AM PDT 24
Peak memory 256656 kb
Host smart-e2918c9f-c606-4156-8b63-ff8940a7f5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30728
21080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3072821080
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2940767285
Short name T351
Test name
Test status
Simulation time 212917770 ps
CPU time 15.88 seconds
Started Jul 02 08:31:07 AM PDT 24
Finished Jul 02 08:31:23 AM PDT 24
Peak memory 256996 kb
Host smart-fa045de4-db3c-46df-9126-e1fadedeb642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29407
67285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2940767285
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1027419672
Short name T97
Test name
Test status
Simulation time 91683327 ps
CPU time 6.69 seconds
Started Jul 02 08:31:08 AM PDT 24
Finished Jul 02 08:31:16 AM PDT 24
Peak memory 248616 kb
Host smart-9da7709e-b6f4-4481-9cb0-1690e3e04bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
19672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1027419672
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1245780904
Short name T457
Test name
Test status
Simulation time 1681649746 ps
CPU time 33.17 seconds
Started Jul 02 08:31:08 AM PDT 24
Finished Jul 02 08:31:42 AM PDT 24
Peak memory 257424 kb
Host smart-dc798e29-c520-4b85-825c-9a950df9c6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12457
80904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1245780904
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.533030654
Short name T57
Test name
Test status
Simulation time 349177980977 ps
CPU time 1561.7 seconds
Started Jul 02 08:31:07 AM PDT 24
Finished Jul 02 08:57:10 AM PDT 24
Peak memory 290428 kb
Host smart-6aa80b7c-0990-4e48-a7b2-a66712b8bc94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533030654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.533030654
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2910424148
Short name T485
Test name
Test status
Simulation time 30963645869 ps
CPU time 2219.54 seconds
Started Jul 02 08:32:56 AM PDT 24
Finished Jul 02 09:09:56 AM PDT 24
Peak memory 290164 kb
Host smart-8a1683e9-025b-4ee5-bf62-bc4799dd3ebf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910424148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2910424148
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4141111766
Short name T591
Test name
Test status
Simulation time 427584875 ps
CPU time 12.26 seconds
Started Jul 02 08:32:55 AM PDT 24
Finished Jul 02 08:33:08 AM PDT 24
Peak memory 255320 kb
Host smart-da185a94-00ea-4548-aa45-adff1ef848b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41411
11766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4141111766
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.173788945
Short name T408
Test name
Test status
Simulation time 484962384 ps
CPU time 7.43 seconds
Started Jul 02 08:32:54 AM PDT 24
Finished Jul 02 08:33:02 AM PDT 24
Peak memory 249276 kb
Host smart-60a21a3f-1c2d-4965-a759-6de79c33df67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
8945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.173788945
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1311083761
Short name T273
Test name
Test status
Simulation time 169351117012 ps
CPU time 2509.41 seconds
Started Jul 02 08:33:02 AM PDT 24
Finished Jul 02 09:14:53 AM PDT 24
Peak memory 288480 kb
Host smart-fd399f17-d73d-449e-aa5e-1f1ff796fed9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311083761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1311083761
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1342653136
Short name T402
Test name
Test status
Simulation time 31103313645 ps
CPU time 1465.8 seconds
Started Jul 02 08:32:59 AM PDT 24
Finished Jul 02 08:57:26 AM PDT 24
Peak memory 273368 kb
Host smart-b2dde3a4-a869-46ca-91b7-81131a20db0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342653136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1342653136
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1739419597
Short name T207
Test name
Test status
Simulation time 43631069010 ps
CPU time 230.45 seconds
Started Jul 02 08:32:55 AM PDT 24
Finished Jul 02 08:36:46 AM PDT 24
Peak memory 255832 kb
Host smart-5dde0d73-d923-4329-ab8d-6d6bbea6522f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739419597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1739419597
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1842055522
Short name T56
Test name
Test status
Simulation time 1713395529 ps
CPU time 33.9 seconds
Started Jul 02 08:32:55 AM PDT 24
Finished Jul 02 08:33:29 AM PDT 24
Peak memory 256804 kb
Host smart-143aeba6-fd9b-4ac5-b822-796ebce94630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420
55522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1842055522
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3976873569
Short name T575
Test name
Test status
Simulation time 30707277 ps
CPU time 5.81 seconds
Started Jul 02 08:32:53 AM PDT 24
Finished Jul 02 08:33:00 AM PDT 24
Peak memory 252960 kb
Host smart-1a741360-9b78-4d9d-8da1-a59ae5086d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39768
73569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3976873569
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2934074380
Short name T518
Test name
Test status
Simulation time 774774513 ps
CPU time 52.63 seconds
Started Jul 02 08:32:55 AM PDT 24
Finished Jul 02 08:33:49 AM PDT 24
Peak memory 256760 kb
Host smart-92b65cc5-0df7-41fa-b0f1-632a864fda0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340
74380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2934074380
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.521158516
Short name T466
Test name
Test status
Simulation time 60634855 ps
CPU time 5.19 seconds
Started Jul 02 08:32:55 AM PDT 24
Finished Jul 02 08:33:01 AM PDT 24
Peak memory 251488 kb
Host smart-c208f238-28bc-4319-82cc-b0a921161ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52115
8516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.521158516
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1019934788
Short name T241
Test name
Test status
Simulation time 35968139921 ps
CPU time 550.87 seconds
Started Jul 02 08:33:02 AM PDT 24
Finished Jul 02 08:42:15 AM PDT 24
Peak memory 257612 kb
Host smart-152a566a-67f0-4a73-9d93-59d799d69720
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019934788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1019934788
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3085262722
Short name T235
Test name
Test status
Simulation time 14741111455 ps
CPU time 949.56 seconds
Started Jul 02 08:33:01 AM PDT 24
Finished Jul 02 08:48:52 AM PDT 24
Peak memory 271172 kb
Host smart-00e1ba73-f1fb-494b-884c-d0dde85a6823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085262722 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3085262722
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2951746824
Short name T362
Test name
Test status
Simulation time 39051455408 ps
CPU time 1553.43 seconds
Started Jul 02 08:33:03 AM PDT 24
Finished Jul 02 08:58:58 AM PDT 24
Peak memory 289880 kb
Host smart-11bd0834-f80a-4bf5-a041-62e81a620050
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951746824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2951746824
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3017550062
Short name T264
Test name
Test status
Simulation time 1055073196 ps
CPU time 97 seconds
Started Jul 02 08:33:03 AM PDT 24
Finished Jul 02 08:34:41 AM PDT 24
Peak memory 257004 kb
Host smart-1a87e060-bbfe-4af4-a2b3-29fccec42bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30175
50062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3017550062
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.148107401
Short name T578
Test name
Test status
Simulation time 1175359488 ps
CPU time 29.28 seconds
Started Jul 02 08:33:01 AM PDT 24
Finished Jul 02 08:33:31 AM PDT 24
Peak memory 256332 kb
Host smart-35fe25cc-fbb1-45ba-b2e8-ca7e767b7349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14810
7401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.148107401
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.538104973
Short name T315
Test name
Test status
Simulation time 153604533666 ps
CPU time 2170.74 seconds
Started Jul 02 08:33:05 AM PDT 24
Finished Jul 02 09:09:16 AM PDT 24
Peak memory 286136 kb
Host smart-2cd37449-d0c2-4e74-a863-d25fa851a9aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538104973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.538104973
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3453353166
Short name T639
Test name
Test status
Simulation time 32452532547 ps
CPU time 1559.94 seconds
Started Jul 02 08:33:04 AM PDT 24
Finished Jul 02 08:59:04 AM PDT 24
Peak memory 289628 kb
Host smart-e7cb48f9-d82f-4b44-a906-2e976391bcc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453353166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3453353166
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1220864007
Short name T220
Test name
Test status
Simulation time 101191279513 ps
CPU time 547.28 seconds
Started Jul 02 08:33:05 AM PDT 24
Finished Jul 02 08:42:13 AM PDT 24
Peak memory 249240 kb
Host smart-ad614210-5549-42e7-94f3-7e3d9d88a1de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220864007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1220864007
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2376723029
Short name T470
Test name
Test status
Simulation time 924560764 ps
CPU time 33.67 seconds
Started Jul 02 08:32:59 AM PDT 24
Finished Jul 02 08:33:34 AM PDT 24
Peak memory 256792 kb
Host smart-7284cf78-d80b-43c5-a854-d3d196aa7dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23767
23029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2376723029
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1927464212
Short name T679
Test name
Test status
Simulation time 650246691 ps
CPU time 47.29 seconds
Started Jul 02 08:32:58 AM PDT 24
Finished Jul 02 08:33:47 AM PDT 24
Peak memory 256764 kb
Host smart-d9d37326-4f84-49f2-9075-8c89db4489a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274
64212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1927464212
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3527500490
Short name T257
Test name
Test status
Simulation time 1934882634 ps
CPU time 19.84 seconds
Started Jul 02 08:32:59 AM PDT 24
Finished Jul 02 08:33:20 AM PDT 24
Peak memory 248816 kb
Host smart-b0953b2d-55d8-42df-a93a-72518763f654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35275
00490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3527500490
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.4267615868
Short name T515
Test name
Test status
Simulation time 962544619 ps
CPU time 10.04 seconds
Started Jul 02 08:32:58 AM PDT 24
Finished Jul 02 08:33:09 AM PDT 24
Peak memory 249112 kb
Host smart-a3bca0b4-5a75-4452-9451-83958e227ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
15868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4267615868
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2708779909
Short name T92
Test name
Test status
Simulation time 16351694695 ps
CPU time 1236.37 seconds
Started Jul 02 08:33:04 AM PDT 24
Finished Jul 02 08:53:41 AM PDT 24
Peak memory 282168 kb
Host smart-913b356b-ffcd-49a6-a68e-0f2bcfd0b491
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708779909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2708779909
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3067036405
Short name T471
Test name
Test status
Simulation time 161650155909 ps
CPU time 2617.33 seconds
Started Jul 02 08:33:08 AM PDT 24
Finished Jul 02 09:16:46 AM PDT 24
Peak memory 285496 kb
Host smart-5c169ec7-c023-44fa-8281-59a283a0d22f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067036405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3067036405
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3525872709
Short name T80
Test name
Test status
Simulation time 5005438178 ps
CPU time 60.59 seconds
Started Jul 02 08:33:09 AM PDT 24
Finished Jul 02 08:34:10 AM PDT 24
Peak memory 249416 kb
Host smart-afb7157e-0a34-476a-9d0d-23257a25dfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35258
72709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3525872709
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2781907346
Short name T444
Test name
Test status
Simulation time 7589933529 ps
CPU time 749.42 seconds
Started Jul 02 08:33:14 AM PDT 24
Finished Jul 02 08:45:44 AM PDT 24
Peak memory 273956 kb
Host smart-90b1e369-84e3-412a-8e59-a8943abfba96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781907346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2781907346
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3141505793
Short name T536
Test name
Test status
Simulation time 8351601023 ps
CPU time 612.16 seconds
Started Jul 02 08:33:13 AM PDT 24
Finished Jul 02 08:43:26 AM PDT 24
Peak memory 265732 kb
Host smart-1e7e0e71-8e97-4b51-92b6-f1e214caf892
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141505793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3141505793
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3945409346
Short name T288
Test name
Test status
Simulation time 62223395615 ps
CPU time 691.62 seconds
Started Jul 02 08:33:09 AM PDT 24
Finished Jul 02 08:44:41 AM PDT 24
Peak memory 249408 kb
Host smart-5d3fea3d-8fb7-42fd-a0de-8825e165aba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945409346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3945409346
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1015470575
Short name T463
Test name
Test status
Simulation time 58330975 ps
CPU time 4.93 seconds
Started Jul 02 08:33:09 AM PDT 24
Finished Jul 02 08:33:15 AM PDT 24
Peak memory 249244 kb
Host smart-1e8dfe13-a17b-4a7c-bfa1-b263ee89f9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10154
70575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1015470575
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1414780223
Short name T81
Test name
Test status
Simulation time 227044731 ps
CPU time 13.35 seconds
Started Jul 02 08:33:11 AM PDT 24
Finished Jul 02 08:33:24 AM PDT 24
Peak memory 255108 kb
Host smart-152ca738-26aa-4313-b269-4b1559f9fa91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14147
80223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1414780223
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3727929527
Short name T464
Test name
Test status
Simulation time 347693772 ps
CPU time 34.07 seconds
Started Jul 02 08:33:10 AM PDT 24
Finished Jul 02 08:33:44 AM PDT 24
Peak memory 250240 kb
Host smart-5ff0ef70-e5e0-4276-aea7-95cdaf41796c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37279
29527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3727929527
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1397852768
Short name T19
Test name
Test status
Simulation time 1611741534 ps
CPU time 26.9 seconds
Started Jul 02 08:33:10 AM PDT 24
Finished Jul 02 08:33:37 AM PDT 24
Peak memory 256948 kb
Host smart-bea252a9-f7eb-4f5a-bbd1-ec421150aba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13978
52768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1397852768
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.654934323
Short name T658
Test name
Test status
Simulation time 109622450003 ps
CPU time 1899.98 seconds
Started Jul 02 08:33:19 AM PDT 24
Finished Jul 02 09:05:00 AM PDT 24
Peak memory 273736 kb
Host smart-355ac62c-a3dc-47d3-ba15-691227bfd1d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654934323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.654934323
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.667752957
Short name T433
Test name
Test status
Simulation time 577811594 ps
CPU time 46.15 seconds
Started Jul 02 08:33:15 AM PDT 24
Finished Jul 02 08:34:02 AM PDT 24
Peak memory 257004 kb
Host smart-767b70d0-d9a9-4d27-b36b-a49d630f2d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66775
2957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.667752957
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1048263253
Short name T562
Test name
Test status
Simulation time 395943991 ps
CPU time 19.27 seconds
Started Jul 02 08:33:15 AM PDT 24
Finished Jul 02 08:33:35 AM PDT 24
Peak memory 249228 kb
Host smart-44676628-590e-4676-9ef7-c4a317b12251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10482
63253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1048263253
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4122680610
Short name T312
Test name
Test status
Simulation time 76421277482 ps
CPU time 2503.24 seconds
Started Jul 02 08:33:18 AM PDT 24
Finished Jul 02 09:15:02 AM PDT 24
Peak memory 289708 kb
Host smart-ef6965fe-821c-4319-98a3-37096fa7ba0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122680610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4122680610
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2492655709
Short name T83
Test name
Test status
Simulation time 38830468061 ps
CPU time 2288.46 seconds
Started Jul 02 08:33:19 AM PDT 24
Finished Jul 02 09:11:28 AM PDT 24
Peak memory 289504 kb
Host smart-0894171d-30b1-41c9-9fad-d37ec7a6b357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492655709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2492655709
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3444917888
Short name T678
Test name
Test status
Simulation time 43957786673 ps
CPU time 465.11 seconds
Started Jul 02 08:33:19 AM PDT 24
Finished Jul 02 08:41:05 AM PDT 24
Peak memory 249408 kb
Host smart-562876d2-42be-47f3-adf8-96f8b0c7f17b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444917888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3444917888
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3950568038
Short name T453
Test name
Test status
Simulation time 1945903974 ps
CPU time 49.59 seconds
Started Jul 02 08:33:13 AM PDT 24
Finished Jul 02 08:34:03 AM PDT 24
Peak memory 249232 kb
Host smart-b8b898e0-b6f8-4052-af34-cd52de3b6294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39505
68038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3950568038
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1743305561
Short name T557
Test name
Test status
Simulation time 902100421 ps
CPU time 57.31 seconds
Started Jul 02 08:33:15 AM PDT 24
Finished Jul 02 08:34:12 AM PDT 24
Peak memory 256416 kb
Host smart-36259092-9693-4657-b57c-ea187ddc533b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
05561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1743305561
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1415390152
Short name T372
Test name
Test status
Simulation time 2829699890 ps
CPU time 40.48 seconds
Started Jul 02 08:33:15 AM PDT 24
Finished Jul 02 08:33:55 AM PDT 24
Peak memory 256320 kb
Host smart-526f9617-f9b5-43ef-87ba-55ccbbc78132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
90152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1415390152
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4199490157
Short name T373
Test name
Test status
Simulation time 7194765076 ps
CPU time 49.97 seconds
Started Jul 02 08:33:15 AM PDT 24
Finished Jul 02 08:34:05 AM PDT 24
Peak memory 256648 kb
Host smart-01c8c371-263c-40b7-afc7-d1959bb527da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41994
90157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4199490157
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4208601085
Short name T476
Test name
Test status
Simulation time 16073818932 ps
CPU time 1649.26 seconds
Started Jul 02 08:33:20 AM PDT 24
Finished Jul 02 09:00:50 AM PDT 24
Peak memory 289852 kb
Host smart-fca26d0c-14dc-45c0-a5f6-fcac14632474
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208601085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4208601085
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1032166711
Short name T230
Test name
Test status
Simulation time 72096887148 ps
CPU time 2513.09 seconds
Started Jul 02 08:33:28 AM PDT 24
Finished Jul 02 09:15:22 AM PDT 24
Peak memory 282904 kb
Host smart-6dc6b101-c707-409c-821d-0bce9c67756f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032166711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1032166711
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2172761286
Short name T206
Test name
Test status
Simulation time 3668661894 ps
CPU time 50.46 seconds
Started Jul 02 08:33:23 AM PDT 24
Finished Jul 02 08:34:14 AM PDT 24
Peak memory 257184 kb
Host smart-20045ac5-0859-4744-8542-bac6ffcc2a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21727
61286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2172761286
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2796639145
Short name T420
Test name
Test status
Simulation time 1433427749 ps
CPU time 39.6 seconds
Started Jul 02 08:33:23 AM PDT 24
Finished Jul 02 08:34:03 AM PDT 24
Peak memory 248972 kb
Host smart-bb369f14-47dc-48f7-bd2a-c4003f865b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27966
39145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2796639145
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.926774242
Short name T552
Test name
Test status
Simulation time 62121684897 ps
CPU time 1382.77 seconds
Started Jul 02 08:33:29 AM PDT 24
Finished Jul 02 08:56:32 AM PDT 24
Peak memory 273240 kb
Host smart-05bb93ee-36bb-4950-be27-62fdf71d2d61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926774242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.926774242
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1562188413
Short name T460
Test name
Test status
Simulation time 33656457083 ps
CPU time 2037.24 seconds
Started Jul 02 08:33:21 AM PDT 24
Finished Jul 02 09:07:19 AM PDT 24
Peak memory 273688 kb
Host smart-57809ebf-c25a-4571-b88b-4b5618f1a58b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562188413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1562188413
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.373166318
Short name T490
Test name
Test status
Simulation time 10073731432 ps
CPU time 406.92 seconds
Started Jul 02 08:33:24 AM PDT 24
Finished Jul 02 08:40:12 AM PDT 24
Peak memory 257556 kb
Host smart-e5a09f7f-b321-4190-bef2-15139c12cd75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373166318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.373166318
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2148833115
Short name T472
Test name
Test status
Simulation time 430605300 ps
CPU time 28.02 seconds
Started Jul 02 08:33:17 AM PDT 24
Finished Jul 02 08:33:46 AM PDT 24
Peak memory 249240 kb
Host smart-4984563b-dadb-4b05-932a-0d433f8e58c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
33115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2148833115
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2938809756
Short name T228
Test name
Test status
Simulation time 72992053 ps
CPU time 8.99 seconds
Started Jul 02 08:33:29 AM PDT 24
Finished Jul 02 08:33:39 AM PDT 24
Peak memory 248712 kb
Host smart-3114b8b5-7716-41bf-b89f-eddfc82a2496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
09756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2938809756
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2624149889
Short name T571
Test name
Test status
Simulation time 856365900 ps
CPU time 56.62 seconds
Started Jul 02 08:33:23 AM PDT 24
Finished Jul 02 08:34:21 AM PDT 24
Peak memory 256688 kb
Host smart-87e99d79-2967-4822-9243-57e1a829c3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26241
49889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2624149889
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3092383295
Short name T631
Test name
Test status
Simulation time 5548241464 ps
CPU time 46.2 seconds
Started Jul 02 08:33:17 AM PDT 24
Finished Jul 02 08:34:03 AM PDT 24
Peak memory 249556 kb
Host smart-31a3ab40-a0c5-4fbb-970c-a3720a800a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30923
83295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3092383295
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1535998942
Short name T21
Test name
Test status
Simulation time 179971966921 ps
CPU time 2819.84 seconds
Started Jul 02 08:33:27 AM PDT 24
Finished Jul 02 09:20:28 AM PDT 24
Peak memory 289408 kb
Host smart-0cba4cc9-976b-43fd-aa4e-46a9e3ecdc68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535998942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1535998942
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4046242654
Short name T699
Test name
Test status
Simulation time 222549717 ps
CPU time 24.03 seconds
Started Jul 02 08:33:28 AM PDT 24
Finished Jul 02 08:33:53 AM PDT 24
Peak memory 256788 kb
Host smart-55d44ad4-f80a-48e2-814c-252200f6caea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
42654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4046242654
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2003667114
Short name T548
Test name
Test status
Simulation time 423337656 ps
CPU time 20.44 seconds
Started Jul 02 08:33:26 AM PDT 24
Finished Jul 02 08:33:47 AM PDT 24
Peak memory 249260 kb
Host smart-a0be9d67-0f15-4b5a-980b-ab6745ac3abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20036
67114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2003667114
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.995666249
Short name T319
Test name
Test status
Simulation time 23068107985 ps
CPU time 1118.29 seconds
Started Jul 02 08:33:28 AM PDT 24
Finished Jul 02 08:52:07 AM PDT 24
Peak memory 273104 kb
Host smart-cc7ccbca-38bc-428b-a1c6-cdf8c74adabf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995666249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.995666249
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.298771464
Short name T627
Test name
Test status
Simulation time 22864914847 ps
CPU time 1315.9 seconds
Started Jul 02 08:33:27 AM PDT 24
Finished Jul 02 08:55:24 AM PDT 24
Peak memory 273108 kb
Host smart-9f187f50-b60a-4ee6-9e5f-fd6192d6536e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298771464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.298771464
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.4213669299
Short name T619
Test name
Test status
Simulation time 44560601636 ps
CPU time 464.42 seconds
Started Jul 02 08:33:30 AM PDT 24
Finished Jul 02 08:41:15 AM PDT 24
Peak memory 256420 kb
Host smart-5269704d-03dd-4016-aea7-117bf8c20dac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213669299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.4213669299
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2848331888
Short name T696
Test name
Test status
Simulation time 217530129 ps
CPU time 20.83 seconds
Started Jul 02 08:33:23 AM PDT 24
Finished Jul 02 08:33:45 AM PDT 24
Peak memory 256828 kb
Host smart-4a7bce2f-903b-4b14-ae55-7eda714afd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28483
31888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2848331888
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1684992930
Short name T534
Test name
Test status
Simulation time 474235327 ps
CPU time 37.67 seconds
Started Jul 02 08:33:27 AM PDT 24
Finished Jul 02 08:34:05 AM PDT 24
Peak memory 256564 kb
Host smart-3c65e41d-76db-4e10-b636-f9d0b3b1be4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16849
92930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1684992930
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3352564440
Short name T424
Test name
Test status
Simulation time 136338239 ps
CPU time 10 seconds
Started Jul 02 08:33:28 AM PDT 24
Finished Jul 02 08:33:38 AM PDT 24
Peak memory 249280 kb
Host smart-d088f43f-17cf-4097-8e60-933c1121b340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33525
64440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3352564440
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3720677485
Short name T391
Test name
Test status
Simulation time 503393328 ps
CPU time 10.37 seconds
Started Jul 02 08:33:23 AM PDT 24
Finished Jul 02 08:33:34 AM PDT 24
Peak memory 257448 kb
Host smart-7e0621bf-67bb-42f5-9f24-5d61dbef8bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37206
77485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3720677485
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1624705860
Short name T531
Test name
Test status
Simulation time 8909578701 ps
CPU time 812.96 seconds
Started Jul 02 08:33:32 AM PDT 24
Finished Jul 02 08:47:05 AM PDT 24
Peak memory 273248 kb
Host smart-aa64e6fd-f9bc-4b1b-9496-73d88ae9f8ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624705860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1624705860
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1673699905
Short name T259
Test name
Test status
Simulation time 42284801560 ps
CPU time 1028.87 seconds
Started Jul 02 08:33:31 AM PDT 24
Finished Jul 02 08:50:40 AM PDT 24
Peak memory 286048 kb
Host smart-c7141fae-85a6-4b6a-91d4-182edbf4b3ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673699905 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1673699905
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3844991143
Short name T703
Test name
Test status
Simulation time 48179735631 ps
CPU time 1607.6 seconds
Started Jul 02 08:33:33 AM PDT 24
Finished Jul 02 09:00:21 AM PDT 24
Peak memory 282992 kb
Host smart-abe47ef4-d0b8-4ac5-821c-ab3b248995a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844991143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3844991143
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2963295024
Short name T636
Test name
Test status
Simulation time 3687791206 ps
CPU time 165.06 seconds
Started Jul 02 08:33:33 AM PDT 24
Finished Jul 02 08:36:19 AM PDT 24
Peak memory 257108 kb
Host smart-c6c32ab7-dc6d-4b14-99b3-e963c2d0cd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
95024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2963295024
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.168981790
Short name T364
Test name
Test status
Simulation time 2014267600 ps
CPU time 40.72 seconds
Started Jul 02 08:33:34 AM PDT 24
Finished Jul 02 08:34:15 AM PDT 24
Peak memory 257460 kb
Host smart-eb3ae40c-4a52-4d4a-8ffa-29ca69b51293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16898
1790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.168981790
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.442908297
Short name T268
Test name
Test status
Simulation time 16071307688 ps
CPU time 1049.57 seconds
Started Jul 02 08:33:33 AM PDT 24
Finished Jul 02 08:51:03 AM PDT 24
Peak memory 273900 kb
Host smart-3de10f1b-0b5b-4fdd-b46b-a4fec4b94f11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442908297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.442908297
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1465449949
Short name T685
Test name
Test status
Simulation time 70625639314 ps
CPU time 1663.21 seconds
Started Jul 02 08:33:32 AM PDT 24
Finished Jul 02 09:01:16 AM PDT 24
Peak memory 273916 kb
Host smart-08d99041-9e28-4592-95ea-0885eb343c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465449949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1465449949
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.68573882
Short name T219
Test name
Test status
Simulation time 907607126 ps
CPU time 16.1 seconds
Started Jul 02 08:33:31 AM PDT 24
Finished Jul 02 08:33:48 AM PDT 24
Peak memory 249260 kb
Host smart-0b99ae47-efec-476a-a200-5201ddb62039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68573
882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.68573882
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3918432689
Short name T473
Test name
Test status
Simulation time 231973556 ps
CPU time 25.44 seconds
Started Jul 02 08:33:32 AM PDT 24
Finished Jul 02 08:33:58 AM PDT 24
Peak memory 248692 kb
Host smart-09806176-946a-4bc1-8797-b0e156a00fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
32689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3918432689
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1960652191
Short name T537
Test name
Test status
Simulation time 804485072 ps
CPU time 43.87 seconds
Started Jul 02 08:33:33 AM PDT 24
Finished Jul 02 08:34:18 AM PDT 24
Peak memory 256588 kb
Host smart-af305094-4ddb-40ae-8c42-a7143b5dc32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19606
52191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1960652191
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3395191439
Short name T576
Test name
Test status
Simulation time 1582172799 ps
CPU time 24.2 seconds
Started Jul 02 08:33:33 AM PDT 24
Finished Jul 02 08:33:58 AM PDT 24
Peak memory 257008 kb
Host smart-7d3ec92f-a8cd-422d-977d-92907cd542c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33951
91439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3395191439
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.85689478
Short name T106
Test name
Test status
Simulation time 63090674763 ps
CPU time 1700.45 seconds
Started Jul 02 08:33:36 AM PDT 24
Finished Jul 02 09:01:58 AM PDT 24
Peak memory 290008 kb
Host smart-36fe09ee-7c21-486e-ba38-cbe39ad2661d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85689478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_hand
ler_stress_all.85689478
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.346367488
Short name T105
Test name
Test status
Simulation time 37381608061 ps
CPU time 3396.09 seconds
Started Jul 02 08:33:37 AM PDT 24
Finished Jul 02 09:30:14 AM PDT 24
Peak memory 356028 kb
Host smart-3c843da0-9782-4f96-ba68-517b991e93e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346367488 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.346367488
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.59940080
Short name T561
Test name
Test status
Simulation time 23093763712 ps
CPU time 1063.35 seconds
Started Jul 02 08:33:37 AM PDT 24
Finished Jul 02 08:51:21 AM PDT 24
Peak memory 273328 kb
Host smart-953b353d-b60f-401c-9071-e8d84f1a1afb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59940080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.59940080
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2753194256
Short name T406
Test name
Test status
Simulation time 3115552492 ps
CPU time 90.53 seconds
Started Jul 02 08:33:36 AM PDT 24
Finished Jul 02 08:35:07 AM PDT 24
Peak memory 257504 kb
Host smart-e0e4ca4a-41ec-4b20-8f84-5eff84e1f9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27531
94256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2753194256
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3850469074
Short name T437
Test name
Test status
Simulation time 165215634 ps
CPU time 21.54 seconds
Started Jul 02 08:33:37 AM PDT 24
Finished Jul 02 08:33:59 AM PDT 24
Peak memory 257048 kb
Host smart-5b39d4eb-b78d-47df-8c81-bacec95732f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38504
69074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3850469074
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2793714776
Short name T677
Test name
Test status
Simulation time 31662954598 ps
CPU time 1048.97 seconds
Started Jul 02 08:33:43 AM PDT 24
Finished Jul 02 08:51:13 AM PDT 24
Peak memory 289960 kb
Host smart-7deb8864-df3a-4051-8b3d-38ab98cb9833
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793714776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2793714776
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3261886992
Short name T499
Test name
Test status
Simulation time 9606482453 ps
CPU time 112.22 seconds
Started Jul 02 08:33:36 AM PDT 24
Finished Jul 02 08:35:29 AM PDT 24
Peak memory 249384 kb
Host smart-48711f1c-1cce-46e9-9409-a10e87264e7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261886992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3261886992
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2588119331
Short name T392
Test name
Test status
Simulation time 819389358 ps
CPU time 27.63 seconds
Started Jul 02 08:33:37 AM PDT 24
Finished Jul 02 08:34:05 AM PDT 24
Peak memory 249288 kb
Host smart-4f40a463-fa8a-4a92-99f5-2a858d7171ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25881
19331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2588119331
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3226166235
Short name T519
Test name
Test status
Simulation time 1039112676 ps
CPU time 65.96 seconds
Started Jul 02 08:33:37 AM PDT 24
Finished Jul 02 08:34:44 AM PDT 24
Peak memory 250164 kb
Host smart-c45d8426-0a4d-4cd6-919c-8b4766e236bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32261
66235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3226166235
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1467352024
Short name T640
Test name
Test status
Simulation time 2823033532 ps
CPU time 46.47 seconds
Started Jul 02 08:33:38 AM PDT 24
Finished Jul 02 08:34:25 AM PDT 24
Peak memory 257536 kb
Host smart-3dc29f39-81a2-4359-84c3-cbd76003b462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14673
52024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1467352024
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2459501524
Short name T348
Test name
Test status
Simulation time 276219990080 ps
CPU time 3566.29 seconds
Started Jul 02 08:33:42 AM PDT 24
Finished Jul 02 09:33:10 AM PDT 24
Peak memory 289424 kb
Host smart-cbb12bce-edd0-44af-ad37-7535f87c0c8e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459501524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2459501524
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3967402906
Short name T245
Test name
Test status
Simulation time 3825552667 ps
CPU time 284.39 seconds
Started Jul 02 08:33:43 AM PDT 24
Finished Jul 02 08:38:28 AM PDT 24
Peak memory 265912 kb
Host smart-545a7d70-33e8-4ff2-a4cf-957d6999616d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967402906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3967402906
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3277784366
Short name T99
Test name
Test status
Simulation time 53992330513 ps
CPU time 1950.93 seconds
Started Jul 02 08:33:43 AM PDT 24
Finished Jul 02 09:06:15 AM PDT 24
Peak memory 272940 kb
Host smart-9919b897-2dd8-4e08-b4e4-1a406540dc7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277784366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3277784366
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1901262959
Short name T688
Test name
Test status
Simulation time 3880080709 ps
CPU time 128.66 seconds
Started Jul 02 08:33:43 AM PDT 24
Finished Jul 02 08:35:53 AM PDT 24
Peak memory 256944 kb
Host smart-ace829a4-35cb-4abb-a346-3bb3b4546ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012
62959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1901262959
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3108999802
Short name T667
Test name
Test status
Simulation time 2882512016 ps
CPU time 46.18 seconds
Started Jul 02 08:33:44 AM PDT 24
Finished Jul 02 08:34:31 AM PDT 24
Peak memory 249448 kb
Host smart-2d074617-b002-434a-b8f3-8752740445d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
99802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3108999802
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3041149712
Short name T574
Test name
Test status
Simulation time 30490838878 ps
CPU time 1971.99 seconds
Started Jul 02 08:33:46 AM PDT 24
Finished Jul 02 09:06:39 AM PDT 24
Peak memory 284788 kb
Host smart-0342ea90-a391-4de5-9a24-ba940ed10e80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041149712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3041149712
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.236417390
Short name T681
Test name
Test status
Simulation time 116997745298 ps
CPU time 2382.64 seconds
Started Jul 02 08:33:47 AM PDT 24
Finished Jul 02 09:13:30 AM PDT 24
Peak memory 287812 kb
Host smart-ecb50a2f-c15f-45ed-b563-5edb9241578f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236417390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.236417390
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4092356952
Short name T564
Test name
Test status
Simulation time 13846208376 ps
CPU time 523.09 seconds
Started Jul 02 08:33:46 AM PDT 24
Finished Jul 02 08:42:30 AM PDT 24
Peak memory 249372 kb
Host smart-79173e51-e596-4539-aeab-d3986607b441
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092356952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4092356952
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1915067767
Short name T368
Test name
Test status
Simulation time 354065194 ps
CPU time 18.21 seconds
Started Jul 02 08:33:42 AM PDT 24
Finished Jul 02 08:34:01 AM PDT 24
Peak memory 249288 kb
Host smart-df5487e6-ab10-4f2a-81f2-f57a86c86494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19150
67767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1915067767
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.674678579
Short name T110
Test name
Test status
Simulation time 1057335768 ps
CPU time 16.99 seconds
Started Jul 02 08:33:41 AM PDT 24
Finished Jul 02 08:33:59 AM PDT 24
Peak memory 249284 kb
Host smart-da9644ff-9e89-40ec-8a3e-fec66eaddb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67467
8579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.674678579
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3939984804
Short name T595
Test name
Test status
Simulation time 1662066662 ps
CPU time 41.31 seconds
Started Jul 02 08:33:43 AM PDT 24
Finished Jul 02 08:34:25 AM PDT 24
Peak memory 248756 kb
Host smart-6c22ebba-6a9d-4a3b-a3e7-12e0f191059f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39399
84804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3939984804
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2073995958
Short name T607
Test name
Test status
Simulation time 1790259603 ps
CPU time 66.45 seconds
Started Jul 02 08:33:41 AM PDT 24
Finished Jul 02 08:34:48 AM PDT 24
Peak memory 257496 kb
Host smart-baf409ae-ea80-471d-ba86-9eed822a9cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20739
95958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2073995958
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4046334298
Short name T64
Test name
Test status
Simulation time 45027398893 ps
CPU time 2855.4 seconds
Started Jul 02 08:33:50 AM PDT 24
Finished Jul 02 09:21:26 AM PDT 24
Peak memory 299604 kb
Host smart-9064c0d9-f249-4c6a-9b5d-875705c1663f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046334298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4046334298
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2798735689
Short name T394
Test name
Test status
Simulation time 45592276446 ps
CPU time 954.33 seconds
Started Jul 02 08:33:55 AM PDT 24
Finished Jul 02 08:49:50 AM PDT 24
Peak memory 273352 kb
Host smart-c41ff9d6-88af-4a2e-af39-a577a4d01e2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798735689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2798735689
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1515008842
Short name T469
Test name
Test status
Simulation time 2357516877 ps
CPU time 84.45 seconds
Started Jul 02 08:33:55 AM PDT 24
Finished Jul 02 08:35:20 AM PDT 24
Peak memory 257636 kb
Host smart-a0a83d1f-2769-42ce-8656-fb5d2fd86541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15150
08842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1515008842
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2045313751
Short name T538
Test name
Test status
Simulation time 417254335 ps
CPU time 8.26 seconds
Started Jul 02 08:33:57 AM PDT 24
Finished Jul 02 08:34:06 AM PDT 24
Peak memory 248816 kb
Host smart-4d414096-6539-4221-996d-ad8d08c18e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20453
13751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2045313751
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4085880170
Short name T556
Test name
Test status
Simulation time 30191774978 ps
CPU time 1291.21 seconds
Started Jul 02 08:33:57 AM PDT 24
Finished Jul 02 08:55:29 AM PDT 24
Peak memory 290308 kb
Host smart-31726d23-0eec-44db-9245-346a9b5fcfbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085880170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4085880170
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1570744858
Short name T614
Test name
Test status
Simulation time 62920415191 ps
CPU time 1600.55 seconds
Started Jul 02 08:34:01 AM PDT 24
Finished Jul 02 09:00:43 AM PDT 24
Peak memory 287368 kb
Host smart-0529830b-251c-499c-afad-acf1cf9481a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570744858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1570744858
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4154038870
Short name T507
Test name
Test status
Simulation time 43143551208 ps
CPU time 458.57 seconds
Started Jul 02 08:33:56 AM PDT 24
Finished Jul 02 08:41:35 AM PDT 24
Peak memory 249212 kb
Host smart-6fd5d3e1-41b3-4c18-a255-0a75b5e83cdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154038870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4154038870
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2277807829
Short name T59
Test name
Test status
Simulation time 236894562 ps
CPU time 26.11 seconds
Started Jul 02 08:33:51 AM PDT 24
Finished Jul 02 08:34:17 AM PDT 24
Peak memory 249132 kb
Host smart-cd795229-b0b6-4c8e-a38f-9ea3a34a6eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22778
07829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2277807829
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3623899763
Short name T544
Test name
Test status
Simulation time 3821236356 ps
CPU time 60.82 seconds
Started Jul 02 08:33:50 AM PDT 24
Finished Jul 02 08:34:51 AM PDT 24
Peak memory 257620 kb
Host smart-87f62948-e2f2-4abc-9f18-cb165e7d0099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36238
99763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3623899763
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3865950071
Short name T276
Test name
Test status
Simulation time 46886616 ps
CPU time 7.25 seconds
Started Jul 02 08:33:57 AM PDT 24
Finished Jul 02 08:34:05 AM PDT 24
Peak memory 253236 kb
Host smart-ee120bfd-99a8-424e-b042-edc533839694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38659
50071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3865950071
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2166228257
Short name T452
Test name
Test status
Simulation time 529092218 ps
CPU time 38.93 seconds
Started Jul 02 08:33:50 AM PDT 24
Finished Jul 02 08:34:29 AM PDT 24
Peak memory 257412 kb
Host smart-fa8852ff-e474-4e77-a4d8-3b8e7a4620f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
28257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2166228257
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2351242321
Short name T615
Test name
Test status
Simulation time 381710254 ps
CPU time 41.03 seconds
Started Jul 02 08:34:00 AM PDT 24
Finished Jul 02 08:34:41 AM PDT 24
Peak memory 256936 kb
Host smart-d9bd1279-eb6a-4199-9840-59739c8d5a08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351242321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2351242321
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.985738862
Short name T187
Test name
Test status
Simulation time 13309875 ps
CPU time 2.46 seconds
Started Jul 02 08:31:11 AM PDT 24
Finished Jul 02 08:31:14 AM PDT 24
Peak memory 249580 kb
Host smart-e6bef068-8ab5-4d2f-8900-cb6364453a75
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=985738862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.985738862
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1930811118
Short name T4
Test name
Test status
Simulation time 36737447493 ps
CPU time 1292.94 seconds
Started Jul 02 08:31:13 AM PDT 24
Finished Jul 02 08:52:47 AM PDT 24
Peak memory 287072 kb
Host smart-23bd78ac-03fb-4610-8419-f4976d395801
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930811118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1930811118
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2433288391
Short name T581
Test name
Test status
Simulation time 231471194 ps
CPU time 12.01 seconds
Started Jul 02 08:31:24 AM PDT 24
Finished Jul 02 08:31:37 AM PDT 24
Peak memory 249176 kb
Host smart-73bd40d7-1026-4c37-9dde-7888bcfd8135
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2433288391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2433288391
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.862610668
Short name T689
Test name
Test status
Simulation time 3927843267 ps
CPU time 101.95 seconds
Started Jul 02 08:31:11 AM PDT 24
Finished Jul 02 08:32:54 AM PDT 24
Peak memory 257532 kb
Host smart-d04e7ed2-2341-4b69-8e70-5f98f8b4809a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86261
0668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.862610668
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3403351661
Short name T376
Test name
Test status
Simulation time 1160117056 ps
CPU time 19.18 seconds
Started Jul 02 08:31:12 AM PDT 24
Finished Jul 02 08:31:32 AM PDT 24
Peak memory 256020 kb
Host smart-3b7e567d-4153-4970-bd21-22b722dd581c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34033
51661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3403351661
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2058286183
Short name T317
Test name
Test status
Simulation time 148880060598 ps
CPU time 1880.17 seconds
Started Jul 02 08:31:25 AM PDT 24
Finished Jul 02 09:02:46 AM PDT 24
Peak memory 273876 kb
Host smart-04344bef-4a55-4075-aab5-c2e6ca57cb52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058286183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2058286183
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1234339158
Short name T410
Test name
Test status
Simulation time 48734659224 ps
CPU time 1149.38 seconds
Started Jul 02 08:31:13 AM PDT 24
Finished Jul 02 08:50:23 AM PDT 24
Peak memory 271928 kb
Host smart-1e16a72e-cd17-4c26-b048-4e7f65233c99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234339158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1234339158
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1281734806
Short name T5
Test name
Test status
Simulation time 7873728414 ps
CPU time 332.17 seconds
Started Jul 02 08:31:12 AM PDT 24
Finished Jul 02 08:36:45 AM PDT 24
Peak memory 256656 kb
Host smart-6d0a8c26-582d-4ceb-adeb-8da4de4a168d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281734806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1281734806
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2193768914
Short name T383
Test name
Test status
Simulation time 3423514546 ps
CPU time 45.35 seconds
Started Jul 02 08:31:14 AM PDT 24
Finished Jul 02 08:32:00 AM PDT 24
Peak memory 257692 kb
Host smart-d76c16b8-4bd3-4b79-a76c-2230cd54f713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21937
68914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2193768914
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.621714734
Short name T88
Test name
Test status
Simulation time 1133770424 ps
CPU time 27.03 seconds
Started Jul 02 08:31:13 AM PDT 24
Finished Jul 02 08:31:40 AM PDT 24
Peak memory 249292 kb
Host smart-9c0f8762-6f76-4b22-b675-a692978cd7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62171
4734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.621714734
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.617124376
Short name T35
Test name
Test status
Simulation time 1725203723 ps
CPU time 23.93 seconds
Started Jul 02 08:31:24 AM PDT 24
Finished Jul 02 08:31:49 AM PDT 24
Peak memory 271776 kb
Host smart-220488d9-5070-4e5e-bac5-8ae00e3dab76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=617124376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.617124376
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2663091460
Short name T349
Test name
Test status
Simulation time 156297407 ps
CPU time 10.96 seconds
Started Jul 02 08:31:14 AM PDT 24
Finished Jul 02 08:31:26 AM PDT 24
Peak memory 248656 kb
Host smart-6ef38654-7ef5-431b-a83b-85a6a925a7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
91460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2663091460
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3225458439
Short name T551
Test name
Test status
Simulation time 207369461 ps
CPU time 5.31 seconds
Started Jul 02 08:31:10 AM PDT 24
Finished Jul 02 08:31:16 AM PDT 24
Peak memory 251408 kb
Host smart-44eb6f9f-141b-477b-be6b-9a22acfe96a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254
58439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3225458439
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1325814203
Short name T563
Test name
Test status
Simulation time 212104113666 ps
CPU time 3491.86 seconds
Started Jul 02 08:31:14 AM PDT 24
Finished Jul 02 09:29:26 AM PDT 24
Peak memory 290008 kb
Host smart-3d658343-6cc1-4f74-90b1-02c412ce689a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325814203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1325814203
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2200238036
Short name T7
Test name
Test status
Simulation time 158454938357 ps
CPU time 2968.24 seconds
Started Jul 02 08:34:06 AM PDT 24
Finished Jul 02 09:23:35 AM PDT 24
Peak memory 290024 kb
Host smart-f2dae808-ee33-4813-8eec-f98c67e7c214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200238036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2200238036
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.84688769
Short name T687
Test name
Test status
Simulation time 54548383813 ps
CPU time 170.25 seconds
Started Jul 02 08:34:08 AM PDT 24
Finished Jul 02 08:36:58 AM PDT 24
Peak memory 257520 kb
Host smart-000cf5da-e597-4cf4-a123-fb549bb057ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84688
769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.84688769
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3501682330
Short name T652
Test name
Test status
Simulation time 169080574 ps
CPU time 13.2 seconds
Started Jul 02 08:34:06 AM PDT 24
Finished Jul 02 08:34:19 AM PDT 24
Peak memory 249316 kb
Host smart-8be38342-48b0-496a-9216-3e57641bf664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
82330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3501682330
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3493691642
Short name T587
Test name
Test status
Simulation time 33936862724 ps
CPU time 1450.46 seconds
Started Jul 02 08:34:09 AM PDT 24
Finished Jul 02 08:58:20 AM PDT 24
Peak memory 267836 kb
Host smart-aea0c546-af7f-4c1a-a10d-ba719aa5e16e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493691642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3493691642
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1235541084
Short name T570
Test name
Test status
Simulation time 71949999502 ps
CPU time 1539.31 seconds
Started Jul 02 08:34:10 AM PDT 24
Finished Jul 02 08:59:50 AM PDT 24
Peak memory 290048 kb
Host smart-0015a1e8-5d80-4e83-a87a-e5beb0a0c73a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235541084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1235541084
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.843124266
Short name T290
Test name
Test status
Simulation time 31602870422 ps
CPU time 336.01 seconds
Started Jul 02 08:34:07 AM PDT 24
Finished Jul 02 08:39:43 AM PDT 24
Peak memory 256636 kb
Host smart-2c3aed2e-6633-4c12-af00-fa1ec49486bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843124266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.843124266
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.231311821
Short name T465
Test name
Test status
Simulation time 1841177980 ps
CPU time 29.82 seconds
Started Jul 02 08:34:02 AM PDT 24
Finished Jul 02 08:34:33 AM PDT 24
Peak memory 256744 kb
Host smart-e6bd4b84-d33c-40ff-b742-3651d20a60a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23131
1821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.231311821
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1053136106
Short name T100
Test name
Test status
Simulation time 323239323 ps
CPU time 26.37 seconds
Started Jul 02 08:34:05 AM PDT 24
Finished Jul 02 08:34:32 AM PDT 24
Peak memory 249308 kb
Host smart-a9871e50-e7e1-47b4-b0f4-29fc07317b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10531
36106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1053136106
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2303196743
Short name T248
Test name
Test status
Simulation time 3033330796 ps
CPU time 56.92 seconds
Started Jul 02 08:34:07 AM PDT 24
Finished Jul 02 08:35:04 AM PDT 24
Peak memory 249436 kb
Host smart-ee6eb3c8-0d7c-47f7-a871-f8f155ac1942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23031
96743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2303196743
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.683135549
Short name T45
Test name
Test status
Simulation time 379083176 ps
CPU time 37.42 seconds
Started Jul 02 08:34:00 AM PDT 24
Finished Jul 02 08:34:38 AM PDT 24
Peak memory 256520 kb
Host smart-87841617-c2f7-4ef5-8858-64f26554a18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68313
5549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.683135549
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3340098519
Short name T247
Test name
Test status
Simulation time 3446440359 ps
CPU time 234.19 seconds
Started Jul 02 08:34:10 AM PDT 24
Finished Jul 02 08:38:05 AM PDT 24
Peak memory 257596 kb
Host smart-e0ef1a9d-113a-4b49-be76-07c3c663ade9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340098519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3340098519
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.4290005405
Short name T101
Test name
Test status
Simulation time 191062892457 ps
CPU time 3593.6 seconds
Started Jul 02 08:34:09 AM PDT 24
Finished Jul 02 09:34:03 AM PDT 24
Peak memory 306740 kb
Host smart-1908bbea-a8bb-4d4c-8071-ce3918a2b700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290005405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.4290005405
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3075883611
Short name T668
Test name
Test status
Simulation time 10510045310 ps
CPU time 1116.43 seconds
Started Jul 02 08:34:16 AM PDT 24
Finished Jul 02 08:52:53 AM PDT 24
Peak memory 273620 kb
Host smart-14bf6b55-4ec4-4c64-8b15-d8791aa5902c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075883611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3075883611
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4093452025
Short name T446
Test name
Test status
Simulation time 783891952 ps
CPU time 56.51 seconds
Started Jul 02 08:34:14 AM PDT 24
Finished Jul 02 08:35:11 AM PDT 24
Peak memory 257452 kb
Host smart-aaa150d2-2c43-4850-853e-d81cca2c32fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40934
52025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4093452025
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2189013878
Short name T467
Test name
Test status
Simulation time 238848139 ps
CPU time 16.57 seconds
Started Jul 02 08:34:15 AM PDT 24
Finished Jul 02 08:34:32 AM PDT 24
Peak memory 249240 kb
Host smart-48936d4a-d2bc-401e-927f-755aa0d357cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21890
13878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2189013878
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.294112738
Short name T316
Test name
Test status
Simulation time 74390911472 ps
CPU time 1530.98 seconds
Started Jul 02 08:34:19 AM PDT 24
Finished Jul 02 08:59:51 AM PDT 24
Peak memory 273808 kb
Host smart-b21aa8d0-41be-4040-9dbb-65c037236d93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294112738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.294112738
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2310098328
Short name T363
Test name
Test status
Simulation time 62172205588 ps
CPU time 1182.8 seconds
Started Jul 02 08:34:19 AM PDT 24
Finished Jul 02 08:54:02 AM PDT 24
Peak memory 282200 kb
Host smart-994917e3-8e21-4af2-aa75-82566482ebf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310098328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2310098328
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3880080277
Short name T456
Test name
Test status
Simulation time 4971183956 ps
CPU time 110.03 seconds
Started Jul 02 08:34:17 AM PDT 24
Finished Jul 02 08:36:08 AM PDT 24
Peak memory 257252 kb
Host smart-288af9f1-49ea-4575-827c-52fce5359ad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880080277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3880080277
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3463166384
Short name T382
Test name
Test status
Simulation time 153199500 ps
CPU time 7.83 seconds
Started Jul 02 08:34:09 AM PDT 24
Finished Jul 02 08:34:17 AM PDT 24
Peak memory 254988 kb
Host smart-6019ecd0-7cf1-4462-a9a0-1bc22689bf7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
66384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3463166384
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2901218607
Short name T673
Test name
Test status
Simulation time 14691173136 ps
CPU time 48.07 seconds
Started Jul 02 08:34:10 AM PDT 24
Finished Jul 02 08:34:58 AM PDT 24
Peak memory 249332 kb
Host smart-989e7b9c-6906-4b17-94bf-a13dd0d760bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29012
18607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2901218607
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1384320883
Short name T533
Test name
Test status
Simulation time 629531977 ps
CPU time 37.51 seconds
Started Jul 02 08:34:14 AM PDT 24
Finished Jul 02 08:34:52 AM PDT 24
Peak memory 256224 kb
Host smart-3a0414cb-102c-4ead-8f84-328c493d4b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13843
20883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1384320883
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1531696318
Short name T365
Test name
Test status
Simulation time 997302694 ps
CPU time 62.44 seconds
Started Jul 02 08:34:09 AM PDT 24
Finished Jul 02 08:35:12 AM PDT 24
Peak memory 257464 kb
Host smart-f8d350d0-8ab7-4775-8c26-901d7b332ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
96318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1531696318
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3037237765
Short name T79
Test name
Test status
Simulation time 37626215648 ps
CPU time 1329.04 seconds
Started Jul 02 08:34:20 AM PDT 24
Finished Jul 02 08:56:30 AM PDT 24
Peak memory 290204 kb
Host smart-38c5fb0b-3301-411c-884b-0bb0688e6a54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037237765 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3037237765
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3958914811
Short name T95
Test name
Test status
Simulation time 246726313340 ps
CPU time 3103.49 seconds
Started Jul 02 08:34:23 AM PDT 24
Finished Jul 02 09:26:08 AM PDT 24
Peak memory 287288 kb
Host smart-cce4494d-481b-4da6-bac7-a765d4e6751e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958914811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3958914811
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3052480500
Short name T526
Test name
Test status
Simulation time 979529605 ps
CPU time 89.24 seconds
Started Jul 02 08:34:29 AM PDT 24
Finished Jul 02 08:36:01 AM PDT 24
Peak memory 257468 kb
Host smart-a49e3713-886e-4b99-9d1e-f4eb2ef3d895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30524
80500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3052480500
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2554964810
Short name T344
Test name
Test status
Simulation time 1165191693 ps
CPU time 44.39 seconds
Started Jul 02 08:34:23 AM PDT 24
Finished Jul 02 08:35:08 AM PDT 24
Peak memory 257400 kb
Host smart-8364325f-d6fd-40e2-812a-67a749c25969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549
64810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2554964810
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3500152897
Short name T680
Test name
Test status
Simulation time 59060915481 ps
CPU time 3195.3 seconds
Started Jul 02 08:34:27 AM PDT 24
Finished Jul 02 09:27:44 AM PDT 24
Peak memory 288704 kb
Host smart-e372b1c2-fc9f-423b-8379-cdf4a4f41d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500152897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3500152897
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3874409412
Short name T671
Test name
Test status
Simulation time 150966794218 ps
CPU time 2253.22 seconds
Started Jul 02 08:34:27 AM PDT 24
Finished Jul 02 09:12:02 AM PDT 24
Peak memory 274168 kb
Host smart-37d520a5-d76b-43c9-8079-7951215b37c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874409412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3874409412
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.855390972
Short name T76
Test name
Test status
Simulation time 779599274 ps
CPU time 27.5 seconds
Started Jul 02 08:34:17 AM PDT 24
Finished Jul 02 08:34:45 AM PDT 24
Peak memory 249304 kb
Host smart-1d5e1496-2f37-4119-aeea-9cd967653928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85539
0972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.855390972
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.127670713
Short name T697
Test name
Test status
Simulation time 96569091 ps
CPU time 8 seconds
Started Jul 02 08:34:20 AM PDT 24
Finished Jul 02 08:34:28 AM PDT 24
Peak memory 248548 kb
Host smart-4a6b93b4-0164-4954-886f-f1a4b3e4e09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
0713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.127670713
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3001121349
Short name T582
Test name
Test status
Simulation time 748276613 ps
CPU time 19.9 seconds
Started Jul 02 08:34:24 AM PDT 24
Finished Jul 02 08:34:44 AM PDT 24
Peak memory 248348 kb
Host smart-a414bdd7-afbf-42dc-9db7-a4448a853db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30011
21349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3001121349
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2324293728
Short name T638
Test name
Test status
Simulation time 405304367 ps
CPU time 11.22 seconds
Started Jul 02 08:34:20 AM PDT 24
Finished Jul 02 08:34:32 AM PDT 24
Peak memory 249244 kb
Host smart-5e59db63-5274-4735-a637-6173893ddf1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23242
93728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2324293728
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3266637871
Short name T225
Test name
Test status
Simulation time 21525906882 ps
CPU time 1211.74 seconds
Started Jul 02 08:34:30 AM PDT 24
Finished Jul 02 08:54:45 AM PDT 24
Peak memory 284272 kb
Host smart-39b5c681-3134-41c2-baa8-e5eedc278a92
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266637871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3266637871
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.746091376
Short name T478
Test name
Test status
Simulation time 11293854811 ps
CPU time 1072.72 seconds
Started Jul 02 08:34:32 AM PDT 24
Finished Jul 02 08:52:27 AM PDT 24
Peak memory 290144 kb
Host smart-80fe2eea-48d4-4b96-876b-b9670630eff7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746091376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.746091376
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.4049250393
Short name T369
Test name
Test status
Simulation time 7616539989 ps
CPU time 135.58 seconds
Started Jul 02 08:34:32 AM PDT 24
Finished Jul 02 08:36:49 AM PDT 24
Peak memory 256892 kb
Host smart-e8aa9860-7d09-41ef-85f2-636ef5764a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40492
50393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4049250393
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.841552549
Short name T414
Test name
Test status
Simulation time 5515123803 ps
CPU time 45.9 seconds
Started Jul 02 08:34:33 AM PDT 24
Finished Jul 02 08:35:20 AM PDT 24
Peak memory 257148 kb
Host smart-9a807a5d-f50b-4152-9ed2-206d3647be79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84155
2549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.841552549
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3121657032
Short name T265
Test name
Test status
Simulation time 21521508207 ps
CPU time 1666.2 seconds
Started Jul 02 08:34:36 AM PDT 24
Finished Jul 02 09:02:24 AM PDT 24
Peak memory 289832 kb
Host smart-42f1f6da-2642-4ff3-b604-2347bff2026c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121657032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3121657032
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.445781106
Short name T41
Test name
Test status
Simulation time 7624696980 ps
CPU time 835.58 seconds
Started Jul 02 08:34:36 AM PDT 24
Finished Jul 02 08:48:32 AM PDT 24
Peak memory 273860 kb
Host smart-38ce5e2a-1501-4cdb-ac7d-ec392ab6da1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445781106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.445781106
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.781939398
Short name T303
Test name
Test status
Simulation time 32265629665 ps
CPU time 358.24 seconds
Started Jul 02 08:34:36 AM PDT 24
Finished Jul 02 08:40:34 AM PDT 24
Peak memory 249088 kb
Host smart-6899a078-1a6f-4fc6-b1fe-d1150750e246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781939398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.781939398
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2462322701
Short name T480
Test name
Test status
Simulation time 475342414 ps
CPU time 45.28 seconds
Started Jul 02 08:34:32 AM PDT 24
Finished Jul 02 08:35:19 AM PDT 24
Peak memory 256792 kb
Host smart-cbdfc094-f74d-4f31-b109-63e7ead7f6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24623
22701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2462322701
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.848773462
Short name T94
Test name
Test status
Simulation time 149104883 ps
CPU time 11.09 seconds
Started Jul 02 08:34:31 AM PDT 24
Finished Jul 02 08:34:45 AM PDT 24
Peak memory 254260 kb
Host smart-48661b65-3acf-4b1b-b65e-2130dc7a19af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84877
3462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.848773462
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.62591657
Short name T605
Test name
Test status
Simulation time 1415749112 ps
CPU time 22.29 seconds
Started Jul 02 08:34:33 AM PDT 24
Finished Jul 02 08:34:57 AM PDT 24
Peak memory 257440 kb
Host smart-0d13c857-7824-4ad4-aae2-bec823f569be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62591
657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.62591657
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1185055453
Short name T65
Test name
Test status
Simulation time 82249650947 ps
CPU time 3466.57 seconds
Started Jul 02 08:34:35 AM PDT 24
Finished Jul 02 09:32:23 AM PDT 24
Peak memory 304712 kb
Host smart-5b0e0b4c-f537-43ed-9dba-c923d45a8c58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185055453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1185055453
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1895003105
Short name T676
Test name
Test status
Simulation time 19224679537 ps
CPU time 1103.66 seconds
Started Jul 02 08:34:41 AM PDT 24
Finished Jul 02 08:53:06 AM PDT 24
Peak memory 273440 kb
Host smart-3ef649d9-861f-4bde-810a-bd4937ed88af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895003105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1895003105
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.4101421422
Short name T523
Test name
Test status
Simulation time 15517642102 ps
CPU time 194.53 seconds
Started Jul 02 08:34:44 AM PDT 24
Finished Jul 02 08:37:59 AM PDT 24
Peak memory 257568 kb
Host smart-64302c9e-cae4-4859-918a-a2eb2f8ce745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41014
21422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4101421422
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1408872866
Short name T495
Test name
Test status
Simulation time 281876641 ps
CPU time 19.2 seconds
Started Jul 02 08:34:37 AM PDT 24
Finished Jul 02 08:34:58 AM PDT 24
Peak memory 248748 kb
Host smart-f0bf2f99-2096-4edf-a5f5-c6b6d2d42417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14088
72866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1408872866
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3319123822
Short name T8
Test name
Test status
Simulation time 153609623055 ps
CPU time 2397.79 seconds
Started Jul 02 08:34:44 AM PDT 24
Finished Jul 02 09:14:43 AM PDT 24
Peak memory 289852 kb
Host smart-38b4dc28-34c4-412b-86b5-c70a6ae9f3e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319123822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3319123822
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2911003883
Short name T585
Test name
Test status
Simulation time 226996779553 ps
CPU time 1167.56 seconds
Started Jul 02 08:34:42 AM PDT 24
Finished Jul 02 08:54:10 AM PDT 24
Peak memory 289200 kb
Host smart-26249baa-f1cb-4e06-a10e-3541b4d87e20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911003883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2911003883
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.750325180
Short name T298
Test name
Test status
Simulation time 40312268987 ps
CPU time 381.59 seconds
Started Jul 02 08:34:44 AM PDT 24
Finished Jul 02 08:41:06 AM PDT 24
Peak memory 256284 kb
Host smart-df5cc40d-88ad-46e1-b965-4738db8b2815
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750325180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.750325180
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.486625707
Short name T339
Test name
Test status
Simulation time 251252058 ps
CPU time 16.58 seconds
Started Jul 02 08:34:37 AM PDT 24
Finished Jul 02 08:34:55 AM PDT 24
Peak memory 249300 kb
Host smart-f324b7d0-b258-4bce-ba71-eeba2dc3feed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48662
5707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.486625707
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1193617239
Short name T386
Test name
Test status
Simulation time 599055579 ps
CPU time 16.75 seconds
Started Jul 02 08:34:36 AM PDT 24
Finished Jul 02 08:34:54 AM PDT 24
Peak memory 249300 kb
Host smart-91eacafa-a22d-4a4d-9aed-43307670d8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
17239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1193617239
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2636443980
Short name T682
Test name
Test status
Simulation time 323377174 ps
CPU time 10.09 seconds
Started Jul 02 08:34:39 AM PDT 24
Finished Jul 02 08:34:50 AM PDT 24
Peak memory 248888 kb
Host smart-d705cfcc-f1f4-4943-8fe2-4b77aededd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26364
43980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2636443980
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2811902760
Short name T361
Test name
Test status
Simulation time 411003235 ps
CPU time 12.7 seconds
Started Jul 02 08:34:37 AM PDT 24
Finished Jul 02 08:34:51 AM PDT 24
Peak memory 257172 kb
Host smart-5821db40-ce66-468c-ba21-0b737444c153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
02760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2811902760
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3770069069
Short name T109
Test name
Test status
Simulation time 32053234421 ps
CPU time 2130.46 seconds
Started Jul 02 08:34:45 AM PDT 24
Finished Jul 02 09:10:16 AM PDT 24
Peak memory 289348 kb
Host smart-4eff75e4-f256-417a-8ce7-6af7b8c8de9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770069069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3770069069
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.670758290
Short name T37
Test name
Test status
Simulation time 57435064837 ps
CPU time 936.27 seconds
Started Jul 02 08:34:44 AM PDT 24
Finished Jul 02 08:50:21 AM PDT 24
Peak memory 274084 kb
Host smart-2ad063bb-6810-47fe-8b30-50be80b818f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670758290 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.670758290
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3024484366
Short name T345
Test name
Test status
Simulation time 80425178390 ps
CPU time 2446.12 seconds
Started Jul 02 08:34:49 AM PDT 24
Finished Jul 02 09:15:37 AM PDT 24
Peak memory 284252 kb
Host smart-29f98c8c-9e6a-4e98-bdf3-e0b792ad0799
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024484366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3024484366
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.802671732
Short name T380
Test name
Test status
Simulation time 8740551102 ps
CPU time 293.03 seconds
Started Jul 02 08:34:50 AM PDT 24
Finished Jul 02 08:39:44 AM PDT 24
Peak memory 256892 kb
Host smart-bd67e995-fc10-4043-83e6-01294deebcd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80267
1732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.802671732
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1168308525
Short name T510
Test name
Test status
Simulation time 67908836 ps
CPU time 4.97 seconds
Started Jul 02 08:34:47 AM PDT 24
Finished Jul 02 08:34:53 AM PDT 24
Peak memory 240656 kb
Host smart-587aab41-79b9-48e9-a14b-0c27a47c4fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11683
08525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1168308525
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.307956840
Short name T698
Test name
Test status
Simulation time 35673494850 ps
CPU time 2214.22 seconds
Started Jul 02 08:34:50 AM PDT 24
Finished Jul 02 09:11:46 AM PDT 24
Peak memory 289760 kb
Host smart-518fa4e0-2ef4-4bb8-82e4-e3830a1057d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307956840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.307956840
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2718014067
Short name T493
Test name
Test status
Simulation time 139107124485 ps
CPU time 2196.73 seconds
Started Jul 02 08:34:52 AM PDT 24
Finished Jul 02 09:11:30 AM PDT 24
Peak memory 289600 kb
Host smart-9a2df7c7-5f01-418d-b30b-b81b38efd364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718014067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2718014067
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2778190617
Short name T670
Test name
Test status
Simulation time 15897680618 ps
CPU time 614.07 seconds
Started Jul 02 08:34:48 AM PDT 24
Finished Jul 02 08:45:03 AM PDT 24
Peak memory 249396 kb
Host smart-1df81020-765f-4acc-9312-c8505f2d38a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778190617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2778190617
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3168909201
Short name T70
Test name
Test status
Simulation time 1489816473 ps
CPU time 40.39 seconds
Started Jul 02 08:34:44 AM PDT 24
Finished Jul 02 08:35:26 AM PDT 24
Peak memory 249304 kb
Host smart-f5cd981b-5f35-4b49-b8c0-14d6b12b25d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
09201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3168909201
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1443504391
Short name T46
Test name
Test status
Simulation time 1225354972 ps
CPU time 36.52 seconds
Started Jul 02 08:34:47 AM PDT 24
Finished Jul 02 08:35:25 AM PDT 24
Peak memory 257084 kb
Host smart-d2f68483-0ab9-40bb-808f-e5772af3b6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14435
04391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1443504391
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3031000747
Short name T443
Test name
Test status
Simulation time 201864698593 ps
CPU time 2935.9 seconds
Started Jul 02 08:34:53 AM PDT 24
Finished Jul 02 09:23:51 AM PDT 24
Peak memory 290140 kb
Host smart-adc7a5c9-9ae7-451f-8cb6-49254737b76d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031000747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3031000747
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3733505203
Short name T579
Test name
Test status
Simulation time 8352856407 ps
CPU time 122.16 seconds
Started Jul 02 08:34:56 AM PDT 24
Finished Jul 02 08:36:59 AM PDT 24
Peak memory 256720 kb
Host smart-f91ef50d-8f31-4300-ae56-e50514437ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37335
05203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3733505203
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2443144704
Short name T419
Test name
Test status
Simulation time 923598030 ps
CPU time 28.04 seconds
Started Jul 02 08:34:57 AM PDT 24
Finished Jul 02 08:35:25 AM PDT 24
Peak memory 249692 kb
Host smart-ba60b792-30a1-4d4f-9835-73288bebc5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24431
44704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2443144704
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2476127800
Short name T93
Test name
Test status
Simulation time 30835897158 ps
CPU time 1995.63 seconds
Started Jul 02 08:35:15 AM PDT 24
Finished Jul 02 09:08:32 AM PDT 24
Peak memory 289492 kb
Host smart-af70f5ae-aa3d-42cf-9c8d-8852152e0778
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476127800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2476127800
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2535958899
Short name T503
Test name
Test status
Simulation time 6166530958 ps
CPU time 59.92 seconds
Started Jul 02 08:34:52 AM PDT 24
Finished Jul 02 08:35:53 AM PDT 24
Peak memory 257248 kb
Host smart-8fcf0949-0b3d-40be-b2a8-d21f585fc2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25359
58899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2535958899
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1678230139
Short name T517
Test name
Test status
Simulation time 3529155664 ps
CPU time 50.1 seconds
Started Jul 02 08:34:59 AM PDT 24
Finished Jul 02 08:35:50 AM PDT 24
Peak memory 249392 kb
Host smart-27cb2609-d5a2-4bda-acb6-8b8102e94af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
30139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1678230139
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1413160587
Short name T664
Test name
Test status
Simulation time 2268179258 ps
CPU time 34.4 seconds
Started Jul 02 08:35:01 AM PDT 24
Finished Jul 02 08:35:37 AM PDT 24
Peak memory 257540 kb
Host smart-1a4c942e-8ecc-4ba8-85cc-9cc14effa9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14131
60587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1413160587
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.608037037
Short name T353
Test name
Test status
Simulation time 144294751 ps
CPU time 9.47 seconds
Started Jul 02 08:34:54 AM PDT 24
Finished Jul 02 08:35:05 AM PDT 24
Peak memory 252332 kb
Host smart-3de122db-33de-4154-b171-7b97d7a39735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60803
7037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.608037037
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3913055357
Short name T379
Test name
Test status
Simulation time 24104949 ps
CPU time 3.77 seconds
Started Jul 02 08:35:15 AM PDT 24
Finished Jul 02 08:35:20 AM PDT 24
Peak memory 251036 kb
Host smart-844bf22a-9bd3-4ee1-b8a8-e379de251ad5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913055357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3913055357
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3699932736
Short name T672
Test name
Test status
Simulation time 28515414501 ps
CPU time 1677.07 seconds
Started Jul 02 08:35:15 AM PDT 24
Finished Jul 02 09:03:13 AM PDT 24
Peak memory 283760 kb
Host smart-5c399168-212b-4d73-822c-d0198949a5d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699932736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3699932736
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.167694563
Short name T227
Test name
Test status
Simulation time 400698511 ps
CPU time 26.18 seconds
Started Jul 02 08:35:06 AM PDT 24
Finished Jul 02 08:35:33 AM PDT 24
Peak memory 256976 kb
Host smart-2f3a6616-740c-4847-afca-d0129affbc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
4563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.167694563
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2604660693
Short name T3
Test name
Test status
Simulation time 150325009 ps
CPU time 11.24 seconds
Started Jul 02 08:35:15 AM PDT 24
Finished Jul 02 08:35:27 AM PDT 24
Peak memory 256528 kb
Host smart-6da66bde-3af6-43eb-94fe-14fdf85c828e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26046
60693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2604660693
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1433408485
Short name T606
Test name
Test status
Simulation time 113228591141 ps
CPU time 1755.36 seconds
Started Jul 02 08:35:15 AM PDT 24
Finished Jul 02 09:04:32 AM PDT 24
Peak memory 273912 kb
Host smart-85e6f56c-5a65-4fff-8898-fd686b2e450f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433408485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1433408485
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2005004689
Short name T231
Test name
Test status
Simulation time 207400854874 ps
CPU time 2243.89 seconds
Started Jul 02 08:35:14 AM PDT 24
Finished Jul 02 09:12:39 AM PDT 24
Peak memory 282176 kb
Host smart-b21ffa05-489c-4262-85fc-0ca7b4fd46e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005004689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2005004689
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.476928167
Short name T302
Test name
Test status
Simulation time 7910848919 ps
CPU time 84.63 seconds
Started Jul 02 08:35:14 AM PDT 24
Finished Jul 02 08:36:40 AM PDT 24
Peak memory 248200 kb
Host smart-f5f0eac2-35dd-4fba-a4c2-75afa56b2f90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476928167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.476928167
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2474503319
Short name T692
Test name
Test status
Simulation time 1658535737 ps
CPU time 39.06 seconds
Started Jul 02 08:35:15 AM PDT 24
Finished Jul 02 08:35:55 AM PDT 24
Peak memory 249288 kb
Host smart-ce9a517c-a8f1-48a1-bc9a-0fe2c4cf957c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
03319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2474503319
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4207670411
Short name T458
Test name
Test status
Simulation time 1371054704 ps
CPU time 20.39 seconds
Started Jul 02 08:35:13 AM PDT 24
Finished Jul 02 08:35:34 AM PDT 24
Peak memory 256720 kb
Host smart-fbdec85b-8e7e-4843-a59e-361b474e1544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42076
70411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4207670411
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.327538854
Short name T60
Test name
Test status
Simulation time 3823009295 ps
CPU time 64.39 seconds
Started Jul 02 08:35:05 AM PDT 24
Finished Jul 02 08:36:10 AM PDT 24
Peak memory 249404 kb
Host smart-02813aba-cdb6-4dc5-bc18-75c3f82a37c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753
8854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.327538854
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2471481670
Short name T522
Test name
Test status
Simulation time 1460133251 ps
CPU time 44.95 seconds
Started Jul 02 08:35:14 AM PDT 24
Finished Jul 02 08:36:00 AM PDT 24
Peak memory 257316 kb
Host smart-454fcf81-45db-4425-b694-89037f3872cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24714
81670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2471481670
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1159661161
Short name T621
Test name
Test status
Simulation time 14223882915 ps
CPU time 1174.94 seconds
Started Jul 02 08:35:20 AM PDT 24
Finished Jul 02 08:54:56 AM PDT 24
Peak memory 285020 kb
Host smart-15eb7d4a-2ee7-44ce-b1ed-6a8798d54f9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159661161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1159661161
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4271458065
Short name T659
Test name
Test status
Simulation time 3076285058 ps
CPU time 194.36 seconds
Started Jul 02 08:35:20 AM PDT 24
Finished Jul 02 08:38:35 AM PDT 24
Peak memory 256748 kb
Host smart-ffde1803-7902-4079-b793-d410c52931e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
58065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4271458065
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1493694371
Short name T637
Test name
Test status
Simulation time 990977314 ps
CPU time 40.38 seconds
Started Jul 02 08:35:23 AM PDT 24
Finished Jul 02 08:36:04 AM PDT 24
Peak memory 249228 kb
Host smart-4bc2432a-207b-4b9a-9bbf-55c733b33885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14936
94371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1493694371
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2068347225
Short name T524
Test name
Test status
Simulation time 28888537922 ps
CPU time 609.65 seconds
Started Jul 02 08:35:27 AM PDT 24
Finished Jul 02 08:45:38 AM PDT 24
Peak memory 273892 kb
Host smart-e2d5adb3-9374-427b-abb1-f5124095d53e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068347225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2068347225
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.219095587
Short name T622
Test name
Test status
Simulation time 17992638663 ps
CPU time 808.12 seconds
Started Jul 02 08:35:23 AM PDT 24
Finished Jul 02 08:48:52 AM PDT 24
Peak memory 273516 kb
Host smart-37249c2d-39fc-41e4-87d1-371e55a2ab0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219095587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.219095587
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2718557205
Short name T603
Test name
Test status
Simulation time 11650694246 ps
CPU time 508.22 seconds
Started Jul 02 08:35:26 AM PDT 24
Finished Jul 02 08:43:55 AM PDT 24
Peak memory 249344 kb
Host smart-8d59d357-a7db-4086-b78b-d5a98949c812
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718557205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2718557205
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2693188629
Short name T527
Test name
Test status
Simulation time 805371824 ps
CPU time 62.75 seconds
Started Jul 02 08:35:16 AM PDT 24
Finished Jul 02 08:36:19 AM PDT 24
Peak memory 256744 kb
Host smart-d63fddbc-b3ce-4b88-b3f7-3b062b287f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
88629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2693188629
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2027899000
Short name T641
Test name
Test status
Simulation time 837939470 ps
CPU time 51.85 seconds
Started Jul 02 08:35:19 AM PDT 24
Finished Jul 02 08:36:11 AM PDT 24
Peak memory 256932 kb
Host smart-8f70d221-198b-405b-9ed2-c56b20e0b4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20278
99000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2027899000
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1456951372
Short name T48
Test name
Test status
Simulation time 1627757913 ps
CPU time 29.78 seconds
Started Jul 02 08:35:20 AM PDT 24
Finished Jul 02 08:35:51 AM PDT 24
Peak memory 256932 kb
Host smart-50120a9e-a395-4a0b-937e-50314a1a6ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14569
51372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1456951372
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2975915916
Short name T17
Test name
Test status
Simulation time 1682511158 ps
CPU time 26.05 seconds
Started Jul 02 08:35:16 AM PDT 24
Finished Jul 02 08:35:43 AM PDT 24
Peak memory 256980 kb
Host smart-d38463b6-30c2-47d1-9b27-1986954bd467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29759
15916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2975915916
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3715957206
Short name T51
Test name
Test status
Simulation time 9866286615 ps
CPU time 1192.86 seconds
Started Jul 02 08:35:28 AM PDT 24
Finished Jul 02 08:55:22 AM PDT 24
Peak memory 289692 kb
Host smart-f444a2bd-c315-420f-8ff4-37a0dbcc9c79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715957206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3715957206
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2948239763
Short name T255
Test name
Test status
Simulation time 78497011350 ps
CPU time 7550.11 seconds
Started Jul 02 08:35:26 AM PDT 24
Finished Jul 02 10:41:18 AM PDT 24
Peak memory 363644 kb
Host smart-e565895d-d132-45a6-a70e-91fe39e983f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948239763 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2948239763
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4019823748
Short name T209
Test name
Test status
Simulation time 41553886853 ps
CPU time 2418.12 seconds
Started Jul 02 08:35:31 AM PDT 24
Finished Jul 02 09:15:50 AM PDT 24
Peak memory 284024 kb
Host smart-f217acdd-7573-4d3d-a30e-d89573fea568
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019823748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4019823748
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.33463690
Short name T20
Test name
Test status
Simulation time 3912749409 ps
CPU time 113.68 seconds
Started Jul 02 08:35:31 AM PDT 24
Finished Jul 02 08:37:25 AM PDT 24
Peak memory 256716 kb
Host smart-a7d341f2-2ea0-4284-a2d2-1cd90fc7d606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.33463690
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1770233784
Short name T683
Test name
Test status
Simulation time 3004097717 ps
CPU time 49.88 seconds
Started Jul 02 08:35:31 AM PDT 24
Finished Jul 02 08:36:22 AM PDT 24
Peak memory 257640 kb
Host smart-726463ca-3e01-443d-bac2-df5cc5123b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17702
33784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1770233784
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2138926759
Short name T596
Test name
Test status
Simulation time 57045490130 ps
CPU time 1462 seconds
Started Jul 02 08:35:31 AM PDT 24
Finished Jul 02 08:59:55 AM PDT 24
Peak memory 289568 kb
Host smart-5f51594a-7acd-4172-a0d1-86b57a049767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138926759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2138926759
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1403292676
Short name T40
Test name
Test status
Simulation time 13336698104 ps
CPU time 500.78 seconds
Started Jul 02 08:35:30 AM PDT 24
Finished Jul 02 08:43:52 AM PDT 24
Peak memory 256220 kb
Host smart-039966c6-cb49-4faa-ad8f-35797b25cdee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403292676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1403292676
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.67841074
Short name T484
Test name
Test status
Simulation time 2056385411 ps
CPU time 34.22 seconds
Started Jul 02 08:35:25 AM PDT 24
Finished Jul 02 08:36:00 AM PDT 24
Peak memory 249232 kb
Host smart-03f6f5ff-f943-4f94-93fa-0e21be80a4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67841
074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.67841074
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2781403814
Short name T226
Test name
Test status
Simulation time 1506509567 ps
CPU time 27.45 seconds
Started Jul 02 08:35:25 AM PDT 24
Finished Jul 02 08:35:53 AM PDT 24
Peak memory 248572 kb
Host smart-6efc122d-9ed4-4dc5-b654-d4cabfaa69a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27814
03814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2781403814
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1270923223
Short name T347
Test name
Test status
Simulation time 326857861 ps
CPU time 21.56 seconds
Started Jul 02 08:35:31 AM PDT 24
Finished Jul 02 08:35:54 AM PDT 24
Peak memory 256980 kb
Host smart-e35707d9-8e97-4a96-a54d-5eb1794e9e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12709
23223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1270923223
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.629504892
Short name T497
Test name
Test status
Simulation time 476777177 ps
CPU time 36.27 seconds
Started Jul 02 08:35:26 AM PDT 24
Finished Jul 02 08:36:03 AM PDT 24
Peak memory 257400 kb
Host smart-ef1dac40-c50f-4b26-854a-41d5bcbee8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62950
4892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.629504892
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1665307656
Short name T367
Test name
Test status
Simulation time 161868565047 ps
CPU time 4584.05 seconds
Started Jul 02 08:35:30 AM PDT 24
Finished Jul 02 09:51:56 AM PDT 24
Peak memory 305816 kb
Host smart-229feaa3-a471-4266-b6b3-8ac86c4b8cf9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665307656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1665307656
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2915764379
Short name T261
Test name
Test status
Simulation time 129465857148 ps
CPU time 4213.92 seconds
Started Jul 02 08:35:31 AM PDT 24
Finished Jul 02 09:45:47 AM PDT 24
Peak memory 306748 kb
Host smart-3cfdfdf2-9127-436e-ad18-4b6cc7054a43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915764379 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2915764379
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3742787856
Short name T198
Test name
Test status
Simulation time 66717547 ps
CPU time 2.72 seconds
Started Jul 02 08:31:15 AM PDT 24
Finished Jul 02 08:31:19 AM PDT 24
Peak memory 249612 kb
Host smart-5c80d0dd-bc98-4c23-b007-2a8bb3a3111c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3742787856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3742787856
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3032130944
Short name T71
Test name
Test status
Simulation time 97403816451 ps
CPU time 2845.58 seconds
Started Jul 02 08:31:17 AM PDT 24
Finished Jul 02 09:18:44 AM PDT 24
Peak memory 289108 kb
Host smart-cd4d8848-a7a7-4081-bdf9-bcf51642c7e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032130944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3032130944
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3816402187
Short name T407
Test name
Test status
Simulation time 220524626 ps
CPU time 11.93 seconds
Started Jul 02 08:31:17 AM PDT 24
Finished Jul 02 08:31:30 AM PDT 24
Peak memory 249332 kb
Host smart-18c6f7c2-d959-408b-9500-1e15cd4b3810
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3816402187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3816402187
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3876315094
Short name T601
Test name
Test status
Simulation time 4249371201 ps
CPU time 59.45 seconds
Started Jul 02 08:31:19 AM PDT 24
Finished Jul 02 08:32:19 AM PDT 24
Peak memory 256932 kb
Host smart-135731c2-ef2b-4745-8d23-3e92ce2703f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
15094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3876315094
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3792127852
Short name T558
Test name
Test status
Simulation time 451592111 ps
CPU time 30.21 seconds
Started Jul 02 08:31:25 AM PDT 24
Finished Jul 02 08:31:56 AM PDT 24
Peak memory 248892 kb
Host smart-c127a495-1baa-4dc0-968c-6be638d6ccde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37921
27852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3792127852
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1243749565
Short name T438
Test name
Test status
Simulation time 127004575274 ps
CPU time 1917.17 seconds
Started Jul 02 08:31:16 AM PDT 24
Finished Jul 02 09:03:14 AM PDT 24
Peak memory 282136 kb
Host smart-b17af6f2-82e5-4dc9-9b01-1d15eebb8701
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243749565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1243749565
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3718033419
Short name T691
Test name
Test status
Simulation time 13585230068 ps
CPU time 532.31 seconds
Started Jul 02 08:31:17 AM PDT 24
Finished Jul 02 08:40:10 AM PDT 24
Peak memory 249388 kb
Host smart-4124a4e5-3386-466d-bf89-d3a1f3eef3cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718033419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3718033419
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1228256031
Short name T654
Test name
Test status
Simulation time 8760309322 ps
CPU time 27.66 seconds
Started Jul 02 08:31:13 AM PDT 24
Finished Jul 02 08:31:41 AM PDT 24
Peak memory 257104 kb
Host smart-30934cde-9d8d-4fcf-a3fc-204f87cd1940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282
56031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1228256031
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.160029463
Short name T358
Test name
Test status
Simulation time 2218816728 ps
CPU time 33.12 seconds
Started Jul 02 08:31:24 AM PDT 24
Finished Jul 02 08:31:58 AM PDT 24
Peak memory 256888 kb
Host smart-10f749d3-663a-4c08-a4f6-5c382c450051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16002
9463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.160029463
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3279474391
Short name T12
Test name
Test status
Simulation time 4355099426 ps
CPU time 163.75 seconds
Started Jul 02 08:31:26 AM PDT 24
Finished Jul 02 08:34:10 AM PDT 24
Peak memory 270548 kb
Host smart-d23e05bb-37b0-479b-a3a8-fc243bb667fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3279474391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3279474391
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3654386288
Short name T542
Test name
Test status
Simulation time 1586116299 ps
CPU time 28.62 seconds
Started Jul 02 08:31:17 AM PDT 24
Finished Jul 02 08:31:46 AM PDT 24
Peak memory 256572 kb
Host smart-92cabbda-80e5-4fac-b0a4-9dbb79c94c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36543
86288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3654386288
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3750367848
Short name T398
Test name
Test status
Simulation time 1050393453 ps
CPU time 59.65 seconds
Started Jul 02 08:31:25 AM PDT 24
Finished Jul 02 08:32:25 AM PDT 24
Peak memory 257356 kb
Host smart-0b9be71e-0dcc-4027-9943-a51050c2b2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37503
67848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3750367848
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.851482776
Short name T55
Test name
Test status
Simulation time 46820754858 ps
CPU time 2675.51 seconds
Started Jul 02 08:31:25 AM PDT 24
Finished Jul 02 09:16:02 AM PDT 24
Peak memory 298544 kb
Host smart-a9709060-2129-44f6-ac9c-86ba430f64eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851482776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.851482776
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1485131441
Short name T629
Test name
Test status
Simulation time 25150611832 ps
CPU time 1328.77 seconds
Started Jul 02 08:35:42 AM PDT 24
Finished Jul 02 08:57:52 AM PDT 24
Peak memory 289436 kb
Host smart-4f28aa2a-8f66-403e-bc6a-c9c859cc826c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485131441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1485131441
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2520258723
Short name T401
Test name
Test status
Simulation time 14352756270 ps
CPU time 243.96 seconds
Started Jul 02 08:35:42 AM PDT 24
Finished Jul 02 08:39:47 AM PDT 24
Peak memory 257116 kb
Host smart-a4af33d9-24f3-42bc-8c97-9b57f5782abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25202
58723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2520258723
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4086257022
Short name T229
Test name
Test status
Simulation time 1538660496 ps
CPU time 23.46 seconds
Started Jul 02 08:35:43 AM PDT 24
Finished Jul 02 08:36:07 AM PDT 24
Peak memory 249024 kb
Host smart-cb95bd78-3f54-45e1-986e-dde756f62545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
57022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4086257022
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1228917615
Short name T282
Test name
Test status
Simulation time 70857732232 ps
CPU time 1452.74 seconds
Started Jul 02 08:35:42 AM PDT 24
Finished Jul 02 08:59:55 AM PDT 24
Peak memory 290520 kb
Host smart-58a5a555-7677-4ea3-b284-b80adc63f2bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228917615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1228917615
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3841902131
Short name T481
Test name
Test status
Simulation time 65162425925 ps
CPU time 1704.46 seconds
Started Jul 02 08:35:42 AM PDT 24
Finished Jul 02 09:04:08 AM PDT 24
Peak memory 290040 kb
Host smart-4e8a89e2-3060-4d1a-8d61-9d8791191338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841902131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3841902131
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1856986834
Short name T403
Test name
Test status
Simulation time 9368140442 ps
CPU time 380.24 seconds
Started Jul 02 08:35:42 AM PDT 24
Finished Jul 02 08:42:03 AM PDT 24
Peak memory 255796 kb
Host smart-b5268b80-84af-4e64-9e9e-82e823eff869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856986834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1856986834
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3461511216
Short name T266
Test name
Test status
Simulation time 761878739 ps
CPU time 15.84 seconds
Started Jul 02 08:35:36 AM PDT 24
Finished Jul 02 08:35:52 AM PDT 24
Peak memory 249272 kb
Host smart-8c51dfbf-f5f3-4497-acd6-f58d0d16aa55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34615
11216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3461511216
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3018222735
Short name T504
Test name
Test status
Simulation time 346830311 ps
CPU time 35.04 seconds
Started Jul 02 08:35:44 AM PDT 24
Finished Jul 02 08:36:20 AM PDT 24
Peak memory 249244 kb
Host smart-190c6f18-c844-4b24-b98e-8e641e568bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30182
22735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3018222735
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1554079523
Short name T546
Test name
Test status
Simulation time 829120148 ps
CPU time 6.3 seconds
Started Jul 02 08:35:42 AM PDT 24
Finished Jul 02 08:35:49 AM PDT 24
Peak memory 248768 kb
Host smart-3bc099f1-933b-4cdc-8078-1036179e3617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15540
79523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1554079523
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4012280974
Short name T511
Test name
Test status
Simulation time 149862490 ps
CPU time 10.4 seconds
Started Jul 02 08:35:30 AM PDT 24
Finished Jul 02 08:35:42 AM PDT 24
Peak memory 254880 kb
Host smart-2e0ef4f7-3f29-4aeb-94a0-bf0e33a1ad0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
80974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4012280974
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3798401300
Short name T448
Test name
Test status
Simulation time 81730433939 ps
CPU time 666.97 seconds
Started Jul 02 08:35:49 AM PDT 24
Finished Jul 02 08:46:56 AM PDT 24
Peak memory 257636 kb
Host smart-03a78692-8f45-4f39-99ec-7ad33fd233e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798401300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3798401300
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3987122864
Short name T441
Test name
Test status
Simulation time 24617868530 ps
CPU time 1572.71 seconds
Started Jul 02 08:35:54 AM PDT 24
Finished Jul 02 09:02:08 AM PDT 24
Peak memory 273988 kb
Host smart-2d887af1-f0d9-43bd-9958-7e5f41a39989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987122864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3987122864
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1178209213
Short name T222
Test name
Test status
Simulation time 3429772337 ps
CPU time 116.68 seconds
Started Jul 02 08:35:51 AM PDT 24
Finished Jul 02 08:37:48 AM PDT 24
Peak memory 257012 kb
Host smart-9da6b715-ea77-4c7b-8011-47ca8c653fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11782
09213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1178209213
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2502589689
Short name T112
Test name
Test status
Simulation time 3105340756 ps
CPU time 51.06 seconds
Started Jul 02 08:35:46 AM PDT 24
Finished Jul 02 08:36:37 AM PDT 24
Peak memory 257596 kb
Host smart-9dbc507a-28d4-4080-83b8-d049a18e2dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
89689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2502589689
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.874307817
Short name T634
Test name
Test status
Simulation time 108007152160 ps
CPU time 1261.89 seconds
Started Jul 02 08:35:55 AM PDT 24
Finished Jul 02 08:56:58 AM PDT 24
Peak memory 289376 kb
Host smart-cf8d76d6-cb6e-4d43-84f0-4dbfda98796f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874307817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.874307817
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3799194582
Short name T10
Test name
Test status
Simulation time 5961976062 ps
CPU time 239.13 seconds
Started Jul 02 08:35:54 AM PDT 24
Finished Jul 02 08:39:54 AM PDT 24
Peak memory 249396 kb
Host smart-4062ec3e-6fc1-4ba0-ba12-ae5cc9374262
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799194582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3799194582
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3256222950
Short name T359
Test name
Test status
Simulation time 3593287972 ps
CPU time 19.57 seconds
Started Jul 02 08:35:46 AM PDT 24
Finished Jul 02 08:36:06 AM PDT 24
Peak memory 249360 kb
Host smart-dec49fb5-9a84-455c-804f-5176495b54f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32562
22950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3256222950
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.715977879
Short name T28
Test name
Test status
Simulation time 408688479 ps
CPU time 14.68 seconds
Started Jul 02 08:35:46 AM PDT 24
Finished Jul 02 08:36:01 AM PDT 24
Peak memory 255240 kb
Host smart-3f6861ba-5913-44c8-88f7-05337b75fc84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71597
7879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.715977879
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2047127797
Short name T608
Test name
Test status
Simulation time 832015505 ps
CPU time 27.88 seconds
Started Jul 02 08:35:53 AM PDT 24
Finished Jul 02 08:36:22 AM PDT 24
Peak memory 249044 kb
Host smart-b1129dde-465d-4774-8cf1-494a2c9f1dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20471
27797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2047127797
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1052680613
Short name T549
Test name
Test status
Simulation time 239564468 ps
CPU time 23.17 seconds
Started Jul 02 08:35:46 AM PDT 24
Finished Jul 02 08:36:10 AM PDT 24
Peak memory 257340 kb
Host smart-ef5b54a8-3927-46cf-b6be-495f7f3813f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
80613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1052680613
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1434137778
Short name T427
Test name
Test status
Simulation time 123483723378 ps
CPU time 2696.28 seconds
Started Jul 02 08:35:53 AM PDT 24
Finished Jul 02 09:20:50 AM PDT 24
Peak memory 290408 kb
Host smart-8958d16c-e145-499e-9322-8937de1eaaf0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434137778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1434137778
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4223789927
Short name T590
Test name
Test status
Simulation time 10125694586 ps
CPU time 1026.11 seconds
Started Jul 02 08:36:06 AM PDT 24
Finished Jul 02 08:53:13 AM PDT 24
Peak memory 290140 kb
Host smart-2a6ad4c8-c9d9-47d2-8c7c-86c8d4e7a3c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223789927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4223789927
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2045620854
Short name T417
Test name
Test status
Simulation time 147715827 ps
CPU time 12.14 seconds
Started Jul 02 08:36:04 AM PDT 24
Finished Jul 02 08:36:17 AM PDT 24
Peak memory 248824 kb
Host smart-f025e0da-c0d0-4ba3-b110-895aaa147307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20456
20854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2045620854
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3216039135
Short name T269
Test name
Test status
Simulation time 4542038775 ps
CPU time 59.7 seconds
Started Jul 02 08:36:05 AM PDT 24
Finished Jul 02 08:37:06 AM PDT 24
Peak memory 249388 kb
Host smart-452772cb-8307-4abd-acdb-f916a9b0414c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32160
39135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3216039135
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2248408227
Short name T307
Test name
Test status
Simulation time 41848629709 ps
CPU time 2500.19 seconds
Started Jul 02 08:36:09 AM PDT 24
Finished Jul 02 09:17:51 AM PDT 24
Peak memory 273888 kb
Host smart-fbd48158-d1e9-4a46-bd4c-3c542ad06404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248408227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2248408227
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.93612830
Short name T33
Test name
Test status
Simulation time 142316718946 ps
CPU time 2393.17 seconds
Started Jul 02 08:36:08 AM PDT 24
Finished Jul 02 09:16:02 AM PDT 24
Peak memory 290120 kb
Host smart-6ec56396-0c69-4eab-9d1e-3379e6f52ec9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93612830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.93612830
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.453040549
Short name T297
Test name
Test status
Simulation time 43531967951 ps
CPU time 462.21 seconds
Started Jul 02 08:36:05 AM PDT 24
Finished Jul 02 08:43:48 AM PDT 24
Peak memory 248384 kb
Host smart-28cf2df0-bdc4-4382-9523-99ce32449b50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453040549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.453040549
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3795316326
Short name T395
Test name
Test status
Simulation time 374334903 ps
CPU time 28.66 seconds
Started Jul 02 08:36:05 AM PDT 24
Finished Jul 02 08:36:34 AM PDT 24
Peak memory 256552 kb
Host smart-6af0c1d1-7144-446f-b07a-3c746b48c648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37953
16326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3795316326
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.904006566
Short name T450
Test name
Test status
Simulation time 243867421 ps
CPU time 23.15 seconds
Started Jul 02 08:36:05 AM PDT 24
Finished Jul 02 08:36:29 AM PDT 24
Peak memory 249272 kb
Host smart-b586f41a-3901-41cb-9818-7af60a746802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90400
6566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.904006566
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3730886084
Short name T488
Test name
Test status
Simulation time 901610847 ps
CPU time 29.4 seconds
Started Jul 02 08:36:05 AM PDT 24
Finished Jul 02 08:36:35 AM PDT 24
Peak memory 248980 kb
Host smart-e937ffdd-56b3-4223-a985-8fbb598afc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37308
86084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3730886084
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1731049290
Short name T501
Test name
Test status
Simulation time 222425727 ps
CPU time 20.2 seconds
Started Jul 02 08:36:00 AM PDT 24
Finished Jul 02 08:36:21 AM PDT 24
Peak memory 249264 kb
Host smart-70fb63a1-6355-46e0-a420-4d2d3f5b6ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17310
49290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1731049290
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3927497586
Short name T528
Test name
Test status
Simulation time 108404265592 ps
CPU time 892.74 seconds
Started Jul 02 08:36:11 AM PDT 24
Finished Jul 02 08:51:05 AM PDT 24
Peak memory 265808 kb
Host smart-f92af441-bf1d-448a-a24f-00e4d2c617f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927497586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3927497586
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3379369709
Short name T625
Test name
Test status
Simulation time 68915569715 ps
CPU time 1211.1 seconds
Started Jul 02 08:36:18 AM PDT 24
Finished Jul 02 08:56:30 AM PDT 24
Peak memory 272892 kb
Host smart-bb8270a1-9df1-4fe7-abe1-ddf6d6409097
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379369709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3379369709
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3935765289
Short name T352
Test name
Test status
Simulation time 3460058621 ps
CPU time 81.89 seconds
Started Jul 02 08:36:17 AM PDT 24
Finished Jul 02 08:37:40 AM PDT 24
Peak memory 257520 kb
Host smart-cb0bc5f0-0201-41c1-b272-2c0e2104fb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39357
65289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3935765289
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.16424192
Short name T305
Test name
Test status
Simulation time 53008618043 ps
CPU time 1372.84 seconds
Started Jul 02 08:36:19 AM PDT 24
Finished Jul 02 08:59:13 AM PDT 24
Peak memory 286664 kb
Host smart-26342a39-a8c7-4819-9fc2-14e214aad91c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16424192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.16424192
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.26993607
Short name T285
Test name
Test status
Simulation time 10888446265 ps
CPU time 433.29 seconds
Started Jul 02 08:36:21 AM PDT 24
Finished Jul 02 08:43:35 AM PDT 24
Peak memory 248672 kb
Host smart-747837b9-e7ae-450f-b8f3-fb2673e5027a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26993607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.26993607
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3823400212
Short name T647
Test name
Test status
Simulation time 619722565 ps
CPU time 34.92 seconds
Started Jul 02 08:36:12 AM PDT 24
Finished Jul 02 08:36:48 AM PDT 24
Peak memory 256568 kb
Host smart-098af31c-3d8a-40f8-8787-7ecb11f65509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38234
00212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3823400212
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.370699459
Short name T96
Test name
Test status
Simulation time 561676481 ps
CPU time 34.1 seconds
Started Jul 02 08:36:16 AM PDT 24
Finished Jul 02 08:36:51 AM PDT 24
Peak memory 249216 kb
Host smart-0a5a7180-9544-4dc5-840c-8af32d0ca0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37069
9459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.370699459
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2379014851
Short name T422
Test name
Test status
Simulation time 657388345 ps
CPU time 39.64 seconds
Started Jul 02 08:36:12 AM PDT 24
Finished Jul 02 08:36:53 AM PDT 24
Peak memory 256800 kb
Host smart-731e8eba-6058-4c36-ba14-2cee30477e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
14851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2379014851
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1318341941
Short name T508
Test name
Test status
Simulation time 12027146191 ps
CPU time 907.35 seconds
Started Jul 02 08:36:26 AM PDT 24
Finished Jul 02 08:51:34 AM PDT 24
Peak memory 271844 kb
Host smart-2234c96f-06dc-46b2-8071-9cea83bb849f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318341941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1318341941
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1834045383
Short name T2
Test name
Test status
Simulation time 5282042231 ps
CPU time 296.98 seconds
Started Jul 02 08:36:24 AM PDT 24
Finished Jul 02 08:41:22 AM PDT 24
Peak memory 257600 kb
Host smart-00041ec2-c13b-4720-b070-011124a3b9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
45383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1834045383
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3362623522
Short name T532
Test name
Test status
Simulation time 600301078 ps
CPU time 15.42 seconds
Started Jul 02 08:36:27 AM PDT 24
Finished Jul 02 08:36:44 AM PDT 24
Peak memory 248748 kb
Host smart-d765c3fb-9d95-4e00-9c22-3559c9b2b05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33626
23522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3362623522
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1432706660
Short name T560
Test name
Test status
Simulation time 11685614900 ps
CPU time 1227.71 seconds
Started Jul 02 08:36:30 AM PDT 24
Finished Jul 02 08:56:59 AM PDT 24
Peak memory 287244 kb
Host smart-a873fad4-efd7-47f5-a7e8-c2b1276478fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432706660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1432706660
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.591965092
Short name T413
Test name
Test status
Simulation time 452550605452 ps
CPU time 2708.13 seconds
Started Jul 02 08:36:30 AM PDT 24
Finished Jul 02 09:21:40 AM PDT 24
Peak memory 290092 kb
Host smart-bd89b3d9-df40-4921-abf0-2f815951490e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591965092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.591965092
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3566671222
Short name T284
Test name
Test status
Simulation time 12605653919 ps
CPU time 531.61 seconds
Started Jul 02 08:36:29 AM PDT 24
Finished Jul 02 08:45:23 AM PDT 24
Peak memory 249380 kb
Host smart-eccf4625-9355-46e8-9d33-bb5404177db9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566671222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3566671222
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1275693284
Short name T342
Test name
Test status
Simulation time 466991781 ps
CPU time 11.3 seconds
Started Jul 02 08:36:27 AM PDT 24
Finished Jul 02 08:36:39 AM PDT 24
Peak memory 249208 kb
Host smart-0f09dadc-f00c-482b-b0c7-376bbb95a5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12756
93284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1275693284
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2150471332
Short name T449
Test name
Test status
Simulation time 190119756 ps
CPU time 17.22 seconds
Started Jul 02 08:36:25 AM PDT 24
Finished Jul 02 08:36:43 AM PDT 24
Peak memory 257004 kb
Host smart-58d68de2-9db2-4ea3-a473-922b9b2e9e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21504
71332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2150471332
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.338512737
Short name T623
Test name
Test status
Simulation time 183464418 ps
CPU time 15.23 seconds
Started Jul 02 08:36:26 AM PDT 24
Finished Jul 02 08:36:42 AM PDT 24
Peak memory 256900 kb
Host smart-740c6a88-f577-4d37-9922-e70fc7b27aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33851
2737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.338512737
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2072380403
Short name T102
Test name
Test status
Simulation time 1933969289 ps
CPU time 68.87 seconds
Started Jul 02 08:36:24 AM PDT 24
Finished Jul 02 08:37:34 AM PDT 24
Peak memory 257388 kb
Host smart-ca390a2d-fbb7-4a26-a638-d86708d31645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20723
80403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2072380403
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3620003561
Short name T645
Test name
Test status
Simulation time 21287195130 ps
CPU time 2251.99 seconds
Started Jul 02 08:36:29 AM PDT 24
Finished Jul 02 09:14:03 AM PDT 24
Peak memory 306416 kb
Host smart-de51db0c-497c-4204-a37c-b1b2005a56b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620003561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3620003561
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.973448793
Short name T630
Test name
Test status
Simulation time 175527016522 ps
CPU time 1987.63 seconds
Started Jul 02 08:36:42 AM PDT 24
Finished Jul 02 09:09:50 AM PDT 24
Peak memory 272740 kb
Host smart-7586f9a5-e20e-4512-913c-02e9605d0342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973448793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.973448793
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.870406468
Short name T502
Test name
Test status
Simulation time 6242513368 ps
CPU time 91.78 seconds
Started Jul 02 08:36:38 AM PDT 24
Finished Jul 02 08:38:11 AM PDT 24
Peak memory 257508 kb
Host smart-8109fcce-be8b-44ff-8396-6a6c8fceb340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87040
6468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.870406468
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3327670259
Short name T104
Test name
Test status
Simulation time 1270291901 ps
CPU time 36.64 seconds
Started Jul 02 08:36:37 AM PDT 24
Finished Jul 02 08:37:15 AM PDT 24
Peak memory 256516 kb
Host smart-d4d1c7f4-61ef-42a0-8743-861dfa8cda19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33276
70259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3327670259
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1149045487
Short name T644
Test name
Test status
Simulation time 13858157040 ps
CPU time 1050.24 seconds
Started Jul 02 08:36:42 AM PDT 24
Finished Jul 02 08:54:13 AM PDT 24
Peak memory 284804 kb
Host smart-be401acc-cf4e-41a6-83cc-059a150a067a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149045487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1149045487
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3205956479
Short name T404
Test name
Test status
Simulation time 73546306811 ps
CPU time 2137.48 seconds
Started Jul 02 08:36:42 AM PDT 24
Finished Jul 02 09:12:20 AM PDT 24
Peak memory 288592 kb
Host smart-d4899ecc-841d-42b6-908a-7c9c17519d6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205956479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3205956479
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3444715488
Short name T300
Test name
Test status
Simulation time 14336708561 ps
CPU time 564.9 seconds
Started Jul 02 08:36:43 AM PDT 24
Finished Jul 02 08:46:09 AM PDT 24
Peak memory 249208 kb
Host smart-d467c64e-a3aa-4026-8b6c-38ab48536a67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444715488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3444715488
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2609988362
Short name T454
Test name
Test status
Simulation time 153086779 ps
CPU time 4.29 seconds
Started Jul 02 08:36:33 AM PDT 24
Finished Jul 02 08:36:38 AM PDT 24
Peak memory 249308 kb
Host smart-3812620b-535d-4a3b-a2da-24fb6baf2c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26099
88362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2609988362
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.281718377
Short name T431
Test name
Test status
Simulation time 3287884042 ps
CPU time 51.97 seconds
Started Jul 02 08:36:33 AM PDT 24
Finished Jul 02 08:37:25 AM PDT 24
Peak memory 256400 kb
Host smart-3a3ed59f-2d85-46eb-985f-10ff59e5fd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171
8377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.281718377
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.55548884
Short name T409
Test name
Test status
Simulation time 232178798 ps
CPU time 16.51 seconds
Started Jul 02 08:36:40 AM PDT 24
Finished Jul 02 08:36:57 AM PDT 24
Peak memory 248772 kb
Host smart-afdbd130-20d2-4d60-bce4-f2e113865a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55548
884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.55548884
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2090960485
Short name T653
Test name
Test status
Simulation time 5912514851 ps
CPU time 47.25 seconds
Started Jul 02 08:36:33 AM PDT 24
Finished Jul 02 08:37:22 AM PDT 24
Peak memory 249852 kb
Host smart-306355c4-b8ba-4a5f-9d6a-f5911a8b8618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20909
60485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2090960485
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3255999492
Short name T554
Test name
Test status
Simulation time 65910998891 ps
CPU time 1479.48 seconds
Started Jul 02 08:36:42 AM PDT 24
Finished Jul 02 09:01:22 AM PDT 24
Peak memory 290088 kb
Host smart-d6a77a74-0c55-446a-bc87-361ab175745d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255999492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3255999492
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.4184018315
Short name T77
Test name
Test status
Simulation time 47819303971 ps
CPU time 5323.27 seconds
Started Jul 02 08:36:41 AM PDT 24
Finished Jul 02 10:05:26 AM PDT 24
Peak memory 348064 kb
Host smart-28f2eecb-5b12-4c1a-9d39-b00c7ff00b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184018315 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.4184018315
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2389006948
Short name T343
Test name
Test status
Simulation time 37573778292 ps
CPU time 2296.88 seconds
Started Jul 02 08:36:50 AM PDT 24
Finished Jul 02 09:15:07 AM PDT 24
Peak memory 289436 kb
Host smart-e7e23b47-8894-41a8-ace2-5219ff4a611f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389006948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2389006948
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2093902389
Short name T223
Test name
Test status
Simulation time 2624107086 ps
CPU time 80.75 seconds
Started Jul 02 08:36:45 AM PDT 24
Finished Jul 02 08:38:07 AM PDT 24
Peak memory 257140 kb
Host smart-966fd9d9-03f7-434b-a1b6-40964cd6bf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20939
02389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2093902389
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3836739974
Short name T218
Test name
Test status
Simulation time 54462496 ps
CPU time 4.95 seconds
Started Jul 02 08:36:46 AM PDT 24
Finished Jul 02 08:36:51 AM PDT 24
Peak memory 248716 kb
Host smart-421cfded-05e0-46f7-b644-3405c8d0a996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38367
39974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3836739974
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.136653930
Short name T425
Test name
Test status
Simulation time 12552430621 ps
CPU time 1052.21 seconds
Started Jul 02 08:36:58 AM PDT 24
Finished Jul 02 08:54:31 AM PDT 24
Peak memory 273656 kb
Host smart-75983e10-c858-44a5-b62e-b3976e617385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136653930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.136653930
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3625332320
Short name T492
Test name
Test status
Simulation time 41077586875 ps
CPU time 2472.78 seconds
Started Jul 02 08:36:56 AM PDT 24
Finished Jul 02 09:18:09 AM PDT 24
Peak memory 282128 kb
Host smart-c1527611-be7c-4aca-8fd0-069c6aa00293
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625332320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3625332320
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1268003717
Short name T486
Test name
Test status
Simulation time 1921787060 ps
CPU time 88.37 seconds
Started Jul 02 08:36:50 AM PDT 24
Finished Jul 02 08:38:20 AM PDT 24
Peak memory 257484 kb
Host smart-b0cfd496-ef75-4858-9b7f-f601cbf516ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268003717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1268003717
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.243995019
Short name T61
Test name
Test status
Simulation time 608797072 ps
CPU time 35.34 seconds
Started Jul 02 08:36:46 AM PDT 24
Finished Jul 02 08:37:22 AM PDT 24
Peak memory 256796 kb
Host smart-c14b6aec-c1d2-414d-af37-12674f83e173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24399
5019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.243995019
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2517963032
Short name T44
Test name
Test status
Simulation time 306290310 ps
CPU time 7.1 seconds
Started Jul 02 08:36:47 AM PDT 24
Finished Jul 02 08:36:55 AM PDT 24
Peak memory 249328 kb
Host smart-aa698bb2-657a-46c2-97ea-4ed5dafa42f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25179
63032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2517963032
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3622896097
Short name T242
Test name
Test status
Simulation time 488470486 ps
CPU time 9.48 seconds
Started Jul 02 08:36:50 AM PDT 24
Finished Jul 02 08:37:01 AM PDT 24
Peak memory 254320 kb
Host smart-0e7f5f64-b851-488f-ba5d-2cc104e0f31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36228
96097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3622896097
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2189006717
Short name T525
Test name
Test status
Simulation time 5212417129 ps
CPU time 75.79 seconds
Started Jul 02 08:36:46 AM PDT 24
Finished Jul 02 08:38:02 AM PDT 24
Peak memory 257472 kb
Host smart-aa4db743-08f2-4918-afb5-ee3b84fe3273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21890
06717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2189006717
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3309981623
Short name T602
Test name
Test status
Simulation time 124935512171 ps
CPU time 2091.13 seconds
Started Jul 02 08:36:58 AM PDT 24
Finished Jul 02 09:11:49 AM PDT 24
Peak memory 285040 kb
Host smart-fdcf08e4-e17f-4b70-945e-c791a13603e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309981623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3309981623
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1327014381
Short name T366
Test name
Test status
Simulation time 15654638298 ps
CPU time 1706.41 seconds
Started Jul 02 08:37:05 AM PDT 24
Finished Jul 02 09:05:32 AM PDT 24
Peak memory 289432 kb
Host smart-d8490ed2-3034-4e59-8798-a472b298d0b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327014381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1327014381
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3029607334
Short name T341
Test name
Test status
Simulation time 1325452008 ps
CPU time 119.15 seconds
Started Jul 02 08:37:01 AM PDT 24
Finished Jul 02 08:39:01 AM PDT 24
Peak memory 256980 kb
Host smart-db3e3b78-8a44-431c-8f94-bedb7566e035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30296
07334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3029607334
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3533218678
Short name T387
Test name
Test status
Simulation time 1832639886 ps
CPU time 7.54 seconds
Started Jul 02 08:36:55 AM PDT 24
Finished Jul 02 08:37:03 AM PDT 24
Peak memory 252260 kb
Host smart-3d904880-354f-4f69-9b10-2c0f3e47b70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35332
18678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3533218678
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4253462043
Short name T293
Test name
Test status
Simulation time 17146451621 ps
CPU time 743.06 seconds
Started Jul 02 08:37:04 AM PDT 24
Finished Jul 02 08:49:28 AM PDT 24
Peak memory 272064 kb
Host smart-4c9a8613-38d7-4ed4-8d1a-a4155ce2a2d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253462043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4253462043
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1484959404
Short name T593
Test name
Test status
Simulation time 11345354953 ps
CPU time 240.97 seconds
Started Jul 02 08:37:05 AM PDT 24
Finished Jul 02 08:41:07 AM PDT 24
Peak memory 249420 kb
Host smart-4ae35bb2-d0cc-43dc-bb14-d9a9ffe27247
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484959404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1484959404
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.300838858
Short name T555
Test name
Test status
Simulation time 739939427 ps
CPU time 10.67 seconds
Started Jul 02 08:36:56 AM PDT 24
Finished Jul 02 08:37:07 AM PDT 24
Peak memory 249276 kb
Host smart-62ffd045-aefc-43ac-9b52-8ed181cb487c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30083
8858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.300838858
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2662211350
Short name T279
Test name
Test status
Simulation time 192188037 ps
CPU time 21.83 seconds
Started Jul 02 08:36:54 AM PDT 24
Finished Jul 02 08:37:17 AM PDT 24
Peak memory 249032 kb
Host smart-55d5566f-4940-4803-8945-5147f859c351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26622
11350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2662211350
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2414723023
Short name T221
Test name
Test status
Simulation time 415377242 ps
CPU time 8.88 seconds
Started Jul 02 08:37:04 AM PDT 24
Finished Jul 02 08:37:14 AM PDT 24
Peak memory 248580 kb
Host smart-75398889-7028-4906-a91d-04b25cdb9ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24147
23023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2414723023
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2122835575
Short name T474
Test name
Test status
Simulation time 4506932488 ps
CPU time 68.04 seconds
Started Jul 02 08:36:56 AM PDT 24
Finished Jul 02 08:38:04 AM PDT 24
Peak memory 249252 kb
Host smart-ec897c17-1b98-472d-9f88-f95af384e6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21228
35575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2122835575
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2660210325
Short name T355
Test name
Test status
Simulation time 35690597392 ps
CPU time 731.08 seconds
Started Jul 02 08:37:16 AM PDT 24
Finished Jul 02 08:49:28 AM PDT 24
Peak memory 273560 kb
Host smart-7ed2ba6c-2e93-454d-9356-2e152f136c85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660210325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2660210325
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.832634223
Short name T371
Test name
Test status
Simulation time 248527207 ps
CPU time 30.5 seconds
Started Jul 02 08:37:13 AM PDT 24
Finished Jul 02 08:37:44 AM PDT 24
Peak memory 256884 kb
Host smart-6b57e08e-6b5b-4c76-a215-f245bb692e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83263
4223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.832634223
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3165849899
Short name T675
Test name
Test status
Simulation time 651112722 ps
CPU time 35.13 seconds
Started Jul 02 08:37:12 AM PDT 24
Finished Jul 02 08:37:48 AM PDT 24
Peak memory 257036 kb
Host smart-9ddf1cd3-132e-4295-b158-fcc834e364f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31658
49899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3165849899
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.597209092
Short name T635
Test name
Test status
Simulation time 24328501711 ps
CPU time 1533.38 seconds
Started Jul 02 08:37:16 AM PDT 24
Finished Jul 02 09:02:50 AM PDT 24
Peak memory 273428 kb
Host smart-b94fbed8-a6a3-4169-8a42-9ac880ad787d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597209092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.597209092
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1510343889
Short name T86
Test name
Test status
Simulation time 26122638974 ps
CPU time 780.24 seconds
Started Jul 02 08:37:21 AM PDT 24
Finished Jul 02 08:50:22 AM PDT 24
Peak memory 273972 kb
Host smart-d0cd7c5d-9c4b-4c5c-b5ec-ba19fee2b073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510343889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1510343889
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2070874261
Short name T530
Test name
Test status
Simulation time 1811385054 ps
CPU time 58.68 seconds
Started Jul 02 08:37:13 AM PDT 24
Finished Jul 02 08:38:13 AM PDT 24
Peak memory 249220 kb
Host smart-360c51ac-3339-4750-8c38-648c9e238199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708
74261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2070874261
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2982872790
Short name T553
Test name
Test status
Simulation time 2686363447 ps
CPU time 32.74 seconds
Started Jul 02 08:37:14 AM PDT 24
Finished Jul 02 08:37:47 AM PDT 24
Peak memory 248672 kb
Host smart-bc4a2995-ea44-49a9-aefb-c25f41d1f277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29828
72790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2982872790
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1053666867
Short name T432
Test name
Test status
Simulation time 767715161 ps
CPU time 13.87 seconds
Started Jul 02 08:37:16 AM PDT 24
Finished Jul 02 08:37:31 AM PDT 24
Peak memory 248828 kb
Host smart-5f9a13f2-874b-4d12-82ae-d435132eec38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10536
66867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1053666867
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3091893573
Short name T217
Test name
Test status
Simulation time 1088819601 ps
CPU time 67.31 seconds
Started Jul 02 08:37:13 AM PDT 24
Finished Jul 02 08:38:21 AM PDT 24
Peak memory 257444 kb
Host smart-09cb6e96-22f4-4410-978d-18b3c62eb615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30918
93573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3091893573
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3517249511
Short name T702
Test name
Test status
Simulation time 73052468513 ps
CPU time 1581.31 seconds
Started Jul 02 08:37:21 AM PDT 24
Finished Jul 02 09:03:43 AM PDT 24
Peak memory 290064 kb
Host smart-58b3e2a4-8c83-43a0-9db6-de6d51f09d67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517249511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3517249511
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2533577031
Short name T58
Test name
Test status
Simulation time 145914482646 ps
CPU time 2042.32 seconds
Started Jul 02 08:37:29 AM PDT 24
Finished Jul 02 09:11:33 AM PDT 24
Peak memory 273880 kb
Host smart-35734728-f884-48c4-acb2-98f003dba209
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533577031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2533577031
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3416838540
Short name T666
Test name
Test status
Simulation time 1980781897 ps
CPU time 194.15 seconds
Started Jul 02 08:37:24 AM PDT 24
Finished Jul 02 08:40:39 AM PDT 24
Peak memory 257496 kb
Host smart-40bd3165-62d8-4fc6-a8a7-dba324c678e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34168
38540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3416838540
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.172338668
Short name T385
Test name
Test status
Simulation time 1341151314 ps
CPU time 43.72 seconds
Started Jul 02 08:37:24 AM PDT 24
Finished Jul 02 08:38:09 AM PDT 24
Peak memory 257472 kb
Host smart-600bf0b0-6ae1-4b27-94b3-251cfdd3901a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17233
8668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.172338668
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1970310347
Short name T215
Test name
Test status
Simulation time 9482066950 ps
CPU time 1244.24 seconds
Started Jul 02 08:37:33 AM PDT 24
Finished Jul 02 08:58:18 AM PDT 24
Peak memory 290312 kb
Host smart-128d1a0f-a815-4d99-abf9-d5cc22ebffc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970310347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1970310347
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2369849651
Short name T632
Test name
Test status
Simulation time 45599786090 ps
CPU time 442.77 seconds
Started Jul 02 08:37:33 AM PDT 24
Finished Jul 02 08:44:57 AM PDT 24
Peak memory 249408 kb
Host smart-9edb960b-c2c7-4464-ba17-13617626f144
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369849651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2369849651
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3789966418
Short name T384
Test name
Test status
Simulation time 7749301427 ps
CPU time 48.24 seconds
Started Jul 02 08:37:21 AM PDT 24
Finished Jul 02 08:38:10 AM PDT 24
Peak memory 257004 kb
Host smart-da01278a-db35-48d0-9b67-5ebb8ba93209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37899
66418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3789966418
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.929443887
Short name T346
Test name
Test status
Simulation time 630891359 ps
CPU time 44.63 seconds
Started Jul 02 08:37:25 AM PDT 24
Finished Jul 02 08:38:10 AM PDT 24
Peak memory 256940 kb
Host smart-5a958b00-4a42-404c-b331-b9e5856b8750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92944
3887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.929443887
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.300827953
Short name T397
Test name
Test status
Simulation time 800097074 ps
CPU time 16.22 seconds
Started Jul 02 08:37:24 AM PDT 24
Finished Jul 02 08:37:41 AM PDT 24
Peak memory 249288 kb
Host smart-01647e0c-a696-42b5-a9b8-56106a851b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30082
7953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.300827953
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2543366818
Short name T378
Test name
Test status
Simulation time 1065203669 ps
CPU time 39.87 seconds
Started Jul 02 08:37:20 AM PDT 24
Finished Jul 02 08:38:01 AM PDT 24
Peak memory 257376 kb
Host smart-4da3a98d-21da-4d67-83c5-a8c20c26faed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25433
66818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2543366818
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2502896831
Short name T252
Test name
Test status
Simulation time 37341989005 ps
CPU time 1804.47 seconds
Started Jul 02 08:37:33 AM PDT 24
Finished Jul 02 09:07:38 AM PDT 24
Peak memory 302372 kb
Host smart-042beb16-e125-4d69-b1a5-d5a651c6ce00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502896831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2502896831
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3113464085
Short name T108
Test name
Test status
Simulation time 81063054335 ps
CPU time 5447.55 seconds
Started Jul 02 08:37:32 AM PDT 24
Finished Jul 02 10:08:21 AM PDT 24
Peak memory 322944 kb
Host smart-b0fc5eea-c6b4-4c62-8231-5cb2ad65d526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113464085 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3113464085
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.798793353
Short name T199
Test name
Test status
Simulation time 33707807 ps
CPU time 3.04 seconds
Started Jul 02 08:31:30 AM PDT 24
Finished Jul 02 08:31:33 AM PDT 24
Peak memory 249548 kb
Host smart-4fb21380-4225-43dd-8622-ba9c271e6bb7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=798793353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.798793353
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1967868488
Short name T451
Test name
Test status
Simulation time 32389434298 ps
CPU time 1801.17 seconds
Started Jul 02 08:31:21 AM PDT 24
Finished Jul 02 09:01:23 AM PDT 24
Peak memory 274032 kb
Host smart-924b68a2-18a7-46ec-93a9-4b3aa79a783b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967868488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1967868488
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1635361967
Short name T440
Test name
Test status
Simulation time 1084239975 ps
CPU time 41.12 seconds
Started Jul 02 08:31:27 AM PDT 24
Finished Jul 02 08:32:09 AM PDT 24
Peak memory 249232 kb
Host smart-4504398f-da5c-4225-a788-12c7e28faeff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1635361967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1635361967
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3719588942
Short name T604
Test name
Test status
Simulation time 5638449837 ps
CPU time 347.32 seconds
Started Jul 02 08:31:23 AM PDT 24
Finished Jul 02 08:37:11 AM PDT 24
Peak memory 252656 kb
Host smart-4e6cd77b-a779-440f-9d36-863ef3edfb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195
88942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3719588942
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.529759043
Short name T633
Test name
Test status
Simulation time 210200918 ps
CPU time 12.32 seconds
Started Jul 02 08:31:23 AM PDT 24
Finished Jul 02 08:31:35 AM PDT 24
Peak memory 249260 kb
Host smart-9c95ca00-5f90-4be3-973e-7a9e4f96b5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52975
9043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.529759043
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.22723981
Short name T310
Test name
Test status
Simulation time 67663029729 ps
CPU time 2263.79 seconds
Started Jul 02 08:31:21 AM PDT 24
Finished Jul 02 09:09:06 AM PDT 24
Peak memory 290192 kb
Host smart-aa89758b-98f7-4193-9d4c-94d90d1615ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22723981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.22723981
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.694511679
Short name T539
Test name
Test status
Simulation time 47789584524 ps
CPU time 1554.8 seconds
Started Jul 02 08:31:26 AM PDT 24
Finished Jul 02 08:57:22 AM PDT 24
Peak memory 273232 kb
Host smart-5f3b818f-f3b0-4a15-814c-cf14da1c8e6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694511679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.694511679
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.168340189
Short name T14
Test name
Test status
Simulation time 56183277663 ps
CPU time 258.4 seconds
Started Jul 02 08:31:21 AM PDT 24
Finished Jul 02 08:35:40 AM PDT 24
Peak memory 249256 kb
Host smart-49d3b459-3702-4b9e-a83b-41010714abc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168340189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.168340189
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.913765772
Short name T535
Test name
Test status
Simulation time 1801266199 ps
CPU time 31.76 seconds
Started Jul 02 08:31:23 AM PDT 24
Finished Jul 02 08:31:55 AM PDT 24
Peak memory 256468 kb
Host smart-e4e7eb18-5bdc-4c28-bd63-0f09405d0a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91376
5772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.913765772
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3380283772
Short name T278
Test name
Test status
Simulation time 3095919029 ps
CPU time 43.67 seconds
Started Jul 02 08:31:22 AM PDT 24
Finished Jul 02 08:32:06 AM PDT 24
Peak memory 257524 kb
Host smart-646a229b-2422-4077-94eb-e94a78e94ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33802
83772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3380283772
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3748919810
Short name T468
Test name
Test status
Simulation time 47767657 ps
CPU time 4.33 seconds
Started Jul 02 08:31:23 AM PDT 24
Finished Jul 02 08:31:28 AM PDT 24
Peak memory 249332 kb
Host smart-eb629a97-94ff-4954-a305-7c7671ff9c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37489
19810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3748919810
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3603034964
Short name T521
Test name
Test status
Simulation time 1132153270 ps
CPU time 32.63 seconds
Started Jul 02 08:31:17 AM PDT 24
Finished Jul 02 08:31:51 AM PDT 24
Peak memory 257432 kb
Host smart-b7d363d8-4e08-481a-a10c-3f483bfb6a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36030
34964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3603034964
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4294537387
Short name T461
Test name
Test status
Simulation time 12523908135 ps
CPU time 1166.82 seconds
Started Jul 02 08:31:27 AM PDT 24
Finished Jul 02 08:50:54 AM PDT 24
Peak memory 289652 kb
Host smart-99dc0b62-c96c-4b5c-bb37-1800cf9c8aea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294537387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4294537387
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2954479685
Short name T89
Test name
Test status
Simulation time 35119966928 ps
CPU time 1068.59 seconds
Started Jul 02 08:31:28 AM PDT 24
Finished Jul 02 08:49:17 AM PDT 24
Peak memory 284020 kb
Host smart-52296863-2f45-4529-955f-3c211b324607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954479685 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2954479685
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1099581170
Short name T202
Test name
Test status
Simulation time 39568523 ps
CPU time 3.39 seconds
Started Jul 02 08:31:32 AM PDT 24
Finished Jul 02 08:31:36 AM PDT 24
Peak memory 249516 kb
Host smart-8b23cc92-2ad6-418f-93bc-f656aca10e18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1099581170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1099581170
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.997823891
Short name T263
Test name
Test status
Simulation time 49272064178 ps
CPU time 1283.27 seconds
Started Jul 02 08:31:32 AM PDT 24
Finished Jul 02 08:52:56 AM PDT 24
Peak memory 290164 kb
Host smart-dcf4876f-0580-48a9-9c96-b0d0808b8020
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997823891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.997823891
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1890274509
Short name T205
Test name
Test status
Simulation time 836995852 ps
CPU time 9.24 seconds
Started Jul 02 08:31:33 AM PDT 24
Finished Jul 02 08:31:43 AM PDT 24
Peak memory 249308 kb
Host smart-5472b7d9-438f-442c-b6f3-0640805dafe6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1890274509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1890274509
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2251316244
Short name T617
Test name
Test status
Simulation time 36114703969 ps
CPU time 180.34 seconds
Started Jul 02 08:31:28 AM PDT 24
Finished Jul 02 08:34:29 AM PDT 24
Peak memory 257568 kb
Host smart-f9056bd4-0d9c-4b30-a613-38572078b7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22513
16244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2251316244
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1282125525
Short name T657
Test name
Test status
Simulation time 792396759 ps
CPU time 19.92 seconds
Started Jul 02 08:31:26 AM PDT 24
Finished Jul 02 08:31:47 AM PDT 24
Peak memory 249224 kb
Host smart-4048b078-3326-4d79-9f56-95760845bf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12821
25525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1282125525
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1153294198
Short name T624
Test name
Test status
Simulation time 149953622697 ps
CPU time 2401.83 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 09:11:37 AM PDT 24
Peak memory 290304 kb
Host smart-5c497de3-673a-4f46-802b-6ce4e0dac870
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153294198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1153294198
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1032877682
Short name T6
Test name
Test status
Simulation time 16413235827 ps
CPU time 486.75 seconds
Started Jul 02 08:31:28 AM PDT 24
Finished Jul 02 08:39:36 AM PDT 24
Peak memory 249348 kb
Host smart-0d10e897-8adc-4139-be79-19e0c2e13f85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032877682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1032877682
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1276893794
Short name T513
Test name
Test status
Simulation time 776127094 ps
CPU time 21.52 seconds
Started Jul 02 08:31:28 AM PDT 24
Finished Jul 02 08:31:50 AM PDT 24
Peak memory 256476 kb
Host smart-08efe928-81da-410f-8acd-c7cc3af5c216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12768
93794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1276893794
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1349925554
Short name T498
Test name
Test status
Simulation time 250007136 ps
CPU time 4.99 seconds
Started Jul 02 08:31:27 AM PDT 24
Finished Jul 02 08:31:32 AM PDT 24
Peak memory 240308 kb
Host smart-dfb16517-65fe-49f3-8d3a-3753fa23c59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
25554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1349925554
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.167820508
Short name T482
Test name
Test status
Simulation time 114905224 ps
CPU time 14.33 seconds
Started Jul 02 08:31:29 AM PDT 24
Finished Jul 02 08:31:44 AM PDT 24
Peak memory 249236 kb
Host smart-d65b40ff-71f1-458b-8758-7cb3a87c9e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
0508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.167820508
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.990148546
Short name T483
Test name
Test status
Simulation time 249060767 ps
CPU time 15.42 seconds
Started Jul 02 08:31:28 AM PDT 24
Finished Jul 02 08:31:44 AM PDT 24
Peak memory 255992 kb
Host smart-cefcac5b-7edc-476c-996b-3ef55ef69a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99014
8546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.990148546
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.328958486
Short name T586
Test name
Test status
Simulation time 10895478481 ps
CPU time 963.49 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:47:38 AM PDT 24
Peak memory 288040 kb
Host smart-4385fd9c-29be-4f47-8947-167fc5d72151
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328958486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.328958486
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2725583295
Short name T191
Test name
Test status
Simulation time 67229830 ps
CPU time 3.45 seconds
Started Jul 02 08:31:38 AM PDT 24
Finished Jul 02 08:31:42 AM PDT 24
Peak memory 249552 kb
Host smart-4ac6c399-241d-443f-967e-a6d93013e938
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2725583295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2725583295
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2364281502
Short name T405
Test name
Test status
Simulation time 98226916293 ps
CPU time 1366.08 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:54:21 AM PDT 24
Peak memory 273940 kb
Host smart-e4b4a9a1-ec6d-4029-aa3b-48cedad5a12c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364281502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2364281502
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1496132571
Short name T487
Test name
Test status
Simulation time 557188397 ps
CPU time 9.86 seconds
Started Jul 02 08:31:39 AM PDT 24
Finished Jul 02 08:31:49 AM PDT 24
Peak memory 249296 kb
Host smart-39dcdcfe-780e-4de7-b85d-4680d8bc3598
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1496132571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1496132571
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1194099553
Short name T695
Test name
Test status
Simulation time 384670143 ps
CPU time 36.56 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:32:12 AM PDT 24
Peak memory 256768 kb
Host smart-7aac5b69-5231-4916-a4f0-de126b122a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11940
99553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1194099553
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2239447089
Short name T213
Test name
Test status
Simulation time 1768872437 ps
CPU time 35.78 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:32:10 AM PDT 24
Peak memory 249252 kb
Host smart-3515d414-afbb-4852-8b78-a829aee6c959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22394
47089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2239447089
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1424837995
Short name T354
Test name
Test status
Simulation time 31130889650 ps
CPU time 1694 seconds
Started Jul 02 08:31:37 AM PDT 24
Finished Jul 02 08:59:51 AM PDT 24
Peak memory 290264 kb
Host smart-f35f7998-4cc5-4b57-917e-65b344378cc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424837995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1424837995
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.419457473
Short name T447
Test name
Test status
Simulation time 4765401633 ps
CPU time 210.41 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:35:05 AM PDT 24
Peak memory 249404 kb
Host smart-96e31055-7bef-4439-9875-d3cec81a68db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419457473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.419457473
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2388787929
Short name T686
Test name
Test status
Simulation time 1286038863 ps
CPU time 26.41 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:32:01 AM PDT 24
Peak memory 257080 kb
Host smart-2c6a8514-1999-490d-9c21-c26453714e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23887
87929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2388787929
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4208218358
Short name T54
Test name
Test status
Simulation time 542932517 ps
CPU time 33.53 seconds
Started Jul 02 08:31:33 AM PDT 24
Finished Jul 02 08:32:07 AM PDT 24
Peak memory 249252 kb
Host smart-0d5ccbb9-4563-4516-8bee-e730a5a155b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42082
18358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4208218358
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2150327283
Short name T514
Test name
Test status
Simulation time 39742499 ps
CPU time 5.09 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:31:40 AM PDT 24
Peak memory 248804 kb
Host smart-67900782-a8f4-4075-af43-fceb96aa51e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21503
27283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2150327283
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2840522385
Short name T594
Test name
Test status
Simulation time 1677618041 ps
CPU time 49.09 seconds
Started Jul 02 08:31:34 AM PDT 24
Finished Jul 02 08:32:24 AM PDT 24
Peak memory 257444 kb
Host smart-5c52c536-e1f4-4156-bc37-8a5a551983c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28405
22385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2840522385
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2873920719
Short name T435
Test name
Test status
Simulation time 939694946 ps
CPU time 51.19 seconds
Started Jul 02 08:31:37 AM PDT 24
Finished Jul 02 08:32:28 AM PDT 24
Peak memory 257348 kb
Host smart-72c991ef-1684-4453-a28f-30e3e4653ddb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873920719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2873920719
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.962399539
Short name T174
Test name
Test status
Simulation time 90604172448 ps
CPU time 4823.66 seconds
Started Jul 02 08:31:37 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 371848 kb
Host smart-9553d446-e5ed-41e3-9e42-48d9ee942020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962399539 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.962399539
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1555285938
Short name T197
Test name
Test status
Simulation time 32686216 ps
CPU time 2.66 seconds
Started Jul 02 08:31:42 AM PDT 24
Finished Jul 02 08:31:46 AM PDT 24
Peak memory 249520 kb
Host smart-103ae57f-ccc6-4875-91f7-695b4b0a780a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1555285938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1555285938
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.287588598
Short name T700
Test name
Test status
Simulation time 17245514328 ps
CPU time 1169.54 seconds
Started Jul 02 08:31:44 AM PDT 24
Finished Jul 02 08:51:14 AM PDT 24
Peak memory 265812 kb
Host smart-8f07fc04-247b-4844-89c6-6182f21b9b1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287588598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.287588598
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1080375097
Short name T660
Test name
Test status
Simulation time 1941581046 ps
CPU time 41.8 seconds
Started Jul 02 08:31:43 AM PDT 24
Finished Jul 02 08:32:26 AM PDT 24
Peak memory 249276 kb
Host smart-29314a1c-2418-42b7-a761-a8cf2f02d58d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1080375097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1080375097
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.860844253
Short name T388
Test name
Test status
Simulation time 743909853 ps
CPU time 58.62 seconds
Started Jul 02 08:31:42 AM PDT 24
Finished Jul 02 08:32:41 AM PDT 24
Peak memory 257264 kb
Host smart-7add9bc1-7966-4a9e-b1d8-1ec4a0cad635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86084
4253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.860844253
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.480670296
Short name T350
Test name
Test status
Simulation time 1705706100 ps
CPU time 32.66 seconds
Started Jul 02 08:31:41 AM PDT 24
Finished Jul 02 08:32:15 AM PDT 24
Peak memory 257044 kb
Host smart-1b16956a-636c-4d09-9ee3-5c63a88cd573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48067
0296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.480670296
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3056145760
Short name T224
Test name
Test status
Simulation time 150444575571 ps
CPU time 2405.78 seconds
Started Jul 02 08:31:43 AM PDT 24
Finished Jul 02 09:11:50 AM PDT 24
Peak memory 290372 kb
Host smart-62ed2dfb-3492-4d3a-bb27-78432cbaa8c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056145760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3056145760
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2012197420
Short name T462
Test name
Test status
Simulation time 190957474264 ps
CPU time 1672.51 seconds
Started Jul 02 08:31:41 AM PDT 24
Finished Jul 02 08:59:34 AM PDT 24
Peak memory 273724 kb
Host smart-95fdf7db-df6a-4815-a134-935b8efbd186
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012197420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2012197420
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.324003701
Short name T292
Test name
Test status
Simulation time 21305403215 ps
CPU time 226.04 seconds
Started Jul 02 08:31:43 AM PDT 24
Finished Jul 02 08:35:29 AM PDT 24
Peak memory 249320 kb
Host smart-988b54dd-2bbb-410b-92ce-e14338a8f8da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324003701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.324003701
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.200260436
Short name T588
Test name
Test status
Simulation time 907292270 ps
CPU time 53.9 seconds
Started Jul 02 08:31:37 AM PDT 24
Finished Jul 02 08:32:32 AM PDT 24
Peak memory 257392 kb
Host smart-dd5afff6-c9ee-410d-94e3-f6b287043a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20026
0436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.200260436
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2776555384
Short name T655
Test name
Test status
Simulation time 121097510 ps
CPU time 10.41 seconds
Started Jul 02 08:31:36 AM PDT 24
Finished Jul 02 08:31:47 AM PDT 24
Peak memory 256940 kb
Host smart-27b63461-ef23-4938-8d95-a93874feb338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
55384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2776555384
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3497836909
Short name T509
Test name
Test status
Simulation time 728163972 ps
CPU time 12.77 seconds
Started Jul 02 08:31:42 AM PDT 24
Finished Jul 02 08:31:55 AM PDT 24
Peak memory 255388 kb
Host smart-251fa67e-51aa-445f-aa6e-a81d32713855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34978
36909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3497836909
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3769516133
Short name T545
Test name
Test status
Simulation time 401578270 ps
CPU time 29.2 seconds
Started Jul 02 08:31:38 AM PDT 24
Finished Jul 02 08:32:08 AM PDT 24
Peak memory 256568 kb
Host smart-27867091-916d-4d21-b81c-4abf659c3f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37695
16133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3769516133
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3670676839
Short name T250
Test name
Test status
Simulation time 13574531379 ps
CPU time 416.67 seconds
Started Jul 02 08:31:41 AM PDT 24
Finished Jul 02 08:38:39 AM PDT 24
Peak memory 257628 kb
Host smart-5c8bb188-54bc-445b-9189-3df805e19dd1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670676839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3670676839
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1761566668
Short name T201
Test name
Test status
Simulation time 117280710 ps
CPU time 3 seconds
Started Jul 02 08:31:47 AM PDT 24
Finished Jul 02 08:31:51 AM PDT 24
Peak memory 249492 kb
Host smart-35a5ae0a-a16e-4478-87c3-7b2d479738f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1761566668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1761566668
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2209657025
Short name T412
Test name
Test status
Simulation time 17287766864 ps
CPU time 1386.65 seconds
Started Jul 02 08:31:47 AM PDT 24
Finished Jul 02 08:54:54 AM PDT 24
Peak memory 289224 kb
Host smart-2e6b0fee-bd3e-41f0-9869-528d09134b57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209657025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2209657025
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3793316777
Short name T67
Test name
Test status
Simulation time 9336063807 ps
CPU time 49.21 seconds
Started Jul 02 08:31:49 AM PDT 24
Finished Jul 02 08:32:39 AM PDT 24
Peak memory 249296 kb
Host smart-29e0bbca-eab3-4b34-a8f5-6246eec52a6a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3793316777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3793316777
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4097150057
Short name T445
Test name
Test status
Simulation time 1344234712 ps
CPU time 77.61 seconds
Started Jul 02 08:31:48 AM PDT 24
Finished Jul 02 08:33:06 AM PDT 24
Peak memory 257112 kb
Host smart-b84f0315-934b-488b-b266-c775619f1fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40971
50057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4097150057
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3365900331
Short name T68
Test name
Test status
Simulation time 258505032 ps
CPU time 22.64 seconds
Started Jul 02 08:31:49 AM PDT 24
Finished Jul 02 08:32:13 AM PDT 24
Peak memory 248816 kb
Host smart-3308dc8c-34a0-4be4-b8e2-679ac78750bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
00331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3365900331
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2101550926
Short name T283
Test name
Test status
Simulation time 33891877443 ps
CPU time 602.15 seconds
Started Jul 02 08:31:48 AM PDT 24
Finished Jul 02 08:41:51 AM PDT 24
Peak memory 273256 kb
Host smart-d7e7fbe1-c868-4d7a-b773-a2539f878032
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101550926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2101550926
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.756672403
Short name T434
Test name
Test status
Simulation time 66863736902 ps
CPU time 1884.36 seconds
Started Jul 02 08:31:49 AM PDT 24
Finished Jul 02 09:03:14 AM PDT 24
Peak memory 289676 kb
Host smart-97f6c37b-f924-4235-ab4e-f48c198fddec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756672403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.756672403
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1044343093
Short name T296
Test name
Test status
Simulation time 56929015738 ps
CPU time 546.07 seconds
Started Jul 02 08:31:49 AM PDT 24
Finished Jul 02 08:40:56 AM PDT 24
Peak memory 249200 kb
Host smart-8cd7aef9-08d6-4000-acce-76eb3b5b7b3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044343093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1044343093
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.826270579
Short name T50
Test name
Test status
Simulation time 576640248 ps
CPU time 26.73 seconds
Started Jul 02 08:31:43 AM PDT 24
Finished Jul 02 08:32:10 AM PDT 24
Peak memory 257400 kb
Host smart-f2d8760b-ddbd-49af-b9ed-aebe5df234ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82627
0579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.826270579
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3942982115
Short name T390
Test name
Test status
Simulation time 539424972 ps
CPU time 27.13 seconds
Started Jul 02 08:31:44 AM PDT 24
Finished Jul 02 08:32:12 AM PDT 24
Peak memory 257304 kb
Host smart-7a7b9f22-76c2-4c7a-985d-039b1ab83ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39429
82115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3942982115
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2974087122
Short name T103
Test name
Test status
Simulation time 427781905 ps
CPU time 26.53 seconds
Started Jul 02 08:31:47 AM PDT 24
Finished Jul 02 08:32:14 AM PDT 24
Peak memory 256540 kb
Host smart-49b76243-85df-4584-8045-07e65777c783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29740
87122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2974087122
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1125935995
Short name T568
Test name
Test status
Simulation time 239767284 ps
CPU time 24.4 seconds
Started Jul 02 08:31:43 AM PDT 24
Finished Jul 02 08:32:08 AM PDT 24
Peak memory 257264 kb
Host smart-75788b2f-2875-451b-97cd-a0f5dba9b92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
35995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1125935995
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2859113511
Short name T72
Test name
Test status
Simulation time 28366750520 ps
CPU time 1856.1 seconds
Started Jul 02 08:31:47 AM PDT 24
Finished Jul 02 09:02:44 AM PDT 24
Peak memory 282140 kb
Host smart-1ef750a7-bd69-47d4-ab21-410e9cccaeb3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859113511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2859113511
Directory /workspace/9.alert_handler_stress_all/latest
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