Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	60369	1			T4	14		T6	4585		T23	47
class_i[0x1]	44486	1			T4	2		T17	1473		T10	2
class_i[0x2]	59620	1			T20	279		T15	231		T17	1318
class_i[0x3]	66433	1			T4	8		T20	7		T15	424

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	59643	1			T4	8		T6	1159		T20	3
alert[0x1]	58027	1			T4	12		T6	1120		T15	145
alert[0x2]	57038	1			T4	3		T6	1142		T20	4
alert[0x3]	56200	1			T4	1		T6	1164		T20	279

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

230638

1

T4

24

T6

4585

T20

286

esc_ping_fail

270

1

T9

6

T10

7

T11

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	59564	1			T4	8		T6	1159		T20	3
esc_integrity_fail	alert[0x1]	57964	1			T4	12		T6	1120		T15	145
esc_integrity_fail	alert[0x2]	56969	1			T4	3		T6	1142		T20	4
esc_integrity_fail	alert[0x3]	56141	1			T4	1		T6	1164		T20	279
esc_ping_fail	alert[0x0]	79	1			T9	2		T10	2		T11	1
esc_ping_fail	alert[0x1]	63	1			T9	1		T10	3		T249	2
esc_ping_fail	alert[0x2]	69	1			T9	2		T10	1		T249	2
esc_ping_fail	alert[0x3]	59	1			T9	1		T10	1		T11	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	60288	1			T4	14		T6	4585		T23	47
esc_integrity_fail	class_i[0x1]	44448	1			T4	2		T17	1473		T10	2
esc_integrity_fail	class_i[0x2]	59545	1			T20	279		T15	231		T17	1318
esc_integrity_fail	class_i[0x3]	66357	1			T4	8		T20	7		T15	424
esc_ping_fail	class_i[0x0]	81	1			T9	6		T10	7		T249	7
esc_ping_fail	class_i[0x1]	38	1			T212	9		T201	4		T82	4
esc_ping_fail	class_i[0x2]	75	1			T11	1		T249	1		T268	2
esc_ping_fail	class_i[0x3]	76	1			T11	2		T251	1		T256	9