Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	732120420	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	732120420	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	732120420	731932530	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	732120420	731932530	0	0
tb.dut.EdnKnownO_A	0	0	732120420	731932530	0	0
tb.dut.EscPKnownO_A	0	0	732120420	731932530	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	732120420	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	732120420	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	732120420	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	732120420	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	732120420	90	0	0
tb.dut.IrqAKnownO_A	0	0	732120420	731932530	0	0
tb.dut.IrqBKnownO_A	0	0	732120420	731932530	0	0
tb.dut.IrqCKnownO_A	0	0	732120420	731932530	0	0
tb.dut.IrqDKnownO_A	0	0	732120420	731932530	0	0
tb.dut.TlAReadyKnownO_A	0	0	732120420	731932530	0	0
tb.dut.TlDValidKnownO_A	0	0	732120420	731932530	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	758467543	3028830	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	758467543	16483	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	758467543	16143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	758467543	16699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	758467543	15391	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	758467543	17407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	758467543	15147	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	758467543	17386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	758467543	16283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	758467543	15015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	758467543	16116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	758467543	15320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	758467543	16310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	758467543	16454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	758467543	16099	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	758467543	16250	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	758467543	16091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	758467543	16404	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	758467543	15926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	758467543	15159	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	758467543	14882	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	758467543	14953	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	758467543	15110	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	758467543	17247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	758467543	16310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	758467543	16150	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	758467543	16143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	758467543	14845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	758467543	14868	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	758467543	15143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	758467543	15999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	758467543	16135	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	758467543	17393	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	758467543	17246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	758467543	16076	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	758467543	16168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	758467543	14867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	758467543	15549	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	758467543	17601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	758467543	16424	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	758467543	15915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	758467543	17104	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	758467543	14716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	758467543	14686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	758467543	15241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	758467543	14802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	758467543	15242	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	758467543	16163	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	758467543	15294	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	758467543	15045	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	758467543	16488	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	758467543	15764	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	758467543	16276	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	758467543	15270	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	758467543	16059	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	758467543	15936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	758467543	16328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	758467543	16376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	758467543	17017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	758467543	15333	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	758467543	16313	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	758467543	16533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	758467543	14902	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	758467543	15856	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	758467543	16130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	758467543	15331	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	758467543	15222	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	758467543	16093	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	758467543	16933	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	758467543	15243	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	758467543	30968	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	758467543	17424	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	758467543	14875	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	758467543	18007	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	758467543	14690	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	758467543	16210	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	758467543	14858	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	758467543	15343	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	758467543	15861	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	732120420	2030	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	732120420	214650	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	732120420	412240854	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	732120420	338	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	732120420	909	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	732120420	55	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	732120420	464	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	731923544	331570281	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	732120420	1015	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	732120420	987	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	732120420	970	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	732120420	944	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	732120420	1191	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	732120420	125834	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	732120420	1074	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	732120420	61	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	732120420	1637	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	732120420	1367	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	731921433	731848399	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	732120420	731932530	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	732120420	4386	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	732120420	191924	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	732120420	414006679	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	732120420	333	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	732120420	556	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	732120420	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	732120420	240	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	731923544	307173599	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	732120420	632	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	732120420	617	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	732120420	598	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	732120420	589	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	732120420	949	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	732120420	114452	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	732120420	865	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	732120420	59	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	732120420	1709	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	732120420	1439	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	731921433	731848399	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	732120420	731932530	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	732120420	3643	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	732120420	165648	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	732120420	416985617	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	732120420	293	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	732120420	505	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	732120420	22	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	732120420	205	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	731923544	310172354	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	732120420	577	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	732120420	569	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	732120420	560	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	732120420	545	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	732120420	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	732120420	69894	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	732120420	483	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	732120420	56	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	732120420	1588	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	732120420	1318	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	731921433	731848399	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	732120420	731932530	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	732120420	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	732120420	1907	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	732120420	186862	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	732120420	386226816	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	732120420	306	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	732120420	519	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	732120420	25	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	732120420	210	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	731923544	318105819	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	732120420	589	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	732120420	579	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	732120420	572	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	732120420	564	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	732120420	1585	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	732120420	178352	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	732120420	1501	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	732120420	53	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	732120420	1607	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	732120420	1337	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	731921433	731848399	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	732120420	731932530	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	758467543	133114780	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	758467543	757799851	0	0
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