Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	0	44	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	0	44	100.00	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	198	1			T5	1		T15	3		T17	1
index[0x1]	206	1			T16	2		T17	4		T40	2
index[0x2]	193	1			T4	1		T7	1		T15	2
index[0x3]	171	1			T4	1		T5	1		T15	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	246	1			T5	1		T15	2		T16	1
lens_less_than_1000[1]	154	1			T15	1		T16	1		T35	1
lens_less_than_1000[2]	101	1			T4	1		T15	1		T23	1
lens_less_than_1000[3]	80	1			T15	2		T17	1		T27	1
lens_less_than_1000[4]	60	1			T4	1		T17	1		T27	1
lens_less_than_1000[5]	44	1			T17	2		T27	1		T43	1
lens_less_than_1000[6]	34	1			T27	1		T29	1		T98	1
lens_less_than_1000[7]	22	1			T11	1		T43	1		T47	1
lens_less_than_1000[8]	8	1			T5	1		T7	1		T59	1
lens_less_than_1000[9]	7	1			T216	1		T233	1		T55	1
len_2	12	1			T16	1		T17	1		T281	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	0	44	100.00

Automatically Generated Cross Bins for len_per_esc_sig

Bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	67	1			T5	1		T17	1		T27	1
index[0x0]	lens_less_than_1000[1]	41	1			T27	1		T280	1		T62	1
index[0x0]	lens_less_than_1000[2]	23	1			T15	1		T41	1		T59	1
index[0x0]	lens_less_than_1000[3]	23	1			T15	2		T41	1		T203	1
index[0x0]	lens_less_than_1000[4]	16	1			T42	1		T48	2		T70	1
index[0x0]	lens_less_than_1000[5]	10	1			T27	1		T43	1		T68	1
index[0x0]	lens_less_than_1000[6]	7	1			T101	1		T225	1		T282	1
index[0x0]	lens_less_than_1000[7]	6	1			T252	1		T224	1		T283	1
index[0x0]	lens_less_than_1000[8]	1	1			T59	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T55	1		-	-		-	-
index[0x0]	len_2	3	1			T281	1		T226	1		T284	1
index[0x1]	lens_less_than_1000[0]	70	1			T16	1		T40	1		T27	1
index[0x1]	lens_less_than_1000[1]	31	1			T27	2		T41	1		T49	1
index[0x1]	lens_less_than_1000[2]	29	1			T17	1		T40	1		T29	1
index[0x1]	lens_less_than_1000[3]	28	1			T76	1		T46	3		T202	1
index[0x1]	lens_less_than_1000[4]	17	1			T59	1		T76	1		T70	1
index[0x1]	lens_less_than_1000[5]	8	1			T17	2		T285	1		T252	1
index[0x1]	lens_less_than_1000[6]	7	1			T27	1		T30	1		T223	1
index[0x1]	lens_less_than_1000[7]	9	1			T11	1		T43	1		T208	1
index[0x1]	lens_less_than_1000[8]	3	1			T49	1		T90	1		T94	1
index[0x1]	lens_less_than_1000[9]	1	1			T217	1		-	-		-	-
index[0x1]	len_2	3	1			T16	1		T17	1		T219	1
index[0x2]	lens_less_than_1000[0]	56	1			T15	2		T38	1		T95	1
index[0x2]	lens_less_than_1000[1]	38	1			T16	1		T35	1		T41	1
index[0x2]	lens_less_than_1000[2]	26	1			T286	1		T222	2		T287	1
index[0x2]	lens_less_than_1000[3]	16	1			T27	1		T280	1		T97	1
index[0x2]	lens_less_than_1000[4]	18	1			T4	1		T17	1		T42	1
index[0x2]	lens_less_than_1000[5]	18	1			T48	1		T70	1		T89	1
index[0x2]	lens_less_than_1000[6]	11	1			T29	1		T98	1		T60	1
index[0x2]	lens_less_than_1000[7]	3	1			T47	1		T90	1		T288	1
index[0x2]	lens_less_than_1000[8]	2	1			T7	1		T289	1		-	-
index[0x2]	lens_less_than_1000[9]	2	1			T216	1		T233	1		-	-
index[0x2]	len_2	3	1			T77	1		T290	1		T291	1
index[0x3]	lens_less_than_1000[0]	53	1			T17	7		T35	1		T27	1
index[0x3]	lens_less_than_1000[1]	44	1			T15	1		T203	2		T50	1
index[0x3]	lens_less_than_1000[2]	23	1			T4	1		T23	1		T65	2
index[0x3]	lens_less_than_1000[3]	13	1			T17	1		T30	1		T200	1
index[0x3]	lens_less_than_1000[4]	9	1			T27	1		T286	1		T243	1
index[0x3]	lens_less_than_1000[5]	8	1			T47	1		T70	1		T90	1
index[0x3]	lens_less_than_1000[6]	9	1			T285	1		T91	1		T55	1
index[0x3]	lens_less_than_1000[7]	4	1			T222	2		T289	1		T236	1
index[0x3]	lens_less_than_1000[8]	2	1			T5	1		T292	1		-	-
index[0x3]	lens_less_than_1000[9]	3	1			T73	1		T293	2		-	-
index[0x3]	len_2	3	1			T294	1		T295	1		T296	1