Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T3	1		T23	1		T17	2
class_index[0x1]	59	1			T15	2		T29	1		T60	1
class_index[0x2]	56	1			T15	1		T41	1		T59	1
class_index[0x3]	53	1			T27	2		T60	1		T30	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	85	1			T3	1		T17	2		T27	1
intr_timeout_cnt[1]	53	1			T15	3		T36	1		T30	2
intr_timeout_cnt[2]	24	1			T62	1		T48	1		T66	5
intr_timeout_cnt[3]	18	1			T23	1		T70	1		T51	1
intr_timeout_cnt[4]	10	1			T27	1		T68	1		T219	1
intr_timeout_cnt[5]	8	1			T48	1		T53	1		T220	1
intr_timeout_cnt[6]	5	1			T52	1		T54	2		T217	1
intr_timeout_cnt[7]	10	1			T59	2		T102	1		T221	1
intr_timeout_cnt[8]	9	1			T30	1		T51	1		T100	1
intr_timeout_cnt[9]	7	1			T219	1		T220	1		T104	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	33	1			T3	1		T17	2		T30	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T36	1		T49	1		T222	1
class_index[0x0]	intr_timeout_cnt[2]	4	1			T48	1		T67	1		T55	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T23	1		T223	1		T224	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T225	1		T173	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T54	2		T226	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T59	1		T227	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T104	1		T228	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	19	1			T29	1		T60	1		T64	1
class_index[0x1]	intr_timeout_cnt[1]	14	1			T15	2		T30	1		T49	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T66	1		T166	1		T217	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T173	1		T229	1		T230	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T217	1		T231	1		T232	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T48	1		T53	1		T220	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T221	1		T230	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T51	1		T55	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T219	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T41	1		T63	1		T97	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T15	1		T47	1		T70	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T62	1		T70	1		T217	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T233	1		T234	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T219	1		T235	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T227	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T217	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	5	1			T59	1		T102	1		T236	1
class_index[0x2]	intr_timeout_cnt[8]	4	1			T100	1		T55	1		T237	1
class_index[0x3]	intr_timeout_cnt[0]	13	1			T27	1		T60	1		T97	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T30	1		T48	2		T68	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T66	4		T238	1		T239	1
class_index[0x3]	intr_timeout_cnt[3]	7	1			T70	1		T51	1		T55	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T27	1		T68	1		T230	1
class_index[0x3]	intr_timeout_cnt[5]	1	1			T173	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T52	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T173	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T30	1		T240	1		T232	1
class_index[0x3]	intr_timeout_cnt[9]	4	1			T220	1		T73	1		T241	2