Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357660	1			T1	13		T3	11		T4	1917
all_values[1]	357660	1			T1	13		T3	11		T4	1917
all_values[2]	357660	1			T1	13		T3	11		T4	1917
all_values[3]	357660	1			T1	13		T3	11		T4	1917

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710536

1

T1

29

T3

22

T4

3834

auto[1]

720104

1

T1

23

T3

22

T4

3834

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

855495

1

T1

28

T3

39

T4

3898

auto[1]

575145

1

T1

24

T3

5

T4

3770

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101199	1			T1	6		T3	3		T4	476
all_values[0]	auto[0]	auto[1]	76227	1			T1	5		T3	2		T4	467
all_values[0]	auto[1]	auto[0]	103127	1			T1	1		T3	3		T4	489
all_values[0]	auto[1]	auto[1]	77107	1			T1	1		T3	3		T4	485
all_values[1]	auto[0]	auto[0]	108061	1			T1	4		T3	7		T4	516
all_values[1]	auto[0]	auto[1]	69943	1			T1	3		T4	466		T5	389
all_values[1]	auto[1]	auto[0]	109462	1			T1	3		T3	4		T4	486
all_values[1]	auto[1]	auto[1]	70194	1			T1	3		T4	449		T5	375
all_values[2]	auto[0]	auto[0]	107192	1			T1	2		T3	6		T4	468
all_values[2]	auto[0]	auto[1]	70524	1			T1	1		T4	467		T5	395
all_values[2]	auto[1]	auto[0]	108885	1			T1	5		T3	5		T4	493
all_values[2]	auto[1]	auto[1]	71059	1			T1	5		T4	489		T5	375
all_values[3]	auto[0]	auto[0]	107570	1			T1	4		T3	4		T4	493
all_values[3]	auto[0]	auto[1]	69820	1			T1	4		T4	481		T5	377
all_values[3]	auto[1]	auto[0]	109999	1			T1	3		T3	7		T4	477
all_values[3]	auto[1]	auto[1]	70271	1			T1	2		T4	466		T5	387