Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357660	1			T1	13		T3	11		T4	1917
all_pins[1]	357660	1			T1	13		T3	11		T4	1917
all_pins[2]	357660	1			T1	13		T3	11		T4	1917
all_pins[3]	357660	1			T1	13		T3	11		T4	1917

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1142008	1			T1	41		T3	41		T4	5779
values[0x1]	288632	1			T1	11		T3	3		T4	1889
transitions[0x0=>0x1]	191701	1			T1	7		T3	2		T4	1178
transitions[0x1=>0x0]	191972	1			T1	7		T3	3		T4	1178

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280553	1			T1	12		T3	8		T4	1432
all_pins[0]	values[0x1]	77107	1			T1	1		T3	3		T4	485
all_pins[0]	transitions[0x0=>0x1]	76467	1			T1	1		T3	2		T4	485
all_pins[0]	transitions[0x1=>0x0]	69903	1			T1	2		T4	466		T5	387
all_pins[1]	values[0x0]	287466	1			T1	10		T3	11		T4	1468
all_pins[1]	values[0x1]	70194	1			T1	3		T4	449		T5	375
all_pins[1]	transitions[0x0=>0x1]	38036	1			T1	3		T4	221		T5	197
all_pins[1]	transitions[0x1=>0x0]	44949	1			T1	1		T3	3		T4	257
all_pins[2]	values[0x0]	286601	1			T1	8		T3	11		T4	1428
all_pins[2]	values[0x1]	71059	1			T1	5		T4	489		T5	375
all_pins[2]	transitions[0x0=>0x1]	38870	1			T1	2		T4	252		T5	188
all_pins[2]	transitions[0x1=>0x0]	38005	1			T4	212		T5	188		T6	236
all_pins[3]	values[0x0]	287388	1			T1	11		T3	11		T4	1451
all_pins[3]	values[0x1]	70272	1			T1	2		T4	466		T5	387
all_pins[3]	transitions[0x0=>0x1]	38328	1			T1	1		T4	220		T5	209
all_pins[3]	transitions[0x1=>0x0]	39115	1			T1	4		T4	243		T5	197