Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T148	4		T149	4		T150	7
all_values[1]	284	1			T148	4		T149	4		T150	7
all_values[2]	284	1			T148	4		T149	4		T150	7
all_values[3]	284	1			T148	4		T149	4		T150	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605

1

T148

6

T149

6

T150

18

auto[1]

531

1

T148

10

T149

10

T150

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

446

1

T148

3

T149

5

T150

7

auto[1]

690

1

T148

13

T149

11

T150

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T148

7

T149

9

T150

14

auto[1]

461

1

T148

9

T149

7

T150

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

61

1

T215

1

T320

3

T321

1

all_values[0]

auto[0]

auto[0]

auto[1]

37

1

T148

1

T149

1

T150

3

all_values[0]

auto[0]

auto[1]

auto[0]

47

1

T148

2

T215

3

T320

1

all_values[0]

auto[0]

auto[1]

auto[1]

29

1

T150

1

T322

2

T321

2

all_values[0]

auto[1]

auto[0]

auto[1]

69

1

T148

1

T149

3

T150

2

all_values[0]

auto[1]

auto[1]

auto[1]

41

1

T150

1

T215

1

T323

2

all_values[1]

auto[0]

auto[0]

auto[0]

55

1

T149

1

T150

3

T215

3

all_values[1]

auto[0]

auto[0]

auto[1]

29

1

T150

1

T324

2

T325

1

all_values[1]

auto[0]

auto[1]

auto[0]

54

1

T149

1

T150

1

T215

1

all_values[1]

auto[0]

auto[1]

auto[1]

28

1

T148

1

T149

1

T320

1

all_values[1]

auto[1]

auto[0]

auto[1]

59

1

T148

2

T150

1

T215

2

all_values[1]

auto[1]

auto[1]

auto[1]

59

1

T148

1

T149

1

T150

1

all_values[2]

auto[0]

auto[0]

auto[0]

61

1

T320

1

T323

3

T321

3

all_values[2]

auto[0]

auto[0]

auto[1]

30

1

T150

1

T320

1

T323

1

all_values[2]

auto[0]

auto[1]

auto[0]

47

1

T149

1

T150

1

T215

2

all_values[2]

auto[0]

auto[1]

auto[1]

29

1

T148

1

T149

1

T215

1

all_values[2]

auto[1]

auto[0]

auto[1]

61

1

T150

2

T320

1

T323

2

all_values[2]

auto[1]

auto[1]

auto[1]

56

1

T148

3

T149

2

T150

3

all_values[3]

auto[0]

auto[0]

auto[0]

58

1

T148

1

T150

1

T215

1

all_values[3]

auto[0]

auto[0]

auto[1]

22

1

T150

1

T320

2

T322

2

all_values[3]

auto[0]

auto[1]

auto[0]

63

1

T149

2

T150

1

T215

1

all_values[3]

auto[0]

auto[1]

auto[1]

25

1

T148

1

T149

1

T215

2

all_values[3]

auto[1]

auto[0]

auto[1]

63

1

T148

1

T149

1

T150

3

all_values[3]

auto[1]

auto[1]

auto[1]

53

1

T148

1

T150

1

T215

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal