Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	88033	1			T4	1574		T5	636		T6	793
accum_cnt_1000	241080	1			T4	1477		T5	1462		T6	707
accum_cnt_100	30446	1			T4	56		T5	76		T6	46
accum_cnt_50	66970	1			T3	6		T4	41		T5	1241
accum_cnt_10	200457	1			T1	28		T3	4		T4	23
accum_cnt_0	391001	1			T1	20		T3	30		T4	1471

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	263637	1			T1	12		T3	10		T4	1457
class_index[0x1]	263637	1			T1	12		T3	10		T4	1457
class_index[0x2]	263637	1			T1	12		T3	10		T4	1457
class_index[0x3]	263637	1			T1	12		T3	10		T4	1457

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20925	1			T4	449		T5	78		T6	222
class_index[0x0]	accum_cnt_1000	58387	1			T4	409		T5	975		T6	215
class_index[0x0]	accum_cnt_100	8094	1			T4	25		T5	47		T6	14
class_index[0x0]	accum_cnt_50	20619	1			T3	6		T4	20		T5	49
class_index[0x0]	accum_cnt_10	55565	1			T1	5		T3	4		T4	10
class_index[0x0]	accum_cnt_0	89642	1			T1	7		T4	4		T5	2
class_index[0x1]	accum_cnt_2000	20666	1			T4	583		T17	182		T35	479
class_index[0x1]	accum_cnt_1000	62463	1			T4	546		T16	657		T17	332
class_index[0x1]	accum_cnt_100	7873	1			T15	79		T16	41		T17	43
class_index[0x1]	accum_cnt_50	13427	1			T6	1326		T15	75		T61	10
class_index[0x1]	accum_cnt_10	52117	1			T1	8		T4	4		T5	1170
class_index[0x1]	accum_cnt_0	96317	1			T1	4		T3	10		T4	2
class_index[0x2]	accum_cnt_2000	23292	1			T4	542		T5	558		T6	571
class_index[0x2]	accum_cnt_1000	58160	1			T4	522		T5	487		T6	492
class_index[0x2]	accum_cnt_100	6782	1			T4	31		T5	29		T6	32
class_index[0x2]	accum_cnt_50	17420	1			T4	21		T5	28		T6	21
class_index[0x2]	accum_cnt_10	48490	1			T1	5		T4	8		T5	11
class_index[0x2]	accum_cnt_0	102808	1			T1	7		T3	10		T4	9
class_index[0x3]	accum_cnt_2000	23150	1			T16	291		T35	268		T40	212
class_index[0x3]	accum_cnt_1000	62070	1			T7	1045		T15	23		T16	403
class_index[0x3]	accum_cnt_100	7697	1			T7	94		T15	25		T16	24
class_index[0x3]	accum_cnt_50	15504	1			T5	1164		T7	63		T15	19
class_index[0x3]	accum_cnt_10	44285	1			T1	10		T4	1		T5	6
class_index[0x3]	accum_cnt_0	102234	1			T1	2		T3	10		T4	1456