Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4879	1			T29	497		T42	422		T60	8
alert[0x1]	11621	1			T17	20		T29	7		T42	14
alert[0x2]	4395	1			T6	5		T17	78		T9	1
alert[0x3]	6408	1			T4	22		T9	1		T11	1
alert[0x4]	11256	1			T95	104		T201	1		T207	841
alert[0x5]	9121	1			T6	2		T8	1		T42	103
alert[0x6]	7608	1			T7	1		T15	2		T95	8
alert[0x7]	3583	1			T15	1		T17	4		T10	1
alert[0x8]	8056	1			T17	26		T10	1		T41	1
alert[0x9]	7090	1			T17	1		T11	1		T28	28
alert[0xa]	7848	1			T4	16		T15	12		T95	18
alert[0xb]	6495	1			T4	11		T17	25		T10	1
alert[0xc]	7185	1			T15	2		T249	1		T201	2
alert[0xd]	10343	1			T95	13		T42	3939		T45	7
alert[0xe]	2667	1			T17	28		T9	1		T95	8
alert[0xf]	10750	1			T6	17		T17	15		T41	3
alert[0x10]	4633	1			T20	2		T17	20		T95	53
alert[0x11]	14018	1			T17	10		T60	9		T68	117
alert[0x12]	9062	1			T4	7		T17	2		T41	6
alert[0x13]	13960	1			T15	42		T8	1		T29	288
alert[0x14]	4758	1			T7	1		T17	2		T10	1
alert[0x15]	3540	1			T72	1		T95	177		T42	199
alert[0x16]	4538	1			T4	13		T11	1		T95	98
alert[0x17]	7138	1			T4	2		T6	3		T17	5
alert[0x18]	9871	1			T6	4		T17	2		T9	1
alert[0x19]	9864	1			T6	1		T15	170		T42	49
alert[0x1a]	6242	1			T20	5		T9	1		T95	211
alert[0x1b]	3421	1			T6	2		T95	7		T42	8
alert[0x1c]	7642	1			T11	1		T41	14		T42	1462
alert[0x1d]	3604	1			T17	1		T95	35		T29	6
alert[0x1e]	10087	1			T17	42		T11	1		T29	13
alert[0x1f]	5065	1			T4	4		T95	6		T29	75
alert[0x20]	8336	1			T10	1		T95	10		T42	307
alert[0x21]	3835	1			T15	42		T17	6		T95	4
alert[0x22]	4415	1			T6	7		T17	23		T41	11
alert[0x23]	2322	1			T6	5		T15	7		T17	8
alert[0x24]	5263	1			T4	2		T15	23		T17	53
alert[0x25]	14835	1			T15	3		T9	1		T42	194
alert[0x26]	8957	1			T15	4		T95	28		T42	43
alert[0x27]	20354	1			T9	1		T95	178		T41	1
alert[0x28]	5625	1			T17	1		T10	1		T95	133
alert[0x29]	4276	1			T17	3		T9	1		T11	1
alert[0x2a]	9900	1			T42	4557		T59	11		T45	362
alert[0x2b]	3782	1			T9	1		T29	49		T45	138
alert[0x2c]	11546	1			T4	15		T6	3		T17	14
alert[0x2d]	5331	1			T17	7		T9	1		T10	2
alert[0x2e]	6112	1			T6	1		T17	1		T95	6
alert[0x2f]	2641	1			T4	50		T17	4		T10	1
alert[0x30]	6836	1			T15	1		T95	38		T45	540
alert[0x31]	8733	1			T4	1		T17	3		T29	4
alert[0x32]	7800	1			T4	111		T15	9		T9	1
alert[0x33]	6062	1			T15	3		T27	9		T95	247
alert[0x34]	4636	1			T4	1		T6	17		T11	1
alert[0x35]	7409	1			T17	14		T95	22		T60	96
alert[0x36]	12843	1			T6	2		T15	11		T41	6
alert[0x37]	3388	1			T6	6		T20	4		T9	1
alert[0x38]	5313	1			T15	1		T95	51		T68	20
alert[0x39]	3774	1			T6	6		T23	37		T17	3
alert[0x3a]	2103	1			T95	4		T250	4		T251	1
alert[0x3b]	6960	1			T15	2		T17	3		T42	1977
alert[0x3c]	4133	1			T11	1		T95	19		T29	21
alert[0x3d]	9804	1			T11	1		T42	7		T28	10
alert[0x3e]	8941	1			T41	5		T30	33		T249	1
alert[0x3f]	10049	1			T6	3		T27	2		T95	45
alert[0x40]	3384	1			T17	10		T9	1		T95	80

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	119962	1			T6	17		T15	335		T23	37
class_i[0x1]	128009	1			T4	112		T6	6		T7	2
class_i[0x2]	105278	1			T4	7		T6	18		T20	11
class_i[0x3]	113197	1			T4	136		T6	43		T8	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

465794

1

T4

255

T6

84

T20

11

alert_ping_fail

652

1

T7

2

T8

2

T9

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4867	1			T29	497		T42	422		T60	8
alert_integrity_fail	alert[0x1]	11613	1			T17	20		T29	7		T42	14
alert_integrity_fail	alert[0x2]	4386	1			T6	5		T17	78		T95	21
alert_integrity_fail	alert[0x3]	6399	1			T4	22		T42	1087		T68	20
alert_integrity_fail	alert[0x4]	11243	1			T95	104		T207	841		T252	8
alert_integrity_fail	alert[0x5]	9115	1			T6	2		T42	103		T60	1679
alert_integrity_fail	alert[0x6]	7595	1			T15	2		T95	8		T30	76
alert_integrity_fail	alert[0x7]	3574	1			T15	1		T17	4		T41	51
alert_integrity_fail	alert[0x8]	8047	1			T17	26		T41	1		T60	27
alert_integrity_fail	alert[0x9]	7083	1			T17	1		T28	28		T30	2
alert_integrity_fail	alert[0xa]	7832	1			T4	16		T15	12		T95	18
alert_integrity_fail	alert[0xb]	6482	1			T4	11		T17	25		T42	10
alert_integrity_fail	alert[0xc]	7177	1			T15	2		T70	134		T207	152
alert_integrity_fail	alert[0xd]	10334	1			T95	13		T42	3939		T45	7
alert_integrity_fail	alert[0xe]	2655	1			T17	28		T95	8		T41	3
alert_integrity_fail	alert[0xf]	10739	1			T6	17		T17	15		T41	3
alert_integrity_fail	alert[0x10]	4627	1			T20	2		T17	20		T95	53
alert_integrity_fail	alert[0x11]	14013	1			T17	10		T60	9		T68	117
alert_integrity_fail	alert[0x12]	9053	1			T4	7		T17	2		T41	6
alert_integrity_fail	alert[0x13]	13946	1			T15	42		T29	288		T42	60
alert_integrity_fail	alert[0x14]	4741	1			T17	2		T95	572		T41	8
alert_integrity_fail	alert[0x15]	3528	1			T95	177		T42	199		T45	38
alert_integrity_fail	alert[0x16]	4525	1			T4	13		T95	98		T41	8
alert_integrity_fail	alert[0x17]	7130	1			T4	2		T6	3		T17	5
alert_integrity_fail	alert[0x18]	9860	1			T6	4		T17	2		T95	41
alert_integrity_fail	alert[0x19]	9857	1			T6	1		T15	170		T42	49
alert_integrity_fail	alert[0x1a]	6234	1			T20	5		T95	211		T29	31
alert_integrity_fail	alert[0x1b]	3407	1			T6	2		T95	7		T42	8
alert_integrity_fail	alert[0x1c]	7634	1			T41	14		T42	1462		T28	1
alert_integrity_fail	alert[0x1d]	3589	1			T17	1		T95	35		T29	6
alert_integrity_fail	alert[0x1e]	10084	1			T17	42		T29	13		T42	419
alert_integrity_fail	alert[0x1f]	5053	1			T4	4		T95	6		T29	75
alert_integrity_fail	alert[0x20]	8327	1			T95	10		T42	307		T97	1
alert_integrity_fail	alert[0x21]	3826	1			T15	42		T17	6		T95	4
alert_integrity_fail	alert[0x22]	4404	1			T6	7		T17	23		T41	11
alert_integrity_fail	alert[0x23]	2308	1			T6	5		T15	7		T17	8
alert_integrity_fail	alert[0x24]	5256	1			T4	2		T15	23		T17	53
alert_integrity_fail	alert[0x25]	14826	1			T15	3		T42	194		T59	1
alert_integrity_fail	alert[0x26]	8947	1			T15	4		T95	28		T42	43
alert_integrity_fail	alert[0x27]	20339	1			T95	178		T41	1		T42	188
alert_integrity_fail	alert[0x28]	5608	1			T17	1		T95	133		T29	78
alert_integrity_fail	alert[0x29]	4266	1			T17	3		T29	1		T45	26
alert_integrity_fail	alert[0x2a]	9890	1			T42	4557		T59	11		T45	362
alert_integrity_fail	alert[0x2b]	3773	1			T29	49		T45	138		T49	9
alert_integrity_fail	alert[0x2c]	11532	1			T4	15		T6	3		T17	14
alert_integrity_fail	alert[0x2d]	5314	1			T17	7		T95	21		T42	72
alert_integrity_fail	alert[0x2e]	6097	1			T6	1		T17	1		T95	6
alert_integrity_fail	alert[0x2f]	2632	1			T4	50		T17	4		T41	3
alert_integrity_fail	alert[0x30]	6822	1			T15	1		T95	38		T45	540
alert_integrity_fail	alert[0x31]	8728	1			T4	1		T17	3		T29	4
alert_integrity_fail	alert[0x32]	7787	1			T4	111		T15	9		T95	11
alert_integrity_fail	alert[0x33]	6058	1			T15	3		T27	9		T95	247
alert_integrity_fail	alert[0x34]	4627	1			T4	1		T6	17		T95	14
alert_integrity_fail	alert[0x35]	7404	1			T17	14		T95	22		T60	96
alert_integrity_fail	alert[0x36]	12836	1			T6	2		T15	11		T41	6
alert_integrity_fail	alert[0x37]	3376	1			T6	6		T20	4		T41	3
alert_integrity_fail	alert[0x38]	5307	1			T15	1		T95	51		T68	20
alert_integrity_fail	alert[0x39]	3761	1			T6	6		T23	37		T17	3
alert_integrity_fail	alert[0x3a]	2097	1			T95	4		T250	4		T49	6
alert_integrity_fail	alert[0x3b]	6953	1			T15	2		T17	3		T42	1977
alert_integrity_fail	alert[0x3c]	4125	1			T95	19		T29	21		T60	4
alert_integrity_fail	alert[0x3d]	9799	1			T42	7		T28	10		T250	1
alert_integrity_fail	alert[0x3e]	8929	1			T41	5		T30	33		T47	1
alert_integrity_fail	alert[0x3f]	10046	1			T6	3		T27	2		T95	45
alert_integrity_fail	alert[0x40]	3372	1			T17	10		T95	80		T250	3
alert_ping_fail	alert[0x0]	12	1			T249	1		T202	1		T253	2
alert_ping_fail	alert[0x1]	8	1			T254	1		T253	1		T255	1
alert_ping_fail	alert[0x2]	9	1			T9	1		T249	1		T202	1
alert_ping_fail	alert[0x3]	9	1			T9	1		T11	1		T256	2
alert_ping_fail	alert[0x4]	13	1			T201	1		T257	1		T258	1
alert_ping_fail	alert[0x5]	6	1			T8	1		T259	1		T255	1
alert_ping_fail	alert[0x6]	13	1			T7	1		T260	1		T261	1
alert_ping_fail	alert[0x7]	9	1			T10	1		T249	1		T254	1
alert_ping_fail	alert[0x8]	9	1			T10	1		T249	1		T262	1
alert_ping_fail	alert[0x9]	7	1			T11	1		T254	1		T82	1
alert_ping_fail	alert[0xa]	16	1			T212	1		T254	1		T169	3
alert_ping_fail	alert[0xb]	13	1			T10	1		T212	1		T202	1
alert_ping_fail	alert[0xc]	8	1			T249	1		T201	2		T251	1
alert_ping_fail	alert[0xd]	9	1			T249	2		T202	2		T263	1
alert_ping_fail	alert[0xe]	12	1			T9	1		T212	1		T202	1
alert_ping_fail	alert[0xf]	11	1			T257	1		T264	1		T265	1
alert_ping_fail	alert[0x10]	6	1			T249	1		T202	1		T257	1
alert_ping_fail	alert[0x11]	5	1			T202	1		T260	1		T266	1
alert_ping_fail	alert[0x12]	9	1			T249	1		T212	1		T267	1
alert_ping_fail	alert[0x13]	14	1			T8	1		T268	1		T202	1
alert_ping_fail	alert[0x14]	17	1			T7	1		T10	1		T244	1
alert_ping_fail	alert[0x15]	12	1			T72	1		T212	2		T256	2
alert_ping_fail	alert[0x16]	13	1			T11	1		T245	1		T246	1
alert_ping_fail	alert[0x17]	8	1			T10	1		T254	1		T82	1
alert_ping_fail	alert[0x18]	11	1			T9	1		T212	1		T202	1
alert_ping_fail	alert[0x19]	7	1			T256	1		T263	1		T269	1
alert_ping_fail	alert[0x1a]	8	1			T9	1		T266	1		T270	1
alert_ping_fail	alert[0x1b]	14	1			T249	1		T212	2		T251	1
alert_ping_fail	alert[0x1c]	8	1			T11	1		T265	1		T270	1
alert_ping_fail	alert[0x1d]	15	1			T268	1		T212	1		T261	1
alert_ping_fail	alert[0x1e]	3	1			T11	1		T202	1		T271	1
alert_ping_fail	alert[0x1f]	12	1			T212	2		T202	1		T256	1
alert_ping_fail	alert[0x20]	9	1			T10	1		T249	1		T251	1
alert_ping_fail	alert[0x21]	9	1			T169	1		T264	1		T269	1
alert_ping_fail	alert[0x22]	11	1			T260	1		T254	2		T272	3
alert_ping_fail	alert[0x23]	14	1			T212	1		T202	1		T256	1
alert_ping_fail	alert[0x24]	7	1			T11	1		T268	1		T251	1
alert_ping_fail	alert[0x25]	9	1			T9	1		T212	2		T201	1
alert_ping_fail	alert[0x26]	10	1			T212	1		T202	1		T251	1
alert_ping_fail	alert[0x27]	15	1			T9	1		T202	1		T264	1
alert_ping_fail	alert[0x28]	17	1			T10	1		T201	1		T251	1
alert_ping_fail	alert[0x29]	10	1			T9	1		T11	1		T257	2
alert_ping_fail	alert[0x2a]	10	1			T81	1		T266	1		T254	1
alert_ping_fail	alert[0x2b]	9	1			T9	1		T264	1		T270	1
alert_ping_fail	alert[0x2c]	14	1			T202	1		T273	1		T274	1
alert_ping_fail	alert[0x2d]	17	1			T9	1		T10	2		T266	1
alert_ping_fail	alert[0x2e]	15	1			T243	1		T251	1		T260	1
alert_ping_fail	alert[0x2f]	9	1			T10	1		T249	1		T201	1
alert_ping_fail	alert[0x30]	14	1			T212	1		T258	1		T266	1
alert_ping_fail	alert[0x31]	5	1			T274	1		T275	2		T276	1
alert_ping_fail	alert[0x32]	13	1			T9	1		T10	1		T256	1
alert_ping_fail	alert[0x33]	4	1			T258	1		T269	1		T276	1
alert_ping_fail	alert[0x34]	9	1			T11	1		T202	1		T253	1
alert_ping_fail	alert[0x35]	5	1			T256	1		T266	1		T270	1
alert_ping_fail	alert[0x36]	7	1			T202	1		T82	1		T264	1
alert_ping_fail	alert[0x37]	12	1			T9	1		T10	1		T260	1
alert_ping_fail	alert[0x38]	6	1			T201	2		T202	2		T270	1
alert_ping_fail	alert[0x39]	13	1			T11	3		T212	2		T256	1
alert_ping_fail	alert[0x3a]	6	1			T251	1		T266	1		T253	1
alert_ping_fail	alert[0x3b]	7	1			T262	1		T276	1		T277	1
alert_ping_fail	alert[0x3c]	8	1			T11	1		T260	1		T274	1
alert_ping_fail	alert[0x3d]	5	1			T11	1		T82	1		T264	1
alert_ping_fail	alert[0x3e]	12	1			T249	1		T212	1		T202	1
alert_ping_fail	alert[0x3f]	3	1			T256	1		T278	1		T279	1
alert_ping_fail	alert[0x40]	12	1			T9	1		T251	1		T260	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	119786	1			T6	17		T15	335		T23	37
alert_integrity_fail	class_i[0x1]	127860	1			T4	112		T6	6		T17	428
alert_integrity_fail	class_i[0x2]	105124	1			T4	7		T6	18		T20	11
alert_integrity_fail	class_i[0x3]	113024	1			T4	136		T6	43		T17	4
alert_ping_fail	class_i[0x0]	176	1			T9	12		T11	12		T243	1
alert_ping_fail	class_i[0x1]	149	1			T7	2		T10	1		T72	1
alert_ping_fail	class_i[0x2]	154	1			T9	1		T245	1		T246	1
alert_ping_fail	class_i[0x3]	173	1			T8	2		T10	11		T212	19