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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.66 100.00 100.00 100.00 99.38 99.64


Total test records in report: 831
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T770 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4108724975 Jul 03 06:05:04 PM PDT 24 Jul 03 06:05:52 PM PDT 24 1403342303 ps
T771 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2835620842 Jul 03 06:05:28 PM PDT 24 Jul 03 06:05:35 PM PDT 24 68263276 ps
T772 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2019079871 Jul 03 06:04:49 PM PDT 24 Jul 03 06:05:04 PM PDT 24 261789566 ps
T124 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1725290984 Jul 03 06:05:14 PM PDT 24 Jul 03 06:15:52 PM PDT 24 33624499623 ps
T120 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3783779068 Jul 03 06:04:55 PM PDT 24 Jul 03 06:12:48 PM PDT 24 36298147510 ps
T154 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.425134150 Jul 03 06:04:43 PM PDT 24 Jul 03 06:05:04 PM PDT 24 152573515 ps
T137 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3186078288 Jul 03 06:04:46 PM PDT 24 Jul 03 06:24:15 PM PDT 24 15910673621 ps
T773 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3393537432 Jul 03 06:05:23 PM PDT 24 Jul 03 06:05:28 PM PDT 24 123302321 ps
T774 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3994691801 Jul 03 06:04:54 PM PDT 24 Jul 03 06:04:59 PM PDT 24 263794821 ps
T135 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.809988966 Jul 03 06:05:24 PM PDT 24 Jul 03 06:26:21 PM PDT 24 30628547474 ps
T775 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2734661638 Jul 03 06:05:14 PM PDT 24 Jul 03 06:05:17 PM PDT 24 98928038 ps
T776 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3155068145 Jul 03 06:05:05 PM PDT 24 Jul 03 06:05:12 PM PDT 24 211839703 ps
T777 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1803847923 Jul 03 06:04:57 PM PDT 24 Jul 03 06:05:36 PM PDT 24 484788190 ps
T778 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3861200668 Jul 03 06:05:22 PM PDT 24 Jul 03 06:05:24 PM PDT 24 9948938 ps
T779 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3492918884 Jul 03 06:04:53 PM PDT 24 Jul 03 06:07:46 PM PDT 24 2887501769 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.777246740 Jul 03 06:04:46 PM PDT 24 Jul 03 06:13:49 PM PDT 24 50230919684 ps
T781 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2949358222 Jul 03 06:04:46 PM PDT 24 Jul 03 06:07:55 PM PDT 24 2879048820 ps
T782 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1897699232 Jul 03 06:05:23 PM PDT 24 Jul 03 06:05:25 PM PDT 24 19396563 ps
T138 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2079443814 Jul 03 06:05:02 PM PDT 24 Jul 03 06:23:28 PM PDT 24 15141921827 ps
T132 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2047069929 Jul 03 06:05:02 PM PDT 24 Jul 03 06:10:01 PM PDT 24 16271546795 ps
T783 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.710871067 Jul 03 06:05:02 PM PDT 24 Jul 03 06:05:14 PM PDT 24 1943883051 ps
T134 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.646471395 Jul 03 06:05:14 PM PDT 24 Jul 03 06:09:01 PM PDT 24 11269656981 ps
T784 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.947905940 Jul 03 06:05:30 PM PDT 24 Jul 03 06:05:33 PM PDT 24 10525742 ps
T785 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1173575160 Jul 03 06:05:27 PM PDT 24 Jul 03 06:05:53 PM PDT 24 664665396 ps
T786 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3747789794 Jul 03 06:04:59 PM PDT 24 Jul 03 06:05:00 PM PDT 24 16341148 ps
T787 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1450291726 Jul 03 06:04:51 PM PDT 24 Jul 03 06:04:55 PM PDT 24 62374985 ps
T133 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1646682295 Jul 03 06:04:44 PM PDT 24 Jul 03 06:08:25 PM PDT 24 3549193684 ps
T788 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3427416649 Jul 03 06:04:49 PM PDT 24 Jul 03 06:04:54 PM PDT 24 92771874 ps
T789 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2069470348 Jul 03 06:04:46 PM PDT 24 Jul 03 06:10:27 PM PDT 24 27109244078 ps
T790 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1544307032 Jul 03 06:05:08 PM PDT 24 Jul 03 06:05:14 PM PDT 24 69862121 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2668440443 Jul 03 06:04:56 PM PDT 24 Jul 03 06:05:04 PM PDT 24 118183622 ps
T792 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1678035292 Jul 03 06:05:29 PM PDT 24 Jul 03 06:05:31 PM PDT 24 9892878 ps
T793 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.136530493 Jul 03 06:05:36 PM PDT 24 Jul 03 06:05:38 PM PDT 24 13400644 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.552389826 Jul 03 06:05:08 PM PDT 24 Jul 03 06:05:15 PM PDT 24 73967275 ps
T795 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2883346529 Jul 03 06:05:05 PM PDT 24 Jul 03 06:05:58 PM PDT 24 1333893491 ps
T142 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3384350737 Jul 03 06:05:25 PM PDT 24 Jul 03 06:08:04 PM PDT 24 2412139572 ps
T796 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1943041 Jul 03 06:05:22 PM PDT 24 Jul 03 06:05:46 PM PDT 24 684742646 ps
T797 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3502829338 Jul 03 06:05:16 PM PDT 24 Jul 03 06:05:17 PM PDT 24 6324087 ps
T798 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.657088909 Jul 03 06:05:26 PM PDT 24 Jul 03 06:05:37 PM PDT 24 154843406 ps
T799 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3176192140 Jul 03 06:04:51 PM PDT 24 Jul 03 06:05:04 PM PDT 24 377902402 ps
T136 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2555815485 Jul 03 06:05:21 PM PDT 24 Jul 03 06:12:09 PM PDT 24 11776683484 ps
T800 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1852595685 Jul 03 06:05:14 PM PDT 24 Jul 03 06:05:21 PM PDT 24 59534316 ps
T801 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1215634615 Jul 03 06:05:28 PM PDT 24 Jul 03 06:05:30 PM PDT 24 8089209 ps
T802 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2065295420 Jul 03 06:05:20 PM PDT 24 Jul 03 06:05:34 PM PDT 24 114834431 ps
T803 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3065907451 Jul 03 06:04:52 PM PDT 24 Jul 03 06:04:59 PM PDT 24 123705497 ps
T804 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2983818596 Jul 03 06:05:34 PM PDT 24 Jul 03 06:05:36 PM PDT 24 64248422 ps
T805 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2778711096 Jul 03 06:04:58 PM PDT 24 Jul 03 06:06:09 PM PDT 24 1988030165 ps
T139 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.824424805 Jul 03 06:04:54 PM PDT 24 Jul 03 06:07:50 PM PDT 24 2523701878 ps
T806 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1215489486 Jul 03 06:04:53 PM PDT 24 Jul 03 06:04:55 PM PDT 24 15757161 ps
T807 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1369615730 Jul 03 06:04:55 PM PDT 24 Jul 03 06:04:57 PM PDT 24 18638587 ps
T165 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.999044474 Jul 03 06:04:59 PM PDT 24 Jul 03 06:05:04 PM PDT 24 303790503 ps
T808 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3616818560 Jul 03 06:05:12 PM PDT 24 Jul 03 06:05:31 PM PDT 24 1040855097 ps
T809 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1707080202 Jul 03 06:05:02 PM PDT 24 Jul 03 06:05:03 PM PDT 24 14865524 ps
T810 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3676981333 Jul 03 06:05:26 PM PDT 24 Jul 03 06:08:02 PM PDT 24 2308340155 ps
T811 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.276658622 Jul 03 06:05:07 PM PDT 24 Jul 03 06:05:09 PM PDT 24 9485155 ps
T812 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1631544940 Jul 03 06:05:14 PM PDT 24 Jul 03 06:05:20 PM PDT 24 33895025 ps
T164 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.932698599 Jul 03 06:05:20 PM PDT 24 Jul 03 06:05:24 PM PDT 24 60096954 ps
T813 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3713413785 Jul 03 06:04:48 PM PDT 24 Jul 03 06:04:49 PM PDT 24 19940105 ps
T814 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3704068998 Jul 03 06:04:57 PM PDT 24 Jul 03 06:05:26 PM PDT 24 1679401235 ps
T141 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.509790801 Jul 03 06:05:11 PM PDT 24 Jul 03 06:13:38 PM PDT 24 23822399887 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.455311564 Jul 03 06:05:16 PM PDT 24 Jul 03 06:11:21 PM PDT 24 2525973865 ps
T143 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1138435857 Jul 03 06:04:48 PM PDT 24 Jul 03 06:15:24 PM PDT 24 8414481094 ps
T816 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3890815460 Jul 03 06:05:01 PM PDT 24 Jul 03 06:05:10 PM PDT 24 181549955 ps
T817 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1852263388 Jul 03 06:05:21 PM PDT 24 Jul 03 06:05:29 PM PDT 24 312972502 ps
T818 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3083194136 Jul 03 06:05:27 PM PDT 24 Jul 03 06:05:29 PM PDT 24 11446139 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.54404850 Jul 03 06:05:09 PM PDT 24 Jul 03 06:05:17 PM PDT 24 237246231 ps
T820 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1609610107 Jul 03 06:05:33 PM PDT 24 Jul 03 06:05:34 PM PDT 24 7570206 ps
T821 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2201021224 Jul 03 06:04:46 PM PDT 24 Jul 03 06:04:56 PM PDT 24 140055853 ps
T822 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.267821835 Jul 03 06:04:49 PM PDT 24 Jul 03 06:04:53 PM PDT 24 50871157 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.333593060 Jul 03 06:05:03 PM PDT 24 Jul 03 06:13:11 PM PDT 24 26513475139 ps
T824 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1178497514 Jul 03 06:05:29 PM PDT 24 Jul 03 06:05:31 PM PDT 24 10194635 ps
T825 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2407845015 Jul 03 06:05:34 PM PDT 24 Jul 03 06:05:36 PM PDT 24 6842765 ps
T163 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3632247858 Jul 03 06:05:18 PM PDT 24 Jul 03 06:05:53 PM PDT 24 1257513315 ps
T140 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1517441349 Jul 03 06:05:19 PM PDT 24 Jul 03 06:10:29 PM PDT 24 6984989483 ps
T826 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.506894265 Jul 03 06:05:35 PM PDT 24 Jul 03 06:05:36 PM PDT 24 11818910 ps
T144 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1230881503 Jul 03 06:04:54 PM PDT 24 Jul 03 06:07:56 PM PDT 24 8473148789 ps
T827 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1055831157 Jul 03 06:05:02 PM PDT 24 Jul 03 06:05:09 PM PDT 24 51122228 ps
T828 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3110545009 Jul 03 06:04:47 PM PDT 24 Jul 03 06:04:56 PM PDT 24 218350415 ps
T829 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.744819201 Jul 03 06:05:35 PM PDT 24 Jul 03 06:05:37 PM PDT 24 8295596 ps
T830 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1639853731 Jul 03 06:05:02 PM PDT 24 Jul 03 06:05:09 PM PDT 24 75888306 ps
T831 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2968275503 Jul 03 06:05:28 PM PDT 24 Jul 03 06:05:29 PM PDT 24 8646997 ps

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2129554799
Short name T15
Test name
Test status
Simulation time 125504778752 ps
CPU time 2115.99 seconds
Started Jul 03 06:19:11 PM PDT 24
Finished Jul 03 06:54:27 PM PDT 24
Peak memory 290492 kb
Host smart-10dba025-9260-47a2-9539-fba715c0fedf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129554799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2129554799
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3596403894
Short name T12
Test name
Test status
Simulation time 432419922 ps
CPU time 24.13 seconds
Started Jul 03 06:15:41 PM PDT 24
Finished Jul 03 06:16:06 PM PDT 24
Peak memory 271508 kb
Host smart-584df145-ee45-4063-8540-5dca453ab37c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3596403894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3596403894
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.916431703
Short name T17
Test name
Test status
Simulation time 59877291478 ps
CPU time 2466.88 seconds
Started Jul 03 06:15:25 PM PDT 24
Finished Jul 03 06:56:33 PM PDT 24
Peak memory 306296 kb
Host smart-866b8c38-eb18-4d60-a484-974f7af628f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916431703 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.916431703
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1309168791
Short name T174
Test name
Test status
Simulation time 877050534 ps
CPU time 10.36 seconds
Started Jul 03 06:05:00 PM PDT 24
Finished Jul 03 06:05:10 PM PDT 24
Peak memory 237616 kb
Host smart-0a13e9c4-caac-4616-b5bc-edee7b292fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1309168791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1309168791
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2673122718
Short name T97
Test name
Test status
Simulation time 61478724524 ps
CPU time 3584.04 seconds
Started Jul 03 06:17:56 PM PDT 24
Finished Jul 03 07:17:40 PM PDT 24
Peak memory 290296 kb
Host smart-d828f8fa-f3cf-4602-b012-bfcc5d43e5c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673122718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2673122718
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2635700807
Short name T113
Test name
Test status
Simulation time 4295721478 ps
CPU time 663.56 seconds
Started Jul 03 06:05:08 PM PDT 24
Finished Jul 03 06:16:11 PM PDT 24
Peak memory 265396 kb
Host smart-5a3458aa-14c6-4230-b8ab-95eaf9e3656a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635700807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2635700807
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3462889279
Short name T4
Test name
Test status
Simulation time 84716137896 ps
CPU time 1621.88 seconds
Started Jul 03 06:19:12 PM PDT 24
Finished Jul 03 06:46:14 PM PDT 24
Peak memory 288620 kb
Host smart-414cbbd8-2e11-46d6-b4cc-10f242b00eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462889279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3462889279
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.176307558
Short name T77
Test name
Test status
Simulation time 772507847960 ps
CPU time 4331.72 seconds
Started Jul 03 06:16:59 PM PDT 24
Finished Jul 03 07:29:12 PM PDT 24
Peak memory 306916 kb
Host smart-3951a212-ab9a-462a-931f-6c2f1d81ca36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176307558 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.176307558
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2404000654
Short name T8
Test name
Test status
Simulation time 133375015904 ps
CPU time 2030.57 seconds
Started Jul 03 06:15:38 PM PDT 24
Finished Jul 03 06:49:29 PM PDT 24
Peak memory 283208 kb
Host smart-e677e319-6f59-46a8-83e2-129b84fbc7a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404000654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2404000654
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2422171012
Short name T127
Test name
Test status
Simulation time 61379652667 ps
CPU time 715.28 seconds
Started Jul 03 06:04:48 PM PDT 24
Finished Jul 03 06:16:44 PM PDT 24
Peak memory 266452 kb
Host smart-6efe97bf-a8f7-4f71-b0bb-3d7b6e68a1c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422171012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2422171012
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.566833224
Short name T82
Test name
Test status
Simulation time 32826609401 ps
CPU time 364.14 seconds
Started Jul 03 06:18:38 PM PDT 24
Finished Jul 03 06:24:43 PM PDT 24
Peak memory 249352 kb
Host smart-1b231fe1-b4cb-43bb-868b-db9a63ffd38d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566833224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.566833224
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2306739311
Short name T18
Test name
Test status
Simulation time 514969774 ps
CPU time 13.16 seconds
Started Jul 03 06:14:59 PM PDT 24
Finished Jul 03 06:15:12 PM PDT 24
Peak memory 249220 kb
Host smart-5765543c-0e8b-408c-9701-db9ba39d6ceb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2306739311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2306739311
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4019772049
Short name T109
Test name
Test status
Simulation time 12639978542 ps
CPU time 982.73 seconds
Started Jul 03 06:05:19 PM PDT 24
Finished Jul 03 06:21:42 PM PDT 24
Peak memory 273052 kb
Host smart-facd41a1-d6a7-4713-8c5a-d3b8ee215c44
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019772049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4019772049
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.4134099604
Short name T52
Test name
Test status
Simulation time 853284567900 ps
CPU time 4438.79 seconds
Started Jul 03 06:14:58 PM PDT 24
Finished Jul 03 07:28:58 PM PDT 24
Peak memory 306584 kb
Host smart-4f458111-e671-40c6-939e-dfeb6c2eb81a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134099604 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.4134099604
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2047069929
Short name T132
Test name
Test status
Simulation time 16271546795 ps
CPU time 298.38 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:10:01 PM PDT 24
Peak memory 271608 kb
Host smart-76c5d0e4-a49b-40f8-b890-919665a25973
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2047069929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2047069929
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1872812739
Short name T73
Test name
Test status
Simulation time 28659270992 ps
CPU time 1877.74 seconds
Started Jul 03 06:17:49 PM PDT 24
Finished Jul 03 06:49:07 PM PDT 24
Peak memory 286408 kb
Host smart-80faae4a-38ef-4df2-a62d-b4da2838cda7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872812739 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1872812739
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1646641343
Short name T155
Test name
Test status
Simulation time 861133129 ps
CPU time 26.33 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:05:18 PM PDT 24
Peak memory 237672 kb
Host smart-7857fba3-b1c2-452a-a0ca-d5c1e5aad691
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1646641343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1646641343
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3930869631
Short name T243
Test name
Test status
Simulation time 275658241220 ps
CPU time 2765.81 seconds
Started Jul 03 06:20:25 PM PDT 24
Finished Jul 03 07:06:31 PM PDT 24
Peak memory 290368 kb
Host smart-feebe47c-36e8-425b-966a-80f671495902
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930869631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3930869631
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3883190801
Short name T150
Test name
Test status
Simulation time 8480410 ps
CPU time 1.52 seconds
Started Jul 03 06:05:14 PM PDT 24
Finished Jul 03 06:05:16 PM PDT 24
Peak memory 236688 kb
Host smart-abe7adef-6c13-4bac-be9a-2551dc7bdfcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3883190801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3883190801
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3013807553
Short name T129
Test name
Test status
Simulation time 9523737314 ps
CPU time 326 seconds
Started Jul 03 06:04:56 PM PDT 24
Finished Jul 03 06:10:22 PM PDT 24
Peak memory 265480 kb
Host smart-18632a43-2ba5-4c0e-b3d0-f60067a445a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3013807553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3013807553
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.158358734
Short name T202
Test name
Test status
Simulation time 28451314013 ps
CPU time 553.28 seconds
Started Jul 03 06:15:10 PM PDT 24
Finished Jul 03 06:24:23 PM PDT 24
Peak memory 256032 kb
Host smart-e1c9453d-35ad-4104-be57-3873bc7ccc0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158358734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.158358734
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3470027534
Short name T169
Test name
Test status
Simulation time 40675297625 ps
CPU time 2554.6 seconds
Started Jul 03 06:18:34 PM PDT 24
Finished Jul 03 07:01:09 PM PDT 24
Peak memory 289704 kb
Host smart-5c24b5df-6adb-42ce-a92a-4902533e9219
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470027534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3470027534
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3077768617
Short name T70
Test name
Test status
Simulation time 339629434914 ps
CPU time 5036.48 seconds
Started Jul 03 06:20:09 PM PDT 24
Finished Jul 03 07:44:07 PM PDT 24
Peak memory 338948 kb
Host smart-e52deac8-1edf-4116-8f99-cc650e239d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077768617 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3077768617
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3186078288
Short name T137
Test name
Test status
Simulation time 15910673621 ps
CPU time 1169.2 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:24:15 PM PDT 24
Peak memory 265428 kb
Host smart-8eac0e8e-0be2-4514-a906-a10119f7c33f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186078288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3186078288
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2219871878
Short name T27
Test name
Test status
Simulation time 47918202664 ps
CPU time 3020.45 seconds
Started Jul 03 06:20:35 PM PDT 24
Finished Jul 03 07:10:56 PM PDT 24
Peak memory 306416 kb
Host smart-9b3dbf3e-7a58-4465-8951-6d3df86e56ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219871878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2219871878
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.69699899
Short name T300
Test name
Test status
Simulation time 234145704577 ps
CPU time 3405.9 seconds
Started Jul 03 06:23:15 PM PDT 24
Finished Jul 03 07:20:02 PM PDT 24
Peak memory 289712 kb
Host smart-7e202178-d785-49f2-ac54-575dc70bc1e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69699899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.69699899
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2072081646
Short name T11
Test name
Test status
Simulation time 8938928377 ps
CPU time 364.88 seconds
Started Jul 03 06:17:41 PM PDT 24
Finished Jul 03 06:23:47 PM PDT 24
Peak memory 249380 kb
Host smart-dd1dfd86-b2e2-41d5-8947-4881b38b7285
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072081646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2072081646
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2555815485
Short name T136
Test name
Test status
Simulation time 11776683484 ps
CPU time 407.65 seconds
Started Jul 03 06:05:21 PM PDT 24
Finished Jul 03 06:12:09 PM PDT 24
Peak memory 273600 kb
Host smart-1c4c1cb1-6096-4c6e-a79b-eb3a9e567152
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2555815485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2555815485
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.120427265
Short name T7
Test name
Test status
Simulation time 71324846156 ps
CPU time 1380.89 seconds
Started Jul 03 06:14:54 PM PDT 24
Finished Jul 03 06:37:55 PM PDT 24
Peak memory 286332 kb
Host smart-4b50ded8-887f-47be-bcd4-f89fabe36c65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120427265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.120427265
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3615145555
Short name T10
Test name
Test status
Simulation time 32737432067 ps
CPU time 364.3 seconds
Started Jul 03 06:17:23 PM PDT 24
Finished Jul 03 06:23:28 PM PDT 24
Peak memory 249356 kb
Host smart-cff021be-d10a-4dc2-90d3-5c67c18b8cfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615145555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3615145555
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.583881978
Short name T276
Test name
Test status
Simulation time 14924270991 ps
CPU time 303.9 seconds
Started Jul 03 06:19:57 PM PDT 24
Finished Jul 03 06:25:01 PM PDT 24
Peak memory 249392 kb
Host smart-c495db07-2516-494f-881e-9bebefb43189
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583881978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.583881978
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2273690261
Short name T55
Test name
Test status
Simulation time 56053297486 ps
CPU time 3238.14 seconds
Started Jul 03 06:19:34 PM PDT 24
Finished Jul 03 07:13:33 PM PDT 24
Peak memory 298344 kb
Host smart-18761e37-e537-40d5-b353-10c3c250c15c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273690261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2273690261
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1646682295
Short name T133
Test name
Test status
Simulation time 3549193684 ps
CPU time 220.46 seconds
Started Jul 03 06:04:44 PM PDT 24
Finished Jul 03 06:08:25 PM PDT 24
Peak memory 265448 kb
Host smart-f90c34ff-391b-44df-9485-4e71eb99b882
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1646682295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1646682295
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3881536047
Short name T173
Test name
Test status
Simulation time 41626226304 ps
CPU time 2719.68 seconds
Started Jul 03 06:16:45 PM PDT 24
Finished Jul 03 07:02:05 PM PDT 24
Peak memory 306240 kb
Host smart-18b26c49-6b5a-4e4f-a328-91013bc809e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881536047 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3881536047
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.561897470
Short name T272
Test name
Test status
Simulation time 215754815132 ps
CPU time 3357.14 seconds
Started Jul 03 06:19:50 PM PDT 24
Finished Jul 03 07:15:48 PM PDT 24
Peak memory 290284 kb
Host smart-47d7a00e-366a-450f-9492-5dc20017992a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561897470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.561897470
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1883069382
Short name T114
Test name
Test status
Simulation time 49520381630 ps
CPU time 1104.55 seconds
Started Jul 03 06:04:55 PM PDT 24
Finished Jul 03 06:23:20 PM PDT 24
Peak memory 272332 kb
Host smart-746d865a-9c8e-433d-a538-7a9e84f6a96f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883069382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1883069382
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.792678116
Short name T49
Test name
Test status
Simulation time 117790665666 ps
CPU time 2255.68 seconds
Started Jul 03 06:17:19 PM PDT 24
Finished Jul 03 06:54:55 PM PDT 24
Peak memory 306128 kb
Host smart-967ddf0c-b752-4656-9a12-c49dc22294a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792678116 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.792678116
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3956778592
Short name T325
Test name
Test status
Simulation time 13251144 ps
CPU time 1.35 seconds
Started Jul 03 06:05:11 PM PDT 24
Finished Jul 03 06:05:12 PM PDT 24
Peak memory 237624 kb
Host smart-2836fb5e-57fa-4b14-bec8-5caaee2acbcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3956778592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3956778592
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1006729124
Short name T312
Test name
Test status
Simulation time 63373401691 ps
CPU time 2425.08 seconds
Started Jul 03 06:17:57 PM PDT 24
Finished Jul 03 06:58:23 PM PDT 24
Peak memory 290332 kb
Host smart-8b85c26a-f1f1-4c94-a0bf-c16df5ab0179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006729124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1006729124
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1066034784
Short name T116
Test name
Test status
Simulation time 9605051675 ps
CPU time 182.25 seconds
Started Jul 03 06:05:03 PM PDT 24
Finished Jul 03 06:08:05 PM PDT 24
Peak memory 265468 kb
Host smart-088f7208-77d2-4530-92cb-45a3fc2074e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1066034784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1066034784
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1311077744
Short name T595
Test name
Test status
Simulation time 12470608647 ps
CPU time 532.35 seconds
Started Jul 03 06:16:47 PM PDT 24
Finished Jul 03 06:25:40 PM PDT 24
Peak memory 249352 kb
Host smart-1ae28f6b-0697-4ba5-b927-6c10ae0aebc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311077744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1311077744
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1574176833
Short name T217
Test name
Test status
Simulation time 274104857762 ps
CPU time 4015.54 seconds
Started Jul 03 06:18:05 PM PDT 24
Finished Jul 03 07:25:01 PM PDT 24
Peak memory 298316 kb
Host smart-02d39fa9-c8dd-45e0-8f5e-287b7ba17962
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574176833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1574176833
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1469423878
Short name T95
Test name
Test status
Simulation time 15023299320 ps
CPU time 1085.88 seconds
Started Jul 03 06:22:26 PM PDT 24
Finished Jul 03 06:40:32 PM PDT 24
Peak memory 273280 kb
Host smart-b684db14-90a4-40b4-a99e-5d0eeaef5f00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469423878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1469423878
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.519298239
Short name T156
Test name
Test status
Simulation time 2150651247 ps
CPU time 45.85 seconds
Started Jul 03 06:04:57 PM PDT 24
Finished Jul 03 06:05:44 PM PDT 24
Peak memory 237792 kb
Host smart-f1150c15-a7d4-4516-bc6d-9451f153317b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=519298239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.519298239
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3066091271
Short name T30
Test name
Test status
Simulation time 418025529051 ps
CPU time 2152.5 seconds
Started Jul 03 06:15:12 PM PDT 24
Finished Jul 03 06:51:05 PM PDT 24
Peak memory 290472 kb
Host smart-50884e31-463c-4977-95a2-157f6e2f45d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066091271 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3066091271
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.748884907
Short name T224
Test name
Test status
Simulation time 8140025496 ps
CPU time 67.89 seconds
Started Jul 03 06:21:35 PM PDT 24
Finished Jul 03 06:22:43 PM PDT 24
Peak memory 250428 kb
Host smart-08476b74-abbd-4b7e-a749-abc4ccd89b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74888
4907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.748884907
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1372074071
Short name T302
Test name
Test status
Simulation time 38385941439 ps
CPU time 2438.29 seconds
Started Jul 03 06:22:51 PM PDT 24
Finished Jul 03 07:03:30 PM PDT 24
Peak memory 290256 kb
Host smart-6dee9ecb-53ce-4329-b45b-ad82ab348d85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372074071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1372074071
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2465414466
Short name T59
Test name
Test status
Simulation time 32026762942 ps
CPU time 2030.98 seconds
Started Jul 03 06:23:38 PM PDT 24
Finished Jul 03 06:57:30 PM PDT 24
Peak memory 286584 kb
Host smart-8c8415c8-c219-47d5-8d78-3d9a58e43602
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465414466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2465414466
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2629563292
Short name T152
Test name
Test status
Simulation time 59939530 ps
CPU time 2.94 seconds
Started Jul 03 06:04:52 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 237992 kb
Host smart-610105f2-59c0-4cb9-9d29-060e46a738ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2629563292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2629563292
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3783779068
Short name T120
Test name
Test status
Simulation time 36298147510 ps
CPU time 473.22 seconds
Started Jul 03 06:04:55 PM PDT 24
Finished Jul 03 06:12:48 PM PDT 24
Peak memory 265520 kb
Host smart-37290131-f128-4d01-8074-b8e03cf6b531
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783779068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3783779068
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3027393012
Short name T39
Test name
Test status
Simulation time 132122293 ps
CPU time 3.12 seconds
Started Jul 03 06:14:57 PM PDT 24
Finished Jul 03 06:15:00 PM PDT 24
Peak memory 249468 kb
Host smart-8d88012b-f288-4a73-af7f-e7bf2b038279
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3027393012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3027393012
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1763512473
Short name T190
Test name
Test status
Simulation time 62511281 ps
CPU time 3.2 seconds
Started Jul 03 06:16:45 PM PDT 24
Finished Jul 03 06:16:48 PM PDT 24
Peak memory 249532 kb
Host smart-7fa86a64-0b5f-4b2f-9da2-9ee80e77fe4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1763512473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1763512473
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2836428078
Short name T196
Test name
Test status
Simulation time 110407443 ps
CPU time 3.4 seconds
Started Jul 03 06:17:02 PM PDT 24
Finished Jul 03 06:17:06 PM PDT 24
Peak memory 249560 kb
Host smart-ae03f9c4-12f7-47ee-a840-0dd13f2041c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2836428078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2836428078
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3610753647
Short name T189
Test name
Test status
Simulation time 190520455 ps
CPU time 4.46 seconds
Started Jul 03 06:17:20 PM PDT 24
Finished Jul 03 06:17:25 PM PDT 24
Peak memory 249588 kb
Host smart-f5022a9d-de6d-4725-849c-c88cd5886ba6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3610753647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3610753647
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2079505405
Short name T306
Test name
Test status
Simulation time 193083409688 ps
CPU time 2830.35 seconds
Started Jul 03 06:16:57 PM PDT 24
Finished Jul 03 07:04:08 PM PDT 24
Peak memory 289692 kb
Host smart-d1785da1-3bf4-411f-bf5d-8f3fb6363109
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079505405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2079505405
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2390499805
Short name T219
Test name
Test status
Simulation time 2714082030 ps
CPU time 45.43 seconds
Started Jul 03 06:16:53 PM PDT 24
Finished Jul 03 06:17:39 PM PDT 24
Peak memory 257224 kb
Host smart-01f9def6-9b49-4701-85e3-021700a1b093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23904
99805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2390499805
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3930577600
Short name T253
Test name
Test status
Simulation time 11045016895 ps
CPU time 267.86 seconds
Started Jul 03 06:17:18 PM PDT 24
Finished Jul 03 06:21:46 PM PDT 24
Peak memory 249384 kb
Host smart-82eb0947-c562-4b05-aa8d-f2c24d9ae2ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930577600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3930577600
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.996804500
Short name T233
Test name
Test status
Simulation time 1107922289 ps
CPU time 22.82 seconds
Started Jul 03 06:17:42 PM PDT 24
Finished Jul 03 06:18:05 PM PDT 24
Peak memory 249204 kb
Host smart-382e422f-e364-4d28-b2c5-913309c496ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99680
4500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.996804500
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1798259113
Short name T267
Test name
Test status
Simulation time 12144339582 ps
CPU time 488.83 seconds
Started Jul 03 06:18:25 PM PDT 24
Finished Jul 03 06:26:34 PM PDT 24
Peak memory 249196 kb
Host smart-de2e577f-315a-4940-9e86-c1f0d3f5bd29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798259113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1798259113
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.4100081846
Short name T226
Test name
Test status
Simulation time 2129782104 ps
CPU time 31.34 seconds
Started Jul 03 06:15:45 PM PDT 24
Finished Jul 03 06:16:16 PM PDT 24
Peak memory 249116 kb
Host smart-72e438e4-1074-4285-8534-0f26db1ade53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41000
81846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.4100081846
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1517441349
Short name T140
Test name
Test status
Simulation time 6984989483 ps
CPU time 310.26 seconds
Started Jul 03 06:05:19 PM PDT 24
Finished Jul 03 06:10:29 PM PDT 24
Peak memory 272120 kb
Host smart-fe2c0105-8a96-4ccc-9e5d-860caf348ff5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1517441349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1517441349
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3518006958
Short name T104
Test name
Test status
Simulation time 12674686579 ps
CPU time 502.89 seconds
Started Jul 03 06:23:26 PM PDT 24
Finished Jul 03 06:31:49 PM PDT 24
Peak memory 257640 kb
Host smart-25068f6c-9a6c-4fa0-ac83-c03a66437182
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518006958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3518006958
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1778851074
Short name T121
Test name
Test status
Simulation time 15835089549 ps
CPU time 296.92 seconds
Started Jul 03 06:04:59 PM PDT 24
Finished Jul 03 06:09:56 PM PDT 24
Peak memory 265472 kb
Host smart-d8bce8f5-962d-49cc-b6b6-f5a63039f4e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1778851074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1778851074
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.646471395
Short name T134
Test name
Test status
Simulation time 11269656981 ps
CPU time 226.95 seconds
Started Jul 03 06:05:14 PM PDT 24
Finished Jul 03 06:09:01 PM PDT 24
Peak memory 267820 kb
Host smart-c4aceee7-218c-46ff-986d-b97bf5032243
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=646471395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.646471395
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.281527284
Short name T149
Test name
Test status
Simulation time 16281122 ps
CPU time 1.33 seconds
Started Jul 03 06:05:19 PM PDT 24
Finished Jul 03 06:05:21 PM PDT 24
Peak memory 237624 kb
Host smart-8b2d6d8d-c6b7-4827-a964-09bf412e0ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=281527284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.281527284
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.234636518
Short name T222
Test name
Test status
Simulation time 984843023 ps
CPU time 57.55 seconds
Started Jul 03 06:17:05 PM PDT 24
Finished Jul 03 06:18:03 PM PDT 24
Peak memory 256972 kb
Host smart-0c71c308-ffef-4333-959d-bdf30a12636a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
6518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.234636518
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3917480366
Short name T294
Test name
Test status
Simulation time 126585199074 ps
CPU time 1332.33 seconds
Started Jul 03 06:17:12 PM PDT 24
Finished Jul 03 06:39:25 PM PDT 24
Peak memory 289964 kb
Host smart-67280597-4905-43d5-b539-6c2c807d15f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917480366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3917480366
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1130915789
Short name T231
Test name
Test status
Simulation time 44366068952 ps
CPU time 2559.31 seconds
Started Jul 03 06:17:17 PM PDT 24
Finished Jul 03 06:59:57 PM PDT 24
Peak memory 290232 kb
Host smart-f5b20ab5-6ebf-44f0-8001-801e1680623f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130915789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1130915789
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3288956059
Short name T230
Test name
Test status
Simulation time 99554612772 ps
CPU time 1602.4 seconds
Started Jul 03 06:17:29 PM PDT 24
Finished Jul 03 06:44:12 PM PDT 24
Peak memory 290496 kb
Host smart-249da237-653b-45ca-b49a-448e3cfd5d32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288956059 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3288956059
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1865643315
Short name T66
Test name
Test status
Simulation time 1098990949 ps
CPU time 33.88 seconds
Started Jul 03 06:15:20 PM PDT 24
Finished Jul 03 06:15:54 PM PDT 24
Peak memory 249844 kb
Host smart-2d18ef33-68e0-43a1-92f9-7677bba2f190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18656
43315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1865643315
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1804016365
Short name T288
Test name
Test status
Simulation time 164795061 ps
CPU time 23.05 seconds
Started Jul 03 06:18:11 PM PDT 24
Finished Jul 03 06:18:34 PM PDT 24
Peak memory 249316 kb
Host smart-28517f2d-e366-4c3d-a916-dd29fd4dbe19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18040
16365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1804016365
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2177991943
Short name T227
Test name
Test status
Simulation time 596907207745 ps
CPU time 9488.74 seconds
Started Jul 03 06:19:44 PM PDT 24
Finished Jul 03 08:57:54 PM PDT 24
Peak memory 339196 kb
Host smart-d05535a5-790f-4812-88f1-5726b26b2b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177991943 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2177991943
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.309653718
Short name T292
Test name
Test status
Simulation time 33710399858 ps
CPU time 1387.32 seconds
Started Jul 03 06:21:57 PM PDT 24
Finished Jul 03 06:45:05 PM PDT 24
Peak memory 289036 kb
Host smart-4f32e8ff-dd82-46e8-a57b-d3111d20af52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309653718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.309653718
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2492885803
Short name T256
Test name
Test status
Simulation time 13080497107 ps
CPU time 510.2 seconds
Started Jul 03 06:22:43 PM PDT 24
Finished Jul 03 06:31:13 PM PDT 24
Peak memory 249208 kb
Host smart-f43aa7f4-17ad-4bc9-91a4-58631f0ed3d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492885803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2492885803
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.968602322
Short name T118
Test name
Test status
Simulation time 1678037327 ps
CPU time 218.77 seconds
Started Jul 03 06:05:04 PM PDT 24
Finished Jul 03 06:08:43 PM PDT 24
Peak memory 265404 kb
Host smart-1083fde2-d3e8-4af8-a546-5c4f9aa502fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=968602322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.968602322
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.425134150
Short name T154
Test name
Test status
Simulation time 152573515 ps
CPU time 20.83 seconds
Started Jul 03 06:04:43 PM PDT 24
Finished Jul 03 06:05:04 PM PDT 24
Peak memory 237824 kb
Host smart-592039f1-6803-4494-a319-420912b63368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=425134150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.425134150
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3875395465
Short name T161
Test name
Test status
Simulation time 409287391 ps
CPU time 2.97 seconds
Started Jul 03 06:04:47 PM PDT 24
Finished Jul 03 06:04:50 PM PDT 24
Peak memory 237496 kb
Host smart-5c0af01b-a586-4cb3-9eaa-70dab4486df8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3875395465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3875395465
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4098666144
Short name T145
Test name
Test status
Simulation time 55060819 ps
CPU time 4.29 seconds
Started Jul 03 06:05:18 PM PDT 24
Finished Jul 03 06:05:23 PM PDT 24
Peak memory 237992 kb
Host smart-3b0ffe11-1d9c-4445-a012-c278868ac6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4098666144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4098666144
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1055630467
Short name T117
Test name
Test status
Simulation time 3557056977 ps
CPU time 113.29 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:06:40 PM PDT 24
Peak memory 267768 kb
Host smart-7b667acd-5c52-4e55-bd74-79c38f7d6c6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1055630467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1055630467
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.591280372
Short name T153
Test name
Test status
Simulation time 3734776711 ps
CPU time 42.54 seconds
Started Jul 03 06:05:08 PM PDT 24
Finished Jul 03 06:05:51 PM PDT 24
Peak memory 238852 kb
Host smart-dc10b0cc-8f36-46ea-b498-fbf65e96947d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=591280372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.591280372
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.20415676
Short name T108
Test name
Test status
Simulation time 1978768385 ps
CPU time 148.03 seconds
Started Jul 03 06:05:11 PM PDT 24
Finished Jul 03 06:07:39 PM PDT 24
Peak memory 266376 kb
Host smart-a3aca967-6fb6-4523-bd31-05121545b343
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=20415676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_error
s.20415676
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1150819402
Short name T151
Test name
Test status
Simulation time 1273814555 ps
CPU time 78.93 seconds
Started Jul 03 06:05:04 PM PDT 24
Finished Jul 03 06:06:23 PM PDT 24
Peak memory 240548 kb
Host smart-559b8dc0-8b95-41b8-80cb-60efd88f9659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1150819402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1150819402
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3356854104
Short name T146
Test name
Test status
Simulation time 561869451 ps
CPU time 21.23 seconds
Started Jul 03 06:05:07 PM PDT 24
Finished Jul 03 06:05:28 PM PDT 24
Peak memory 240548 kb
Host smart-390058e4-02ce-491a-8ec2-b0488da46d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3356854104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3356854104
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3632247858
Short name T163
Test name
Test status
Simulation time 1257513315 ps
CPU time 34.24 seconds
Started Jul 03 06:05:18 PM PDT 24
Finished Jul 03 06:05:53 PM PDT 24
Peak memory 240544 kb
Host smart-5f2ab6f9-bf80-4b14-8124-1ac08b9f39df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3632247858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3632247858
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.689149260
Short name T158
Test name
Test status
Simulation time 107046954 ps
CPU time 3.29 seconds
Started Jul 03 06:05:22 PM PDT 24
Finished Jul 03 06:05:26 PM PDT 24
Peak memory 237624 kb
Host smart-d821d3e1-8eb6-466a-8d73-56166443a66b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=689149260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.689149260
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.932698599
Short name T164
Test name
Test status
Simulation time 60096954 ps
CPU time 3.86 seconds
Started Jul 03 06:05:20 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 236632 kb
Host smart-a5c16be1-d960-4233-99e0-fd92638772c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=932698599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.932698599
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3576672574
Short name T157
Test name
Test status
Simulation time 46651140 ps
CPU time 3.57 seconds
Started Jul 03 06:05:00 PM PDT 24
Finished Jul 03 06:05:04 PM PDT 24
Peak memory 237580 kb
Host smart-677e04b8-2553-4cb4-aefc-32d87f6723df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3576672574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3576672574
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.999044474
Short name T165
Test name
Test status
Simulation time 303790503 ps
CPU time 4.16 seconds
Started Jul 03 06:04:59 PM PDT 24
Finished Jul 03 06:05:04 PM PDT 24
Peak memory 237576 kb
Host smart-5ba1b6f6-7903-4f40-bbce-6118f910d235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=999044474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.999044474
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.324338638
Short name T179
Test name
Test status
Simulation time 2511760611 ps
CPU time 140.09 seconds
Started Jul 03 06:04:47 PM PDT 24
Finished Jul 03 06:07:07 PM PDT 24
Peak memory 241052 kb
Host smart-ed08369e-f17b-4ffb-8b39-c6ea86e5acf5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=324338638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.324338638
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2949358222
Short name T781
Test name
Test status
Simulation time 2879048820 ps
CPU time 189.32 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:07:55 PM PDT 24
Peak memory 240620 kb
Host smart-376473fc-46f8-47c6-945a-d6a7d2185517
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2949358222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2949358222
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.278771035
Short name T713
Test name
Test status
Simulation time 100950206 ps
CPU time 8.84 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 248768 kb
Host smart-064fb11b-818d-4fab-aa49-4b23e2db9c16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=278771035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.278771035
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3114138774
Short name T756
Test name
Test status
Simulation time 162827603 ps
CPU time 11.06 seconds
Started Jul 03 06:04:47 PM PDT 24
Finished Jul 03 06:04:58 PM PDT 24
Peak memory 251836 kb
Host smart-deda2bdf-9621-46de-96e2-128e44e5f031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114138774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3114138774
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2066295703
Short name T769
Test name
Test status
Simulation time 124463664 ps
CPU time 3.13 seconds
Started Jul 03 06:04:42 PM PDT 24
Finished Jul 03 06:04:46 PM PDT 24
Peak memory 237628 kb
Host smart-99b14e19-40ba-4d89-920e-7adfcb52f1fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2066295703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2066295703
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1990247440
Short name T736
Test name
Test status
Simulation time 12216670 ps
CPU time 1.63 seconds
Started Jul 03 06:04:44 PM PDT 24
Finished Jul 03 06:04:46 PM PDT 24
Peak memory 237624 kb
Host smart-97d48843-c96f-4c86-956d-239c11dab030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1990247440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1990247440
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1164085780
Short name T177
Test name
Test status
Simulation time 357549402 ps
CPU time 25.99 seconds
Started Jul 03 06:04:45 PM PDT 24
Finished Jul 03 06:05:11 PM PDT 24
Peak memory 245656 kb
Host smart-d1fdde4f-3b9d-4066-8051-e83869cee376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1164085780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1164085780
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3045725823
Short name T738
Test name
Test status
Simulation time 1091081594 ps
CPU time 12.16 seconds
Started Jul 03 06:04:44 PM PDT 24
Finished Jul 03 06:04:56 PM PDT 24
Peak memory 248796 kb
Host smart-5b13c33e-30d2-4e68-8bc5-2fb15f28c2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3045725823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3045725823
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2069470348
Short name T789
Test name
Test status
Simulation time 27109244078 ps
CPU time 340.26 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:10:27 PM PDT 24
Peak memory 241332 kb
Host smart-0aba4275-ef9e-4cd2-9fff-8bfc622c039b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2069470348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2069470348
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.777246740
Short name T780
Test name
Test status
Simulation time 50230919684 ps
CPU time 542.42 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:13:49 PM PDT 24
Peak memory 237648 kb
Host smart-2055fffb-fb5e-40a5-879e-e64c7fc1dd88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=777246740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.777246740
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3463840094
Short name T744
Test name
Test status
Simulation time 58919799 ps
CPU time 5.46 seconds
Started Jul 03 06:04:47 PM PDT 24
Finished Jul 03 06:04:52 PM PDT 24
Peak memory 248700 kb
Host smart-598ae238-9ba4-4949-9679-50b3e24edd46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3463840094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3463840094
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3110545009
Short name T828
Test name
Test status
Simulation time 218350415 ps
CPU time 7.99 seconds
Started Jul 03 06:04:47 PM PDT 24
Finished Jul 03 06:04:56 PM PDT 24
Peak memory 254108 kb
Host smart-1c9d8e9f-8975-4b81-8adb-5286ca14266f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110545009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3110545009
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.267821835
Short name T822
Test name
Test status
Simulation time 50871157 ps
CPU time 4.51 seconds
Started Jul 03 06:04:49 PM PDT 24
Finished Jul 03 06:04:53 PM PDT 24
Peak memory 240532 kb
Host smart-7d732e2c-51ed-4968-a8e1-8171eaac2f52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=267821835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.267821835
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3713413785
Short name T813
Test name
Test status
Simulation time 19940105 ps
CPU time 1.3 seconds
Started Jul 03 06:04:48 PM PDT 24
Finished Jul 03 06:04:49 PM PDT 24
Peak memory 236632 kb
Host smart-2bbd7787-e17f-4c31-b239-8dde426b9b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3713413785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3713413785
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3788055399
Short name T714
Test name
Test status
Simulation time 179231166 ps
CPU time 12.67 seconds
Started Jul 03 06:04:47 PM PDT 24
Finished Jul 03 06:05:00 PM PDT 24
Peak memory 240556 kb
Host smart-44b88aaa-90cf-4eaf-bcfc-b29982afb454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3788055399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3788055399
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2201021224
Short name T821
Test name
Test status
Simulation time 140055853 ps
CPU time 9.8 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:04:56 PM PDT 24
Peak memory 249848 kb
Host smart-0d455238-1ed7-41bf-b2ca-e65be639f491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2201021224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2201021224
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.552389826
Short name T794
Test name
Test status
Simulation time 73967275 ps
CPU time 7.3 seconds
Started Jul 03 06:05:08 PM PDT 24
Finished Jul 03 06:05:15 PM PDT 24
Peak memory 239748 kb
Host smart-c1f16658-10c3-477b-bfa1-cd1d998df724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552389826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.552389826
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3155068145
Short name T776
Test name
Test status
Simulation time 211839703 ps
CPU time 6.15 seconds
Started Jul 03 06:05:05 PM PDT 24
Finished Jul 03 06:05:12 PM PDT 24
Peak memory 240572 kb
Host smart-56a55bef-50b2-48c4-bcb4-74558c9eb447
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3155068145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3155068145
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2709344954
Short name T709
Test name
Test status
Simulation time 10632769 ps
CPU time 1.29 seconds
Started Jul 03 06:05:10 PM PDT 24
Finished Jul 03 06:05:12 PM PDT 24
Peak memory 236648 kb
Host smart-82d456d3-dae8-4411-9d63-17da372b9895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2709344954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2709344954
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.432657259
Short name T725
Test name
Test status
Simulation time 1248075270 ps
CPU time 23.72 seconds
Started Jul 03 06:05:07 PM PDT 24
Finished Jul 03 06:05:31 PM PDT 24
Peak memory 245800 kb
Host smart-1c0d6556-8f56-4f4a-9a1f-3441fc781788
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=432657259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.432657259
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2772920468
Short name T131
Test name
Test status
Simulation time 13245914864 ps
CPU time 679.89 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:16:22 PM PDT 24
Peak memory 265444 kb
Host smart-e26d4044-edc8-4bd2-b09c-ccc8a82fb783
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772920468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2772920468
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2766382759
Short name T211
Test name
Test status
Simulation time 707274387 ps
CPU time 14.91 seconds
Started Jul 03 06:05:03 PM PDT 24
Finished Jul 03 06:05:18 PM PDT 24
Peak memory 254584 kb
Host smart-da39e36a-af06-47ae-bc25-105eb1a6f604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2766382759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2766382759
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1544307032
Short name T790
Test name
Test status
Simulation time 69862121 ps
CPU time 5.9 seconds
Started Jul 03 06:05:08 PM PDT 24
Finished Jul 03 06:05:14 PM PDT 24
Peak memory 237536 kb
Host smart-215b5f00-ce93-4260-a8f5-1002c992cad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544307032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1544307032
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1868529569
Short name T327
Test name
Test status
Simulation time 354655664 ps
CPU time 8.22 seconds
Started Jul 03 06:05:10 PM PDT 24
Finished Jul 03 06:05:19 PM PDT 24
Peak memory 237576 kb
Host smart-adb2195d-79e7-4584-a391-a36012ef4491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1868529569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1868529569
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.276658622
Short name T811
Test name
Test status
Simulation time 9485155 ps
CPU time 1.5 seconds
Started Jul 03 06:05:07 PM PDT 24
Finished Jul 03 06:05:09 PM PDT 24
Peak memory 235596 kb
Host smart-55af27e1-5818-4156-baaa-c4aee6ec2abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=276658622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.276658622
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3699339070
Short name T176
Test name
Test status
Simulation time 1376487365 ps
CPU time 44.44 seconds
Started Jul 03 06:05:12 PM PDT 24
Finished Jul 03 06:05:57 PM PDT 24
Peak memory 245804 kb
Host smart-1e6776cc-4d2e-4f4f-8197-0b65d4882f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3699339070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3699339070
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3861547470
Short name T122
Test name
Test status
Simulation time 3203934690 ps
CPU time 99.6 seconds
Started Jul 03 06:05:07 PM PDT 24
Finished Jul 03 06:06:47 PM PDT 24
Peak memory 265320 kb
Host smart-91d472fd-4ffd-4738-a9ef-5ec7fa81f0bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3861547470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3861547470
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.14894061
Short name T735
Test name
Test status
Simulation time 273951044 ps
CPU time 17.38 seconds
Started Jul 03 06:05:06 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 256916 kb
Host smart-162832f4-acea-444c-852f-5aea581bf6e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=14894061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.14894061
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1631544940
Short name T812
Test name
Test status
Simulation time 33895025 ps
CPU time 4.98 seconds
Started Jul 03 06:05:14 PM PDT 24
Finished Jul 03 06:05:20 PM PDT 24
Peak memory 248816 kb
Host smart-16c81585-b1ea-48ba-a17a-50de3acd204b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631544940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1631544940
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.54404850
Short name T819
Test name
Test status
Simulation time 237246231 ps
CPU time 8.37 seconds
Started Jul 03 06:05:09 PM PDT 24
Finished Jul 03 06:05:17 PM PDT 24
Peak memory 240576 kb
Host smart-6407b609-a547-466c-9193-9e1b6cf740f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=54404850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.54404850
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3480685770
Short name T175
Test name
Test status
Simulation time 950874842 ps
CPU time 26.02 seconds
Started Jul 03 06:05:09 PM PDT 24
Finished Jul 03 06:05:35 PM PDT 24
Peak memory 245808 kb
Host smart-196f6543-d098-4146-b8e8-d31577590b2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3480685770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3480685770
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.458729681
Short name T128
Test name
Test status
Simulation time 8010805324 ps
CPU time 307.84 seconds
Started Jul 03 06:05:08 PM PDT 24
Finished Jul 03 06:10:16 PM PDT 24
Peak memory 271692 kb
Host smart-9831cbdc-6317-45d7-9913-e6e5b28f840e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=458729681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.458729681
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2290723322
Short name T110
Test name
Test status
Simulation time 10075365457 ps
CPU time 530.19 seconds
Started Jul 03 06:05:11 PM PDT 24
Finished Jul 03 06:14:01 PM PDT 24
Peak memory 265520 kb
Host smart-935f2347-c8f8-4ec2-8013-5b7bddc82301
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290723322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2290723322
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1665061034
Short name T716
Test name
Test status
Simulation time 106487225 ps
CPU time 7.34 seconds
Started Jul 03 06:05:10 PM PDT 24
Finished Jul 03 06:05:18 PM PDT 24
Peak memory 253408 kb
Host smart-7e756c58-33b9-47fa-97e1-d9cce667b351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1665061034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1665061034
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3860313154
Short name T147
Test name
Test status
Simulation time 115718626 ps
CPU time 3.55 seconds
Started Jul 03 06:05:11 PM PDT 24
Finished Jul 03 06:05:15 PM PDT 24
Peak memory 236672 kb
Host smart-af4cd657-ce69-475a-9924-fe196d830fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3860313154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3860313154
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2782803102
Short name T743
Test name
Test status
Simulation time 277030511 ps
CPU time 7.7 seconds
Started Jul 03 06:05:13 PM PDT 24
Finished Jul 03 06:05:21 PM PDT 24
Peak memory 239264 kb
Host smart-9d631988-052c-42bc-9226-df438ffad97a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782803102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2782803102
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1852595685
Short name T800
Test name
Test status
Simulation time 59534316 ps
CPU time 5.91 seconds
Started Jul 03 06:05:14 PM PDT 24
Finished Jul 03 06:05:21 PM PDT 24
Peak memory 237564 kb
Host smart-01849613-126b-478a-a737-74abd619b18e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1852595685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1852595685
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3502829338
Short name T797
Test name
Test status
Simulation time 6324087 ps
CPU time 1.47 seconds
Started Jul 03 06:05:16 PM PDT 24
Finished Jul 03 06:05:17 PM PDT 24
Peak memory 235636 kb
Host smart-ee0923bf-10ae-4200-a6c7-c82fdd783894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3502829338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3502829338
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.26359857
Short name T746
Test name
Test status
Simulation time 314925707 ps
CPU time 26.91 seconds
Started Jul 03 06:05:14 PM PDT 24
Finished Jul 03 06:05:42 PM PDT 24
Peak memory 245772 kb
Host smart-6d318c9f-22b0-491e-8eeb-9f7e6356800f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=26359857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outs
tanding.26359857
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.509790801
Short name T141
Test name
Test status
Simulation time 23822399887 ps
CPU time 506.82 seconds
Started Jul 03 06:05:11 PM PDT 24
Finished Jul 03 06:13:38 PM PDT 24
Peak memory 265472 kb
Host smart-6b716809-8769-4fd7-9327-b4a681a4c9d9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509790801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.509790801
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3431225810
Short name T733
Test name
Test status
Simulation time 777108506 ps
CPU time 10.57 seconds
Started Jul 03 06:05:13 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 248332 kb
Host smart-23da1e43-1b4c-4dfa-ace0-d6fc95beb8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3431225810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3431225810
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3932782720
Short name T326
Test name
Test status
Simulation time 1072650361 ps
CPU time 27.2 seconds
Started Jul 03 06:05:13 PM PDT 24
Finished Jul 03 06:05:41 PM PDT 24
Peak memory 240536 kb
Host smart-f60dedd3-6a68-4569-a05a-2970845ba01d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3932782720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3932782720
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3345159858
Short name T750
Test name
Test status
Simulation time 67626860 ps
CPU time 5.62 seconds
Started Jul 03 06:05:20 PM PDT 24
Finished Jul 03 06:05:26 PM PDT 24
Peak memory 239788 kb
Host smart-e20af733-898c-434e-8da3-09043b535f9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345159858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3345159858
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2372676217
Short name T730
Test name
Test status
Simulation time 827265864 ps
CPU time 10.12 seconds
Started Jul 03 06:05:16 PM PDT 24
Finished Jul 03 06:05:27 PM PDT 24
Peak memory 240536 kb
Host smart-0b309018-5409-43d0-b43b-1a3622b91113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2372676217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2372676217
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3616818560
Short name T808
Test name
Test status
Simulation time 1040855097 ps
CPU time 19.36 seconds
Started Jul 03 06:05:12 PM PDT 24
Finished Jul 03 06:05:31 PM PDT 24
Peak memory 244764 kb
Host smart-f427aaa1-f6bc-4fc1-b144-4da184b1c903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3616818560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3616818560
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1725290984
Short name T124
Test name
Test status
Simulation time 33624499623 ps
CPU time 637.18 seconds
Started Jul 03 06:05:14 PM PDT 24
Finished Jul 03 06:15:52 PM PDT 24
Peak memory 265440 kb
Host smart-52b6cdfb-abe8-41cd-8a8e-856d2f5b6d44
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725290984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1725290984
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2534512993
Short name T734
Test name
Test status
Simulation time 132270692 ps
CPU time 10.57 seconds
Started Jul 03 06:05:13 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 252820 kb
Host smart-f8904d9e-69e1-497d-9a90-da3be9435be2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2534512993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2534512993
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2734661638
Short name T775
Test name
Test status
Simulation time 98928038 ps
CPU time 2.44 seconds
Started Jul 03 06:05:14 PM PDT 24
Finished Jul 03 06:05:17 PM PDT 24
Peak memory 237688 kb
Host smart-298d3184-e7e3-443f-a10a-fb376f0655bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2734661638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2734661638
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4015614422
Short name T761
Test name
Test status
Simulation time 374583517 ps
CPU time 7.98 seconds
Started Jul 03 06:05:17 PM PDT 24
Finished Jul 03 06:05:25 PM PDT 24
Peak memory 240504 kb
Host smart-b0856696-a700-4385-977b-4048673b06dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015614422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4015614422
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1982850664
Short name T178
Test name
Test status
Simulation time 65498020 ps
CPU time 5.75 seconds
Started Jul 03 06:05:18 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 240536 kb
Host smart-c8156f49-afe9-403b-b27b-36ca4e486c09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1982850664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1982850664
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2566409941
Short name T760
Test name
Test status
Simulation time 85561777 ps
CPU time 10.42 seconds
Started Jul 03 06:05:18 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 244848 kb
Host smart-eb629a93-3765-43af-833d-04c4088ac273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2566409941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2566409941
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3695928400
Short name T125
Test name
Test status
Simulation time 26860710596 ps
CPU time 511.12 seconds
Started Jul 03 06:05:17 PM PDT 24
Finished Jul 03 06:13:48 PM PDT 24
Peak memory 273472 kb
Host smart-41ebf625-483a-4079-bdc6-0668eea7f2da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695928400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3695928400
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.875576156
Short name T741
Test name
Test status
Simulation time 187367885 ps
CPU time 12.65 seconds
Started Jul 03 06:05:19 PM PDT 24
Finished Jul 03 06:05:32 PM PDT 24
Peak memory 253620 kb
Host smart-9eae6bdb-97c3-4fec-87f1-500bf05623ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=875576156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.875576156
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.997032930
Short name T711
Test name
Test status
Simulation time 134291197 ps
CPU time 12.03 seconds
Started Jul 03 06:05:23 PM PDT 24
Finished Jul 03 06:05:35 PM PDT 24
Peak memory 254568 kb
Host smart-13bc2444-e6c1-4995-a386-9a22e06c2a97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997032930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.997032930
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3393537432
Short name T773
Test name
Test status
Simulation time 123302321 ps
CPU time 5.02 seconds
Started Jul 03 06:05:23 PM PDT 24
Finished Jul 03 06:05:28 PM PDT 24
Peak memory 237624 kb
Host smart-f03d4980-72cf-441d-9ceb-a42659cf84f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3393537432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3393537432
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.367978820
Short name T752
Test name
Test status
Simulation time 8445953 ps
CPU time 1.38 seconds
Started Jul 03 06:05:19 PM PDT 24
Finished Jul 03 06:05:21 PM PDT 24
Peak memory 237596 kb
Host smart-04f34622-7fe4-44a5-84ca-7d7f5c94987a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=367978820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.367978820
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1943041
Short name T796
Test name
Test status
Simulation time 684742646 ps
CPU time 23.62 seconds
Started Jul 03 06:05:22 PM PDT 24
Finished Jul 03 06:05:46 PM PDT 24
Peak memory 244888 kb
Host smart-163a8cb1-d9e2-4050-b55f-e523219205bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1943041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outst
anding.1943041
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3018121663
Short name T111
Test name
Test status
Simulation time 3499561591 ps
CPU time 218.16 seconds
Started Jul 03 06:05:19 PM PDT 24
Finished Jul 03 06:08:57 PM PDT 24
Peak memory 265488 kb
Host smart-7efb7354-8183-4306-ae78-b3f47f2b9980
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3018121663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3018121663
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.455311564
Short name T815
Test name
Test status
Simulation time 2525973865 ps
CPU time 364.34 seconds
Started Jul 03 06:05:16 PM PDT 24
Finished Jul 03 06:11:21 PM PDT 24
Peak memory 268664 kb
Host smart-07fe5be0-21a2-4de0-9b0b-911162635db4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455311564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.455311564
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.615788423
Short name T213
Test name
Test status
Simulation time 1447858493 ps
CPU time 20.62 seconds
Started Jul 03 06:05:20 PM PDT 24
Finished Jul 03 06:05:41 PM PDT 24
Peak memory 255460 kb
Host smart-aac2bfa2-e6c7-4dc1-96ff-efceaa1845b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=615788423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.615788423
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1852263388
Short name T817
Test name
Test status
Simulation time 312972502 ps
CPU time 6.95 seconds
Started Jul 03 06:05:21 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 240872 kb
Host smart-1827fef9-123c-4d28-92c7-4b9a7505c4dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852263388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1852263388
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.187849905
Short name T757
Test name
Test status
Simulation time 126057887 ps
CPU time 5.36 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:32 PM PDT 24
Peak memory 236608 kb
Host smart-ee2b8a2e-9d91-4ec1-8bd3-47dfb4d1d18c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=187849905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.187849905
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.115393793
Short name T708
Test name
Test status
Simulation time 9243937 ps
CPU time 1.54 seconds
Started Jul 03 06:05:22 PM PDT 24
Finished Jul 03 06:05:23 PM PDT 24
Peak memory 236676 kb
Host smart-f9b61a9d-b021-4a00-86a9-a50adff19268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=115393793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.115393793
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1173575160
Short name T785
Test name
Test status
Simulation time 664665396 ps
CPU time 25.56 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:53 PM PDT 24
Peak memory 245748 kb
Host smart-fdd13133-0340-4d5f-bf55-3db16a37cb33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1173575160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1173575160
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2937461021
Short name T119
Test name
Test status
Simulation time 14764797710 ps
CPU time 1084.66 seconds
Started Jul 03 06:05:21 PM PDT 24
Finished Jul 03 06:23:27 PM PDT 24
Peak memory 265584 kb
Host smart-2c9d3d9f-f64d-4412-9633-544b941eeced
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937461021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2937461021
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1674028832
Short name T727
Test name
Test status
Simulation time 69429445 ps
CPU time 10.41 seconds
Started Jul 03 06:05:26 PM PDT 24
Finished Jul 03 06:05:37 PM PDT 24
Peak memory 248780 kb
Host smart-07d892cb-025d-43da-8a97-642ebd3dfcdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1674028832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1674028832
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1674969056
Short name T759
Test name
Test status
Simulation time 191938225 ps
CPU time 13.66 seconds
Started Jul 03 06:05:26 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 249848 kb
Host smart-aca7766e-fc05-42ae-8108-ff1994ae4293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674969056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1674969056
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1423750680
Short name T214
Test name
Test status
Simulation time 483978595 ps
CPU time 9.71 seconds
Started Jul 03 06:05:19 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 237752 kb
Host smart-1476889c-c345-4796-bbf0-ab5504a9026d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1423750680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1423750680
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3861200668
Short name T778
Test name
Test status
Simulation time 9948938 ps
CPU time 1.46 seconds
Started Jul 03 06:05:22 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 235740 kb
Host smart-e438155d-b3fc-4dda-93b1-18c6a98f3a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3861200668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3861200668
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3571952929
Short name T723
Test name
Test status
Simulation time 2466470831 ps
CPU time 44.95 seconds
Started Jul 03 06:05:24 PM PDT 24
Finished Jul 03 06:06:10 PM PDT 24
Peak memory 248772 kb
Host smart-b23d554e-c7ff-45ba-b8a0-e36c288c900b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3571952929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3571952929
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3676981333
Short name T810
Test name
Test status
Simulation time 2308340155 ps
CPU time 155.7 seconds
Started Jul 03 06:05:26 PM PDT 24
Finished Jul 03 06:08:02 PM PDT 24
Peak memory 265424 kb
Host smart-7ca6a303-cd35-4cec-9afb-ab5d0ca78486
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3676981333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3676981333
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2065295420
Short name T802
Test name
Test status
Simulation time 114834431 ps
CPU time 14.08 seconds
Started Jul 03 06:05:20 PM PDT 24
Finished Jul 03 06:05:34 PM PDT 24
Peak memory 248804 kb
Host smart-6d74a4a3-55cd-42db-b15e-3fefe2858b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065295420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2065295420
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.657088909
Short name T798
Test name
Test status
Simulation time 154843406 ps
CPU time 10.51 seconds
Started Jul 03 06:05:26 PM PDT 24
Finished Jul 03 06:05:37 PM PDT 24
Peak memory 257020 kb
Host smart-c233d3c2-4f22-4278-9e7c-3d5688b4855a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657088909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.657088909
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2835620842
Short name T771
Test name
Test status
Simulation time 68263276 ps
CPU time 5.67 seconds
Started Jul 03 06:05:28 PM PDT 24
Finished Jul 03 06:05:35 PM PDT 24
Peak memory 237572 kb
Host smart-670d9a35-ad8e-4d19-95bc-b380f4e4744c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2835620842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2835620842
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1897699232
Short name T782
Test name
Test status
Simulation time 19396563 ps
CPU time 1.57 seconds
Started Jul 03 06:05:23 PM PDT 24
Finished Jul 03 06:05:25 PM PDT 24
Peak memory 236656 kb
Host smart-955e7c94-799c-46dc-a8cc-f5e17a0bc435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1897699232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1897699232
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1175142041
Short name T160
Test name
Test status
Simulation time 171501158 ps
CPU time 10.92 seconds
Started Jul 03 06:05:29 PM PDT 24
Finished Jul 03 06:05:41 PM PDT 24
Peak memory 244820 kb
Host smart-b9870f8b-4f46-4244-99da-64cc7e8d541c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1175142041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1175142041
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3384350737
Short name T142
Test name
Test status
Simulation time 2412139572 ps
CPU time 159.28 seconds
Started Jul 03 06:05:25 PM PDT 24
Finished Jul 03 06:08:04 PM PDT 24
Peak memory 265472 kb
Host smart-feffbf24-42ef-4245-954d-87556fd9e75c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3384350737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3384350737
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.809988966
Short name T135
Test name
Test status
Simulation time 30628547474 ps
CPU time 1255.96 seconds
Started Jul 03 06:05:24 PM PDT 24
Finished Jul 03 06:26:21 PM PDT 24
Peak memory 265448 kb
Host smart-6d6069be-76d8-4abd-bfb6-7cb7741e0336
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809988966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.809988966
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3850720039
Short name T728
Test name
Test status
Simulation time 104025179 ps
CPU time 15.12 seconds
Started Jul 03 06:05:26 PM PDT 24
Finished Jul 03 06:05:42 PM PDT 24
Peak memory 249044 kb
Host smart-af397681-64a1-4e2e-b668-6ace54caedf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3850720039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3850720039
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3951755689
Short name T721
Test name
Test status
Simulation time 48477896 ps
CPU time 3.34 seconds
Started Jul 03 06:05:24 PM PDT 24
Finished Jul 03 06:05:27 PM PDT 24
Peak memory 237436 kb
Host smart-95e16371-94e7-4bd6-a85d-05c9be834d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3951755689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3951755689
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3492918884
Short name T779
Test name
Test status
Simulation time 2887501769 ps
CPU time 172.61 seconds
Started Jul 03 06:04:53 PM PDT 24
Finished Jul 03 06:07:46 PM PDT 24
Peak memory 237676 kb
Host smart-1fd05f9f-e620-497b-956d-ce94ae5aea62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3492918884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3492918884
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.42669588
Short name T159
Test name
Test status
Simulation time 4290912864 ps
CPU time 264.51 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:09:16 PM PDT 24
Peak memory 237696 kb
Host smart-3fa36a26-67dc-4240-a496-a69e580d4eed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=42669588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.42669588
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2750402
Short name T722
Test name
Test status
Simulation time 97038489 ps
CPU time 3.81 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 248744 kb
Host smart-27ed3abf-d278-4cb2-b0f8-e625490332a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2750402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2750402
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2019079871
Short name T772
Test name
Test status
Simulation time 261789566 ps
CPU time 14.55 seconds
Started Jul 03 06:04:49 PM PDT 24
Finished Jul 03 06:05:04 PM PDT 24
Peak memory 254988 kb
Host smart-abb399d3-b879-4f01-be63-5cbce6b9a5da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019079871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2019079871
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1450291726
Short name T787
Test name
Test status
Simulation time 62374985 ps
CPU time 3.41 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 236656 kb
Host smart-fa0da09c-524f-4a2f-a3bf-b57dd1f0181c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1450291726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1450291726
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1395660055
Short name T754
Test name
Test status
Simulation time 6521305 ps
CPU time 1.42 seconds
Started Jul 03 06:04:50 PM PDT 24
Finished Jul 03 06:04:52 PM PDT 24
Peak memory 237540 kb
Host smart-c5ec82a6-c938-4d0a-b31d-ffdf97654c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1395660055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1395660055
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3469952364
Short name T724
Test name
Test status
Simulation time 456678619 ps
CPU time 22.04 seconds
Started Jul 03 06:04:54 PM PDT 24
Finished Jul 03 06:05:16 PM PDT 24
Peak memory 244848 kb
Host smart-f9c7e5ec-b13b-44dd-8884-027860b16bf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3469952364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3469952364
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1230881503
Short name T144
Test name
Test status
Simulation time 8473148789 ps
CPU time 182.33 seconds
Started Jul 03 06:04:54 PM PDT 24
Finished Jul 03 06:07:56 PM PDT 24
Peak memory 265448 kb
Host smart-73cdd159-f561-4ed1-945e-a3589ccb2177
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1230881503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1230881503
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3189244015
Short name T123
Test name
Test status
Simulation time 7444215943 ps
CPU time 555.65 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:14:07 PM PDT 24
Peak memory 265436 kb
Host smart-6d298e01-1390-4297-bf05-84f57e4d6516
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189244015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3189244015
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3176192140
Short name T799
Test name
Test status
Simulation time 377902402 ps
CPU time 13.19 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:05:04 PM PDT 24
Peak memory 254412 kb
Host smart-089c44ff-3e92-4df0-8a4a-dcadc8b8cb07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3176192140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3176192140
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.694253253
Short name T320
Test name
Test status
Simulation time 14516396 ps
CPU time 1.34 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 237504 kb
Host smart-3e9075ae-fb6f-4d10-a019-b49588ab592f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=694253253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.694253253
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1984835397
Short name T755
Test name
Test status
Simulation time 12390254 ps
CPU time 1.45 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 235668 kb
Host smart-5e9643a9-a35d-44f2-a64a-382f06af8e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1984835397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1984835397
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.767007447
Short name T148
Test name
Test status
Simulation time 9654245 ps
CPU time 1.41 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 236672 kb
Host smart-51a6b699-f53e-40d6-be44-38109bf7d480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=767007447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.767007447
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1206919738
Short name T763
Test name
Test status
Simulation time 7306067 ps
CPU time 1.45 seconds
Started Jul 03 06:05:29 PM PDT 24
Finished Jul 03 06:05:31 PM PDT 24
Peak memory 237628 kb
Host smart-4f00ea01-ebb5-4c64-9eac-c7114507de6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1206919738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1206919738
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1215634615
Short name T801
Test name
Test status
Simulation time 8089209 ps
CPU time 1.35 seconds
Started Jul 03 06:05:28 PM PDT 24
Finished Jul 03 06:05:30 PM PDT 24
Peak memory 236728 kb
Host smart-a8cc4e0b-402d-404d-aa79-188142d20197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1215634615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1215634615
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1485575333
Short name T749
Test name
Test status
Simulation time 21024014 ps
CPU time 1.41 seconds
Started Jul 03 06:05:28 PM PDT 24
Finished Jul 03 06:05:30 PM PDT 24
Peak memory 237624 kb
Host smart-2f58b030-f6cb-45d2-9b46-be622c77237c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1485575333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1485575333
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1178497514
Short name T824
Test name
Test status
Simulation time 10194635 ps
CPU time 1.47 seconds
Started Jul 03 06:05:29 PM PDT 24
Finished Jul 03 06:05:31 PM PDT 24
Peak memory 237632 kb
Host smart-518d8e5f-ef83-4a75-b62b-f2e19107b62c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1178497514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1178497514
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2770047038
Short name T322
Test name
Test status
Simulation time 11376824 ps
CPU time 1.26 seconds
Started Jul 03 06:05:29 PM PDT 24
Finished Jul 03 06:05:31 PM PDT 24
Peak memory 236640 kb
Host smart-034df8cc-10c4-4aeb-bf17-e375c89a2e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2770047038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2770047038
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3083194136
Short name T818
Test name
Test status
Simulation time 11446139 ps
CPU time 1.41 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 236648 kb
Host smart-ad855ae7-5d60-4370-bc63-ec951da6d607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3083194136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3083194136
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.394695595
Short name T719
Test name
Test status
Simulation time 10631340 ps
CPU time 1.39 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 237632 kb
Host smart-df110331-4fc6-4b39-9c31-b9fe871b48e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=394695595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.394695595
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.598680329
Short name T717
Test name
Test status
Simulation time 8598110091 ps
CPU time 169.94 seconds
Started Jul 03 06:04:55 PM PDT 24
Finished Jul 03 06:07:45 PM PDT 24
Peak memory 240632 kb
Host smart-6fa20ee0-e1d8-46a0-973c-521a998075fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=598680329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.598680329
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.580902715
Short name T181
Test name
Test status
Simulation time 12403547029 ps
CPU time 180.4 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:07:52 PM PDT 24
Peak memory 236728 kb
Host smart-cf8c2265-35e1-426e-b72f-4d0bb1554ce5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=580902715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.580902715
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1249540573
Short name T745
Test name
Test status
Simulation time 195062198 ps
CPU time 10.18 seconds
Started Jul 03 06:04:51 PM PDT 24
Finished Jul 03 06:05:01 PM PDT 24
Peak memory 249292 kb
Host smart-d841a4a8-1a32-4400-b1fa-efe0087407d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1249540573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1249540573
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1731175605
Short name T739
Test name
Test status
Simulation time 223636112 ps
CPU time 5.33 seconds
Started Jul 03 06:04:53 PM PDT 24
Finished Jul 03 06:04:59 PM PDT 24
Peak memory 242996 kb
Host smart-612f767b-2cb8-4069-a0e0-f115f6433e3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731175605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1731175605
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3427416649
Short name T788
Test name
Test status
Simulation time 92771874 ps
CPU time 4.83 seconds
Started Jul 03 06:04:49 PM PDT 24
Finished Jul 03 06:04:54 PM PDT 24
Peak memory 237596 kb
Host smart-1761dba3-8fd0-4382-8dee-9bc969f32203
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3427416649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3427416649
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1215489486
Short name T806
Test name
Test status
Simulation time 15757161 ps
CPU time 1.58 seconds
Started Jul 03 06:04:53 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 236692 kb
Host smart-b738c3ff-2dff-447c-805b-440eb9a9d4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1215489486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1215489486
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3094654355
Short name T747
Test name
Test status
Simulation time 797565454 ps
CPU time 33.14 seconds
Started Jul 03 06:04:53 PM PDT 24
Finished Jul 03 06:05:26 PM PDT 24
Peak memory 244884 kb
Host smart-e5f6a49c-a2a5-4761-90a4-fd833cdc31bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3094654355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3094654355
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2967321051
Short name T115
Test name
Test status
Simulation time 1963060505 ps
CPU time 165.56 seconds
Started Jul 03 06:04:52 PM PDT 24
Finished Jul 03 06:07:38 PM PDT 24
Peak memory 257208 kb
Host smart-405f150e-58f3-4544-bf64-aa63cb73949f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2967321051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2967321051
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1138435857
Short name T143
Test name
Test status
Simulation time 8414481094 ps
CPU time 635.58 seconds
Started Jul 03 06:04:48 PM PDT 24
Finished Jul 03 06:15:24 PM PDT 24
Peak memory 265460 kb
Host smart-0d1963de-5335-4f43-b25c-56a680f9de41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138435857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1138435857
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2471977041
Short name T707
Test name
Test status
Simulation time 65464573 ps
CPU time 7.9 seconds
Started Jul 03 06:04:50 PM PDT 24
Finished Jul 03 06:04:58 PM PDT 24
Peak memory 248000 kb
Host smart-32dc43ac-98f0-41dc-bee1-3ad51833d5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2471977041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2471977041
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2629696007
Short name T242
Test name
Test status
Simulation time 47973093 ps
CPU time 3.27 seconds
Started Jul 03 06:04:50 PM PDT 24
Finished Jul 03 06:04:54 PM PDT 24
Peak memory 238552 kb
Host smart-565586a6-2afc-44e9-9d5b-08b3737fff32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2629696007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2629696007
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1678035292
Short name T792
Test name
Test status
Simulation time 9892878 ps
CPU time 1.66 seconds
Started Jul 03 06:05:29 PM PDT 24
Finished Jul 03 06:05:31 PM PDT 24
Peak memory 237628 kb
Host smart-6b8cc6b6-e9d6-4a2c-98cc-ac5ed1e23712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1678035292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1678035292
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2968275503
Short name T831
Test name
Test status
Simulation time 8646997 ps
CPU time 1.4 seconds
Started Jul 03 06:05:28 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 237624 kb
Host smart-8951975d-8d83-4106-8077-d77442bb6967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2968275503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2968275503
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1912449680
Short name T731
Test name
Test status
Simulation time 61073585 ps
CPU time 1.39 seconds
Started Jul 03 06:05:28 PM PDT 24
Finished Jul 03 06:05:30 PM PDT 24
Peak memory 235636 kb
Host smart-b66fdc3f-21a8-410b-9d6e-1a071218ddaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1912449680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1912449680
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3782726326
Short name T729
Test name
Test status
Simulation time 9366529 ps
CPU time 1.31 seconds
Started Jul 03 06:05:27 PM PDT 24
Finished Jul 03 06:05:29 PM PDT 24
Peak memory 236644 kb
Host smart-959f18c2-2436-4c40-9c34-aaa7aca198e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3782726326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3782726326
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1758976597
Short name T765
Test name
Test status
Simulation time 58316046 ps
CPU time 3.42 seconds
Started Jul 03 06:05:29 PM PDT 24
Finished Jul 03 06:05:33 PM PDT 24
Peak memory 236648 kb
Host smart-d72cbddd-21a8-451d-9079-1a4d0fdeaa7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758976597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1758976597
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3844536901
Short name T215
Test name
Test status
Simulation time 9077707 ps
CPU time 1.66 seconds
Started Jul 03 06:05:31 PM PDT 24
Finished Jul 03 06:05:33 PM PDT 24
Peak memory 236644 kb
Host smart-da8b1780-e73a-4bef-96bc-b3f2f559a254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3844536901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3844536901
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2407845015
Short name T825
Test name
Test status
Simulation time 6842765 ps
CPU time 1.47 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 236640 kb
Host smart-3049fb70-9048-4e37-b699-68098518f620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2407845015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2407845015
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1609610107
Short name T820
Test name
Test status
Simulation time 7570206 ps
CPU time 1.41 seconds
Started Jul 03 06:05:33 PM PDT 24
Finished Jul 03 06:05:34 PM PDT 24
Peak memory 237652 kb
Host smart-86398552-bf7d-41b0-b033-40c752e29ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609610107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1609610107
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1810818718
Short name T737
Test name
Test status
Simulation time 13674176 ps
CPU time 1.76 seconds
Started Jul 03 06:05:30 PM PDT 24
Finished Jul 03 06:05:32 PM PDT 24
Peak memory 235676 kb
Host smart-6456fb30-24bf-4a61-b424-5bc15e68caa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1810818718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1810818718
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2983818596
Short name T804
Test name
Test status
Simulation time 64248422 ps
CPU time 1.49 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 236736 kb
Host smart-dff6f96f-4dda-41fa-a77f-fcca2ccbd1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983818596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2983818596
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2778711096
Short name T805
Test name
Test status
Simulation time 1988030165 ps
CPU time 70.05 seconds
Started Jul 03 06:04:58 PM PDT 24
Finished Jul 03 06:06:09 PM PDT 24
Peak memory 237592 kb
Host smart-8fbbc69c-4ee9-4ccc-a823-871636ade1fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2778711096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2778711096
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4004414033
Short name T767
Test name
Test status
Simulation time 5705708981 ps
CPU time 203.88 seconds
Started Jul 03 06:04:54 PM PDT 24
Finished Jul 03 06:08:18 PM PDT 24
Peak memory 237668 kb
Host smart-ed6ffe40-6620-4a64-a6f2-220567808b8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4004414033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4004414033
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3994691801
Short name T774
Test name
Test status
Simulation time 263794821 ps
CPU time 5.15 seconds
Started Jul 03 06:04:54 PM PDT 24
Finished Jul 03 06:04:59 PM PDT 24
Peak memory 240536 kb
Host smart-04e5d913-e922-4533-9443-d2bba937f318
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3994691801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3994691801
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1423587880
Short name T764
Test name
Test status
Simulation time 309007864 ps
CPU time 8.19 seconds
Started Jul 03 06:04:56 PM PDT 24
Finished Jul 03 06:05:05 PM PDT 24
Peak memory 240972 kb
Host smart-90281511-3d87-4026-9ac0-d03fdd2fbe5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423587880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1423587880
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3065907451
Short name T803
Test name
Test status
Simulation time 123705497 ps
CPU time 6.61 seconds
Started Jul 03 06:04:52 PM PDT 24
Finished Jul 03 06:04:59 PM PDT 24
Peak memory 237568 kb
Host smart-e99c6a5d-1972-425a-9a45-8d2c993e285f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3065907451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3065907451
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1417391036
Short name T712
Test name
Test status
Simulation time 7873018 ps
CPU time 1.26 seconds
Started Jul 03 06:04:55 PM PDT 24
Finished Jul 03 06:04:56 PM PDT 24
Peak memory 236692 kb
Host smart-161900bd-dad0-40e0-b09d-f8682e184598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1417391036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1417391036
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3704068998
Short name T814
Test name
Test status
Simulation time 1679401235 ps
CPU time 28.4 seconds
Started Jul 03 06:04:57 PM PDT 24
Finished Jul 03 06:05:26 PM PDT 24
Peak memory 245836 kb
Host smart-7ed86ae9-ea45-4e07-a4f5-f73f1ed195e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3704068998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3704068998
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.824424805
Short name T139
Test name
Test status
Simulation time 2523701878 ps
CPU time 176.01 seconds
Started Jul 03 06:04:54 PM PDT 24
Finished Jul 03 06:07:50 PM PDT 24
Peak memory 257252 kb
Host smart-676a6071-599e-4129-b83d-23a0d2a3e298
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=824424805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.824424805
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.54551071
Short name T706
Test name
Test status
Simulation time 361162950 ps
CPU time 10.65 seconds
Started Jul 03 06:04:53 PM PDT 24
Finished Jul 03 06:05:03 PM PDT 24
Peak memory 254212 kb
Host smart-87d5188a-f4bc-4323-b6a6-055a88ed44f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=54551071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.54551071
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1280240904
Short name T766
Test name
Test status
Simulation time 20402483 ps
CPU time 1.41 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:37 PM PDT 24
Peak memory 236768 kb
Host smart-20840ec1-c081-4109-a98b-18ff8342dcd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1280240904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1280240904
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3233874648
Short name T710
Test name
Test status
Simulation time 10377862 ps
CPU time 1.29 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 236684 kb
Host smart-160f68ce-70e3-49ea-88af-2965a36e1839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3233874648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3233874648
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.947905940
Short name T784
Test name
Test status
Simulation time 10525742 ps
CPU time 1.3 seconds
Started Jul 03 06:05:30 PM PDT 24
Finished Jul 03 06:05:33 PM PDT 24
Peak memory 235624 kb
Host smart-f2bd8e32-7a24-43f9-96de-151137d7d3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=947905940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.947905940
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2621128258
Short name T720
Test name
Test status
Simulation time 10720482 ps
CPU time 1.34 seconds
Started Jul 03 06:05:32 PM PDT 24
Finished Jul 03 06:05:33 PM PDT 24
Peak memory 237592 kb
Host smart-978f9d35-1743-408a-8a53-cbe3fe186fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2621128258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2621128258
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1967571865
Short name T323
Test name
Test status
Simulation time 26868288 ps
CPU time 1.51 seconds
Started Jul 03 06:05:36 PM PDT 24
Finished Jul 03 06:05:38 PM PDT 24
Peak memory 237624 kb
Host smart-90ba61b9-7c05-4c54-bfc2-5561bb4c6146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1967571865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1967571865
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.136530493
Short name T793
Test name
Test status
Simulation time 13400644 ps
CPU time 1.78 seconds
Started Jul 03 06:05:36 PM PDT 24
Finished Jul 03 06:05:38 PM PDT 24
Peak memory 237620 kb
Host smart-b0ff2a6b-2688-4ec0-b25c-b975b687c3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=136530493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.136530493
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1150048630
Short name T740
Test name
Test status
Simulation time 22687869 ps
CPU time 1.47 seconds
Started Jul 03 06:05:31 PM PDT 24
Finished Jul 03 06:05:33 PM PDT 24
Peak memory 236688 kb
Host smart-240d894e-4615-4beb-84ab-ac04876accc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1150048630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1150048630
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.506894265
Short name T826
Test name
Test status
Simulation time 11818910 ps
CPU time 1.33 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 236684 kb
Host smart-182428be-1355-4129-bec5-7cc71f9708e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=506894265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.506894265
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.562950316
Short name T321
Test name
Test status
Simulation time 8035517 ps
CPU time 1.48 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 237588 kb
Host smart-bfe757ec-7a54-4f4e-af9c-7a1b50a07869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=562950316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.562950316
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.744819201
Short name T829
Test name
Test status
Simulation time 8295596 ps
CPU time 1.32 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:37 PM PDT 24
Peak memory 236684 kb
Host smart-c85e90fe-d90e-48c1-b1f5-cf4905a1f35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=744819201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.744819201
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1674224745
Short name T751
Test name
Test status
Simulation time 259246526 ps
CPU time 5.08 seconds
Started Jul 03 06:04:57 PM PDT 24
Finished Jul 03 06:05:03 PM PDT 24
Peak memory 237652 kb
Host smart-15b6191b-c0db-4d48-a6c6-f1fdf6971835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674224745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1674224745
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4215103479
Short name T762
Test name
Test status
Simulation time 750140256 ps
CPU time 4.74 seconds
Started Jul 03 06:04:55 PM PDT 24
Finished Jul 03 06:05:00 PM PDT 24
Peak memory 236660 kb
Host smart-5574f900-59d7-4964-b4d9-55fa4e02aed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4215103479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4215103479
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1369615730
Short name T807
Test name
Test status
Simulation time 18638587 ps
CPU time 1.31 seconds
Started Jul 03 06:04:55 PM PDT 24
Finished Jul 03 06:04:57 PM PDT 24
Peak memory 237472 kb
Host smart-d8b1e7fc-ca3d-45ae-b21a-7db5152ccc2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1369615730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1369615730
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.779143133
Short name T715
Test name
Test status
Simulation time 710469512 ps
CPU time 49.83 seconds
Started Jul 03 06:04:57 PM PDT 24
Finished Jul 03 06:05:47 PM PDT 24
Peak memory 245832 kb
Host smart-95b3cc25-82ae-4eb3-af71-21962fb6746c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=779143133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.779143133
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2668440443
Short name T791
Test name
Test status
Simulation time 118183622 ps
CPU time 7.65 seconds
Started Jul 03 06:04:56 PM PDT 24
Finished Jul 03 06:05:04 PM PDT 24
Peak memory 248488 kb
Host smart-7c87ca37-7cf5-4044-85ca-795a81bb4884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2668440443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2668440443
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1803847923
Short name T777
Test name
Test status
Simulation time 484788190 ps
CPU time 38.85 seconds
Started Jul 03 06:04:57 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 240520 kb
Host smart-e91da63c-4617-439b-96a1-ae86edf2fd89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1803847923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1803847923
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1026630174
Short name T768
Test name
Test status
Simulation time 129490064 ps
CPU time 5.73 seconds
Started Jul 03 06:05:00 PM PDT 24
Finished Jul 03 06:05:06 PM PDT 24
Peak memory 238728 kb
Host smart-7084d55d-e9f2-401b-ab04-9b571bd7890d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026630174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1026630174
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3096127523
Short name T162
Test name
Test status
Simulation time 484073730 ps
CPU time 4.75 seconds
Started Jul 03 06:04:56 PM PDT 24
Finished Jul 03 06:05:01 PM PDT 24
Peak memory 237572 kb
Host smart-ac4aa1bb-4004-4c44-b00a-915b719edfec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3096127523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3096127523
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.635795072
Short name T753
Test name
Test status
Simulation time 9591034 ps
CPU time 1.47 seconds
Started Jul 03 06:04:54 PM PDT 24
Finished Jul 03 06:04:56 PM PDT 24
Peak memory 237632 kb
Host smart-e3b2ca79-c8be-40d6-812d-94ee10740fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=635795072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.635795072
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.49942009
Short name T748
Test name
Test status
Simulation time 514199698 ps
CPU time 37.62 seconds
Started Jul 03 06:04:56 PM PDT 24
Finished Jul 03 06:05:34 PM PDT 24
Peak memory 248744 kb
Host smart-9be37d7e-e98c-4184-a714-0cb9bc4bb1dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=49942009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outst
anding.49942009
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3552011337
Short name T112
Test name
Test status
Simulation time 14607096985 ps
CPU time 490.33 seconds
Started Jul 03 06:04:56 PM PDT 24
Finished Jul 03 06:13:06 PM PDT 24
Peak memory 268576 kb
Host smart-c34bc637-447a-4f38-bd09-60e8d281f2b1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552011337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3552011337
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1895984200
Short name T732
Test name
Test status
Simulation time 1079826729 ps
CPU time 10.69 seconds
Started Jul 03 06:04:56 PM PDT 24
Finished Jul 03 06:05:07 PM PDT 24
Peak memory 248864 kb
Host smart-911b745b-598d-4526-9963-d5136941d8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1895984200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1895984200
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3890815460
Short name T816
Test name
Test status
Simulation time 181549955 ps
CPU time 9.21 seconds
Started Jul 03 06:05:01 PM PDT 24
Finished Jul 03 06:05:10 PM PDT 24
Peak memory 251908 kb
Host smart-e2eb2b63-09e0-4f9c-9280-d7559b94e437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890815460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3890815460
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3747789794
Short name T786
Test name
Test status
Simulation time 16341148 ps
CPU time 1.33 seconds
Started Jul 03 06:04:59 PM PDT 24
Finished Jul 03 06:05:00 PM PDT 24
Peak memory 236624 kb
Host smart-1fc327f6-cb14-4402-a900-f142016dcaf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3747789794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3747789794
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3917450302
Short name T718
Test name
Test status
Simulation time 355492075 ps
CPU time 24.22 seconds
Started Jul 03 06:05:03 PM PDT 24
Finished Jul 03 06:05:27 PM PDT 24
Peak memory 245796 kb
Host smart-c1ee3132-bd1d-4dc3-97ca-3b1940e324d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3917450302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3917450302
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2050155964
Short name T130
Test name
Test status
Simulation time 2009542265 ps
CPU time 160.18 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:07:43 PM PDT 24
Peak memory 257200 kb
Host smart-8c5bba3c-3658-433a-9575-9149f60c918a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2050155964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2050155964
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2067490025
Short name T126
Test name
Test status
Simulation time 9167576836 ps
CPU time 608.12 seconds
Started Jul 03 06:04:58 PM PDT 24
Finished Jul 03 06:15:07 PM PDT 24
Peak memory 270548 kb
Host smart-8940602d-ba20-41c6-8457-7ead13e66a58
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067490025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2067490025
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2505967173
Short name T705
Test name
Test status
Simulation time 78134607 ps
CPU time 10.12 seconds
Started Jul 03 06:04:58 PM PDT 24
Finished Jul 03 06:05:08 PM PDT 24
Peak memory 248872 kb
Host smart-0f7774d7-c8b8-425d-bc02-0b90b7cfcdc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2505967173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2505967173
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1639853731
Short name T830
Test name
Test status
Simulation time 75888306 ps
CPU time 6.11 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:05:09 PM PDT 24
Peak memory 239740 kb
Host smart-f4b285dc-0b61-4147-a759-ad1c4ffa93d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639853731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1639853731
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2317654249
Short name T742
Test name
Test status
Simulation time 480190977 ps
CPU time 7.55 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:05:10 PM PDT 24
Peak memory 240576 kb
Host smart-4bfd9efb-4a74-4670-b6f9-2893c6371752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2317654249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2317654249
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1707080202
Short name T809
Test name
Test status
Simulation time 14865524 ps
CPU time 1.32 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:05:03 PM PDT 24
Peak memory 236636 kb
Host smart-e24652c6-d066-4d7f-8b02-cc242ff01d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1707080202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1707080202
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4108724975
Short name T770
Test name
Test status
Simulation time 1403342303 ps
CPU time 47.85 seconds
Started Jul 03 06:05:04 PM PDT 24
Finished Jul 03 06:05:52 PM PDT 24
Peak memory 245804 kb
Host smart-81524fe6-aad2-4373-9298-959999e3ee8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4108724975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4108724975
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.333593060
Short name T823
Test name
Test status
Simulation time 26513475139 ps
CPU time 487.54 seconds
Started Jul 03 06:05:03 PM PDT 24
Finished Jul 03 06:13:11 PM PDT 24
Peak memory 265448 kb
Host smart-7f5fc549-aed9-45d2-8d9c-6785b354709b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333593060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.333593060
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1408331131
Short name T726
Test name
Test status
Simulation time 367800048 ps
CPU time 5.84 seconds
Started Jul 03 06:05:01 PM PDT 24
Finished Jul 03 06:05:07 PM PDT 24
Peak memory 248880 kb
Host smart-a2053eee-ce37-4161-b353-9fd707ab06a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1408331131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1408331131
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.710871067
Short name T783
Test name
Test status
Simulation time 1943883051 ps
CPU time 11.81 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:05:14 PM PDT 24
Peak memory 250836 kb
Host smart-18327db6-66e9-4736-9d53-e5dd5dac3409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710871067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.710871067
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1396346012
Short name T758
Test name
Test status
Simulation time 68980595 ps
CPU time 3.6 seconds
Started Jul 03 06:05:04 PM PDT 24
Finished Jul 03 06:05:08 PM PDT 24
Peak memory 237596 kb
Host smart-819e9e11-75af-4005-a647-01b3919fd423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1396346012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1396346012
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3662529009
Short name T324
Test name
Test status
Simulation time 48622846 ps
CPU time 1.51 seconds
Started Jul 03 06:05:03 PM PDT 24
Finished Jul 03 06:05:05 PM PDT 24
Peak memory 237584 kb
Host smart-bc62c477-e06d-489d-8493-2b51e97602e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3662529009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3662529009
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2883346529
Short name T795
Test name
Test status
Simulation time 1333893491 ps
CPU time 52.5 seconds
Started Jul 03 06:05:05 PM PDT 24
Finished Jul 03 06:05:58 PM PDT 24
Peak memory 245832 kb
Host smart-f78fd136-15ce-4ebf-a326-003bfde9343b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2883346529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2883346529
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2079443814
Short name T138
Test name
Test status
Simulation time 15141921827 ps
CPU time 1106.11 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:23:28 PM PDT 24
Peak memory 265500 kb
Host smart-a55c5442-82c5-458d-adfd-9fcba3b149f1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079443814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2079443814
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1055831157
Short name T827
Test name
Test status
Simulation time 51122228 ps
CPU time 6 seconds
Started Jul 03 06:05:02 PM PDT 24
Finished Jul 03 06:05:09 PM PDT 24
Peak memory 253292 kb
Host smart-d7e0e9bb-c240-45cd-a993-e31e936f6395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1055831157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1055831157
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3149844123
Short name T478
Test name
Test status
Simulation time 34295576604 ps
CPU time 2003.08 seconds
Started Jul 03 06:14:50 PM PDT 24
Finished Jul 03 06:48:14 PM PDT 24
Peak memory 274036 kb
Host smart-5173abe7-b4fa-4a51-b2e8-aa3211239098
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149844123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3149844123
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1223364826
Short name T681
Test name
Test status
Simulation time 1477713477 ps
CPU time 42.04 seconds
Started Jul 03 06:14:52 PM PDT 24
Finished Jul 03 06:15:34 PM PDT 24
Peak memory 256588 kb
Host smart-bc3792c4-b352-43e3-962b-eb559639788d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12233
64826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1223364826
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3887941542
Short name T421
Test name
Test status
Simulation time 1118878871 ps
CPU time 61.55 seconds
Started Jul 03 06:14:52 PM PDT 24
Finished Jul 03 06:15:53 PM PDT 24
Peak memory 249284 kb
Host smart-e617f0f9-c1bc-48aa-bc21-3159eb2b98f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38879
41542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3887941542
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1597351616
Short name T335
Test name
Test status
Simulation time 13206541145 ps
CPU time 1220.1 seconds
Started Jul 03 06:14:55 PM PDT 24
Finished Jul 03 06:35:16 PM PDT 24
Peak memory 282200 kb
Host smart-5ec7563e-3a53-41d9-aa07-b19e3321ca27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597351616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1597351616
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3444895600
Short name T471
Test name
Test status
Simulation time 1888797175 ps
CPU time 78.03 seconds
Started Jul 03 06:14:55 PM PDT 24
Finished Jul 03 06:16:14 PM PDT 24
Peak memory 254340 kb
Host smart-ac845e93-b8d2-4511-9642-522b78320fa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444895600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3444895600
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1643810500
Short name T434
Test name
Test status
Simulation time 51987112 ps
CPU time 4.29 seconds
Started Jul 03 06:14:49 PM PDT 24
Finished Jul 03 06:14:54 PM PDT 24
Peak memory 251812 kb
Host smart-e9ff59c8-7351-4d01-82f2-5a6e1b61488f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16438
10500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1643810500
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1705570489
Short name T377
Test name
Test status
Simulation time 1005243387 ps
CPU time 24.1 seconds
Started Jul 03 06:14:51 PM PDT 24
Finished Jul 03 06:15:15 PM PDT 24
Peak memory 249228 kb
Host smart-9a3c3690-04ce-4301-94b3-3ec62859bfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17055
70489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1705570489
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1962429456
Short name T13
Test name
Test status
Simulation time 214948107 ps
CPU time 13.21 seconds
Started Jul 03 06:14:57 PM PDT 24
Finished Jul 03 06:15:11 PM PDT 24
Peak memory 271796 kb
Host smart-f651b9f0-8a31-49d2-8142-76a76bd8abbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1962429456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1962429456
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.413662457
Short name T23
Test name
Test status
Simulation time 894230946 ps
CPU time 58.91 seconds
Started Jul 03 06:14:51 PM PDT 24
Finished Jul 03 06:15:51 PM PDT 24
Peak memory 257264 kb
Host smart-e5372419-5bf6-405f-b0cf-96385e38f48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41366
2457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.413662457
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.699052672
Short name T483
Test name
Test status
Simulation time 625557317 ps
CPU time 13.33 seconds
Started Jul 03 06:14:48 PM PDT 24
Finished Jul 03 06:15:02 PM PDT 24
Peak memory 257440 kb
Host smart-7e5d009f-50a2-46f6-911b-f4d79badd172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69905
2672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.699052672
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2737282445
Short name T622
Test name
Test status
Simulation time 45959326345 ps
CPU time 2006.85 seconds
Started Jul 03 06:14:58 PM PDT 24
Finished Jul 03 06:48:25 PM PDT 24
Peak memory 305844 kb
Host smart-40ed2632-2255-4332-a79a-2778b7b98143
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737282445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2737282445
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.683031269
Short name T192
Test name
Test status
Simulation time 225433981 ps
CPU time 3.8 seconds
Started Jul 03 06:15:10 PM PDT 24
Finished Jul 03 06:15:15 PM PDT 24
Peak memory 249548 kb
Host smart-15debc58-3c5f-4757-8782-cc49bf49d843
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=683031269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.683031269
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3488711987
Short name T388
Test name
Test status
Simulation time 66231746035 ps
CPU time 2407.44 seconds
Started Jul 03 06:15:05 PM PDT 24
Finished Jul 03 06:55:13 PM PDT 24
Peak memory 289364 kb
Host smart-0ddf0939-65c4-45a0-9d1d-e7d3d039fb08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488711987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3488711987
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2046860593
Short name T487
Test name
Test status
Simulation time 1115821336 ps
CPU time 14.26 seconds
Started Jul 03 06:15:09 PM PDT 24
Finished Jul 03 06:15:24 PM PDT 24
Peak memory 249264 kb
Host smart-f461ac6b-0fa6-4169-9730-7650063f2568
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2046860593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2046860593
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.4187505879
Short name T574
Test name
Test status
Simulation time 20677242229 ps
CPU time 155.04 seconds
Started Jul 03 06:15:03 PM PDT 24
Finished Jul 03 06:17:38 PM PDT 24
Peak memory 257520 kb
Host smart-f1c76887-c3df-4b2a-ac8f-453d46f3e174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
05879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.4187505879
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3319451302
Short name T606
Test name
Test status
Simulation time 321396748 ps
CPU time 6.07 seconds
Started Jul 03 06:15:02 PM PDT 24
Finished Jul 03 06:15:08 PM PDT 24
Peak memory 249280 kb
Host smart-46637a9f-7b14-478e-acfc-354f85f028f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
51302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3319451302
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1610522255
Short name T261
Test name
Test status
Simulation time 115545357273 ps
CPU time 2524.74 seconds
Started Jul 03 06:15:09 PM PDT 24
Finished Jul 03 06:57:15 PM PDT 24
Peak memory 290272 kb
Host smart-3e707dc2-edf6-4405-9acf-3f76e45086d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610522255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1610522255
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4020808789
Short name T668
Test name
Test status
Simulation time 85129031373 ps
CPU time 1365.63 seconds
Started Jul 03 06:15:08 PM PDT 24
Finished Jul 03 06:37:54 PM PDT 24
Peak memory 273704 kb
Host smart-4cac7979-8cfb-49f4-a9d7-dc491beb3391
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020808789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4020808789
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.100942179
Short name T685
Test name
Test status
Simulation time 626615599 ps
CPU time 21.23 seconds
Started Jul 03 06:15:03 PM PDT 24
Finished Jul 03 06:15:24 PM PDT 24
Peak memory 256624 kb
Host smart-9ca7112a-4a9f-452f-a60f-722a6d032f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10094
2179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.100942179
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2342084736
Short name T65
Test name
Test status
Simulation time 902748514 ps
CPU time 32.31 seconds
Started Jul 03 06:15:02 PM PDT 24
Finished Jul 03 06:15:35 PM PDT 24
Peak memory 249060 kb
Host smart-d89b3c89-4f8d-4c35-b1b6-3767f13964b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23420
84736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2342084736
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1484908285
Short name T31
Test name
Test status
Simulation time 438464607 ps
CPU time 23.16 seconds
Started Jul 03 06:15:13 PM PDT 24
Finished Jul 03 06:15:37 PM PDT 24
Peak memory 270728 kb
Host smart-eb434931-665c-4514-a461-f4f307c5cf1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1484908285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1484908285
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1378669160
Short name T536
Test name
Test status
Simulation time 80480833 ps
CPU time 6.93 seconds
Started Jul 03 06:15:05 PM PDT 24
Finished Jul 03 06:15:12 PM PDT 24
Peak memory 251744 kb
Host smart-a9ba6569-8499-4c0c-a89b-ee3b23103161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13786
69160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1378669160
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3918402832
Short name T387
Test name
Test status
Simulation time 1281665248 ps
CPU time 15.37 seconds
Started Jul 03 06:14:57 PM PDT 24
Finished Jul 03 06:15:13 PM PDT 24
Peak memory 249304 kb
Host smart-87721e82-ac52-42a1-89c2-f5bddbe9e4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
02832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3918402832
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3643061950
Short name T78
Test name
Test status
Simulation time 79815632692 ps
CPU time 2904.28 seconds
Started Jul 03 06:15:09 PM PDT 24
Finished Jul 03 07:03:34 PM PDT 24
Peak memory 290416 kb
Host smart-896e4bda-d7d7-4fa9-9a53-cf8c5290ba56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643061950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3643061950
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.4007662991
Short name T696
Test name
Test status
Simulation time 12105244007 ps
CPU time 650.31 seconds
Started Jul 03 06:16:41 PM PDT 24
Finished Jul 03 06:27:32 PM PDT 24
Peak memory 273116 kb
Host smart-ea5baa60-63b0-4ba2-9666-f815d5b4f4c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007662991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4007662991
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1743032890
Short name T366
Test name
Test status
Simulation time 466646389 ps
CPU time 22.92 seconds
Started Jul 03 06:16:43 PM PDT 24
Finished Jul 03 06:17:06 PM PDT 24
Peak memory 249204 kb
Host smart-09e0b9c7-7825-4b62-b53a-4caed3eba0d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1743032890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1743032890
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1946991508
Short name T392
Test name
Test status
Simulation time 1495414514 ps
CPU time 89.06 seconds
Started Jul 03 06:16:39 PM PDT 24
Finished Jul 03 06:18:08 PM PDT 24
Peak memory 257524 kb
Host smart-d8366bf5-6cbc-44bc-a6aa-96cbebb3ef2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
91508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1946991508
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.555593494
Short name T626
Test name
Test status
Simulation time 738197637 ps
CPU time 40.7 seconds
Started Jul 03 06:16:37 PM PDT 24
Finished Jul 03 06:17:18 PM PDT 24
Peak memory 249700 kb
Host smart-314da14c-a7c4-43e9-a50e-0a181f1ad5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55559
3494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.555593494
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.651554033
Short name T307
Test name
Test status
Simulation time 43894028403 ps
CPU time 3021.19 seconds
Started Jul 03 06:16:41 PM PDT 24
Finished Jul 03 07:07:03 PM PDT 24
Peak memory 290288 kb
Host smart-f0ad3805-3e89-40c5-87d2-c989c89ad519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651554033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.651554033
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1645560658
Short name T347
Test name
Test status
Simulation time 56475760435 ps
CPU time 2149.95 seconds
Started Jul 03 06:16:44 PM PDT 24
Finished Jul 03 06:52:34 PM PDT 24
Peak memory 285272 kb
Host smart-dd8d0f79-8186-477d-807e-b53656878f70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645560658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1645560658
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3105208935
Short name T494
Test name
Test status
Simulation time 38175472805 ps
CPU time 596.12 seconds
Started Jul 03 06:16:40 PM PDT 24
Finished Jul 03 06:26:36 PM PDT 24
Peak memory 249420 kb
Host smart-1b85b994-a94b-48ba-84fb-ca5efb3e2a4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105208935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3105208935
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3863313354
Short name T703
Test name
Test status
Simulation time 412180418 ps
CPU time 10.44 seconds
Started Jul 03 06:16:40 PM PDT 24
Finished Jul 03 06:16:51 PM PDT 24
Peak memory 249336 kb
Host smart-6864e607-d69b-4ee4-8f12-d327fd86a1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
13354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3863313354
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.225472057
Short name T544
Test name
Test status
Simulation time 2013470964 ps
CPU time 28.3 seconds
Started Jul 03 06:16:38 PM PDT 24
Finished Jul 03 06:17:07 PM PDT 24
Peak memory 256912 kb
Host smart-993cadaa-833c-4770-a8ee-c03ab30f14fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
2057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.225472057
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.373822916
Short name T241
Test name
Test status
Simulation time 849583296 ps
CPU time 15.68 seconds
Started Jul 03 06:16:38 PM PDT 24
Finished Jul 03 06:16:54 PM PDT 24
Peak memory 249208 kb
Host smart-f3b9dc2d-ac3c-4dc7-b90f-3ed00048d899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37382
2916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.373822916
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3613684080
Short name T678
Test name
Test status
Simulation time 7176014906 ps
CPU time 35.6 seconds
Started Jul 03 06:16:37 PM PDT 24
Finished Jul 03 06:17:13 PM PDT 24
Peak memory 257536 kb
Host smart-9b30073e-dea5-47dc-9ce0-93b3c0b5223d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36136
84080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3613684080
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.805286325
Short name T680
Test name
Test status
Simulation time 27887713174 ps
CPU time 1571.68 seconds
Started Jul 03 06:16:44 PM PDT 24
Finished Jul 03 06:42:56 PM PDT 24
Peak memory 289948 kb
Host smart-bfb6178a-f6ec-4981-ae61-42f9a3bcbeb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805286325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.805286325
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1279543129
Short name T167
Test name
Test status
Simulation time 136198708 ps
CPU time 3.25 seconds
Started Jul 03 06:16:50 PM PDT 24
Finished Jul 03 06:16:54 PM PDT 24
Peak memory 249616 kb
Host smart-1e22130c-33e5-4242-a1b3-cc43aaad2c4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1279543129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1279543129
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2780957734
Short name T647
Test name
Test status
Simulation time 32760733296 ps
CPU time 2005.49 seconds
Started Jul 03 06:16:48 PM PDT 24
Finished Jul 03 06:50:14 PM PDT 24
Peak memory 284980 kb
Host smart-87ede389-7fd8-4edf-b3aa-d6b7e58d6f77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780957734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2780957734
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.167982567
Short name T449
Test name
Test status
Simulation time 892503380 ps
CPU time 13.48 seconds
Started Jul 03 06:16:50 PM PDT 24
Finished Jul 03 06:17:04 PM PDT 24
Peak memory 249232 kb
Host smart-fb47d824-92a9-4497-9bb9-5ebf037b8c00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=167982567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.167982567
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2773941058
Short name T616
Test name
Test status
Simulation time 14392242024 ps
CPU time 252.24 seconds
Started Jul 03 06:16:53 PM PDT 24
Finished Jul 03 06:21:06 PM PDT 24
Peak memory 257500 kb
Host smart-a45398ff-652a-4ced-87f8-f24154f94378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27739
41058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2773941058
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2786086208
Short name T416
Test name
Test status
Simulation time 455372354 ps
CPU time 26.33 seconds
Started Jul 03 06:16:53 PM PDT 24
Finished Jul 03 06:17:20 PM PDT 24
Peak memory 248580 kb
Host smart-26b8a55f-c2ee-43f9-b393-ff53e191d21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27860
86208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2786086208
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3923599884
Short name T624
Test name
Test status
Simulation time 83338600824 ps
CPU time 2718.11 seconds
Started Jul 03 06:16:46 PM PDT 24
Finished Jul 03 07:02:05 PM PDT 24
Peak memory 289532 kb
Host smart-a5765c77-ce14-4908-b111-d8a82dcef562
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923599884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3923599884
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1489547129
Short name T198
Test name
Test status
Simulation time 135738527682 ps
CPU time 2054.25 seconds
Started Jul 03 06:16:50 PM PDT 24
Finished Jul 03 06:51:05 PM PDT 24
Peak memory 273792 kb
Host smart-46fe77ea-f8fe-4deb-b3b7-cd9ec569486b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489547129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1489547129
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.384496776
Short name T350
Test name
Test status
Simulation time 2328806792 ps
CPU time 15.6 seconds
Started Jul 03 06:16:48 PM PDT 24
Finished Jul 03 06:17:04 PM PDT 24
Peak memory 249404 kb
Host smart-ef3d446e-6b91-4121-a67b-e0010592c868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38449
6776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.384496776
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.790492089
Short name T522
Test name
Test status
Simulation time 232082732 ps
CPU time 7.82 seconds
Started Jul 03 06:16:47 PM PDT 24
Finished Jul 03 06:16:55 PM PDT 24
Peak memory 255300 kb
Host smart-5d91bcd9-5500-40a3-a0a8-c9fe182c6aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79049
2089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.790492089
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3156686007
Short name T62
Test name
Test status
Simulation time 775737771 ps
CPU time 57.52 seconds
Started Jul 03 06:16:52 PM PDT 24
Finished Jul 03 06:17:50 PM PDT 24
Peak memory 250172 kb
Host smart-668b87d5-1728-4ccb-8aae-b5efa56eb20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31566
86007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3156686007
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1804218695
Short name T477
Test name
Test status
Simulation time 2527931062 ps
CPU time 23.57 seconds
Started Jul 03 06:16:45 PM PDT 24
Finished Jul 03 06:17:09 PM PDT 24
Peak memory 257032 kb
Host smart-c3007704-c134-4111-9769-a7395edf46d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18042
18695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1804218695
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2437655191
Short name T569
Test name
Test status
Simulation time 4434378199 ps
CPU time 287.94 seconds
Started Jul 03 06:16:51 PM PDT 24
Finished Jul 03 06:21:40 PM PDT 24
Peak memory 257504 kb
Host smart-d56442f6-f69d-41d2-8fd8-7d5679995e5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437655191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2437655191
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2919673947
Short name T638
Test name
Test status
Simulation time 76610694326 ps
CPU time 7954.28 seconds
Started Jul 03 06:16:53 PM PDT 24
Finished Jul 03 08:29:28 PM PDT 24
Peak memory 354704 kb
Host smart-998782b1-1bc1-4e8f-875f-985e1aa28042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919673947 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2919673947
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2938294431
Short name T691
Test name
Test status
Simulation time 39633985674 ps
CPU time 2274.76 seconds
Started Jul 03 06:16:58 PM PDT 24
Finished Jul 03 06:54:53 PM PDT 24
Peak memory 273416 kb
Host smart-e2b3ca5f-c98b-40ee-a18d-c848a4251f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938294431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2938294431
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3029956000
Short name T418
Test name
Test status
Simulation time 289544551 ps
CPU time 15.32 seconds
Started Jul 03 06:16:57 PM PDT 24
Finished Jul 03 06:17:12 PM PDT 24
Peak memory 249180 kb
Host smart-612c9e59-e313-4976-9647-86f23b52a2ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3029956000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3029956000
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1438171223
Short name T698
Test name
Test status
Simulation time 97985938 ps
CPU time 8.22 seconds
Started Jul 03 06:16:54 PM PDT 24
Finished Jul 03 06:17:03 PM PDT 24
Peak memory 252444 kb
Host smart-dae9cb6b-e456-40f2-961d-60823bdf03d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14381
71223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1438171223
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2699574551
Short name T643
Test name
Test status
Simulation time 398623871 ps
CPU time 18.55 seconds
Started Jul 03 06:16:57 PM PDT 24
Finished Jul 03 06:17:16 PM PDT 24
Peak memory 256028 kb
Host smart-b0d7c9d0-24d7-4534-aaaf-ac5bfed5eb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26995
74551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2699574551
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3155592321
Short name T16
Test name
Test status
Simulation time 29434177622 ps
CPU time 1722.88 seconds
Started Jul 03 06:16:58 PM PDT 24
Finished Jul 03 06:45:42 PM PDT 24
Peak memory 273996 kb
Host smart-8a259aa8-f52c-4420-b004-265fa6e10e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155592321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3155592321
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3953406069
Short name T694
Test name
Test status
Simulation time 7596475429 ps
CPU time 310.06 seconds
Started Jul 03 06:16:58 PM PDT 24
Finished Jul 03 06:22:08 PM PDT 24
Peak memory 249364 kb
Host smart-8a6544c5-508a-41d0-8df9-9306028e6c70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953406069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3953406069
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2591503933
Short name T371
Test name
Test status
Simulation time 487285987 ps
CPU time 33.1 seconds
Started Jul 03 06:16:53 PM PDT 24
Finished Jul 03 06:17:26 PM PDT 24
Peak memory 256640 kb
Host smart-f437c643-646a-4ab0-bd40-2aa1e3d221fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25915
03933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2591503933
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2948044227
Short name T423
Test name
Test status
Simulation time 1669302641 ps
CPU time 29.6 seconds
Started Jul 03 06:16:50 PM PDT 24
Finished Jul 03 06:17:20 PM PDT 24
Peak memory 249268 kb
Host smart-8ad7bae2-6460-4c9a-adc1-49ad97d61917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
44227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2948044227
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.783871885
Short name T329
Test name
Test status
Simulation time 628414383 ps
CPU time 41.99 seconds
Started Jul 03 06:16:51 PM PDT 24
Finished Jul 03 06:17:34 PM PDT 24
Peak memory 257400 kb
Host smart-ab89505d-b02c-405b-911d-0753c4df0259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78387
1885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.783871885
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1055250801
Short name T293
Test name
Test status
Simulation time 73596445168 ps
CPU time 3496.32 seconds
Started Jul 03 06:17:00 PM PDT 24
Finished Jul 03 07:15:17 PM PDT 24
Peak memory 306436 kb
Host smart-64307d37-ffeb-46b2-a744-480bc0028457
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055250801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1055250801
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.153210946
Short name T187
Test name
Test status
Simulation time 21140149 ps
CPU time 2.42 seconds
Started Jul 03 06:17:14 PM PDT 24
Finished Jul 03 06:17:16 PM PDT 24
Peak memory 249576 kb
Host smart-e1b7b3d0-67ca-40bb-a449-35e937025b90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=153210946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.153210946
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2340429639
Short name T579
Test name
Test status
Simulation time 644918475465 ps
CPU time 2691.99 seconds
Started Jul 03 06:17:04 PM PDT 24
Finished Jul 03 07:01:57 PM PDT 24
Peak memory 290276 kb
Host smart-f93ded27-49af-4797-b2d8-8009420ba0b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340429639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2340429639
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3836619306
Short name T442
Test name
Test status
Simulation time 259317683 ps
CPU time 14.8 seconds
Started Jul 03 06:17:11 PM PDT 24
Finished Jul 03 06:17:26 PM PDT 24
Peak memory 249236 kb
Host smart-74b8979a-2433-40cf-87f8-3bf4af3fe0e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3836619306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3836619306
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2746833786
Short name T529
Test name
Test status
Simulation time 9393334266 ps
CPU time 278.7 seconds
Started Jul 03 06:17:04 PM PDT 24
Finished Jul 03 06:21:43 PM PDT 24
Peak memory 257128 kb
Host smart-3136c7e4-f9b5-4fb9-85e9-5d566153c95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27468
33786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2746833786
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3693936345
Short name T572
Test name
Test status
Simulation time 3607802745 ps
CPU time 19.96 seconds
Started Jul 03 06:17:03 PM PDT 24
Finished Jul 03 06:17:23 PM PDT 24
Peak memory 248852 kb
Host smart-9a6bca9e-617b-4052-bd99-be69d01d55ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36939
36345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3693936345
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1304189347
Short name T475
Test name
Test status
Simulation time 8558070226 ps
CPU time 926.92 seconds
Started Jul 03 06:17:08 PM PDT 24
Finished Jul 03 06:32:35 PM PDT 24
Peak memory 273264 kb
Host smart-3c8c62dc-4bea-4103-9f54-de351af64151
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304189347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1304189347
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2603202514
Short name T507
Test name
Test status
Simulation time 79414297380 ps
CPU time 2463.06 seconds
Started Jul 03 06:17:07 PM PDT 24
Finished Jul 03 06:58:11 PM PDT 24
Peak memory 287416 kb
Host smart-276ec698-0d16-4d49-a9ac-4c63df3835b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603202514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2603202514
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.593047806
Short name T675
Test name
Test status
Simulation time 170997445473 ps
CPU time 471.04 seconds
Started Jul 03 06:17:08 PM PDT 24
Finished Jul 03 06:24:59 PM PDT 24
Peak memory 249304 kb
Host smart-308126bf-8e56-4569-91ea-c4ae907ca12c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593047806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.593047806
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1121565185
Short name T490
Test name
Test status
Simulation time 74157265 ps
CPU time 9.15 seconds
Started Jul 03 06:17:04 PM PDT 24
Finished Jul 03 06:17:14 PM PDT 24
Peak memory 249312 kb
Host smart-b186eecb-50fb-4487-b6e3-0648b1fbe93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
65185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1121565185
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1116449824
Short name T280
Test name
Test status
Simulation time 2273991414 ps
CPU time 69.25 seconds
Started Jul 03 06:17:04 PM PDT 24
Finished Jul 03 06:18:13 PM PDT 24
Peak memory 257044 kb
Host smart-71fa2bea-d20b-43cd-9c6c-e4a9a32f8ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11164
49824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1116449824
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3252475552
Short name T285
Test name
Test status
Simulation time 4612738286 ps
CPU time 32.56 seconds
Started Jul 03 06:17:00 PM PDT 24
Finished Jul 03 06:17:33 PM PDT 24
Peak memory 257064 kb
Host smart-9f9098db-af37-4738-abc2-2dc575b829d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32524
75552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3252475552
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.369306944
Short name T534
Test name
Test status
Simulation time 7098033604 ps
CPU time 689.39 seconds
Started Jul 03 06:17:14 PM PDT 24
Finished Jul 03 06:28:44 PM PDT 24
Peak memory 273912 kb
Host smart-7bc99cd5-9093-4128-aed3-a761764b95a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369306944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.369306944
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2991294090
Short name T546
Test name
Test status
Simulation time 602631248 ps
CPU time 10.15 seconds
Started Jul 03 06:17:17 PM PDT 24
Finished Jul 03 06:17:27 PM PDT 24
Peak memory 249328 kb
Host smart-6e016861-d066-40ae-9bc8-bbb2274206d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2991294090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2991294090
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.105239036
Short name T463
Test name
Test status
Simulation time 91099725465 ps
CPU time 278.36 seconds
Started Jul 03 06:17:17 PM PDT 24
Finished Jul 03 06:21:55 PM PDT 24
Peak memory 251488 kb
Host smart-798276ac-572c-493d-b539-5684c4ee53fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
9036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.105239036
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1915645582
Short name T36
Test name
Test status
Simulation time 1170609654 ps
CPU time 59.65 seconds
Started Jul 03 06:17:16 PM PDT 24
Finished Jul 03 06:18:16 PM PDT 24
Peak memory 257196 kb
Host smart-121af94c-54a5-4bea-a3d0-0207216bc5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
45582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1915645582
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.4073925158
Short name T556
Test name
Test status
Simulation time 73458679801 ps
CPU time 1258.88 seconds
Started Jul 03 06:17:20 PM PDT 24
Finished Jul 03 06:38:19 PM PDT 24
Peak memory 289360 kb
Host smart-1b4fe9f4-5a2a-4e52-8718-68fe6e4620fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073925158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4073925158
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4104909620
Short name T516
Test name
Test status
Simulation time 113965711961 ps
CPU time 1464.13 seconds
Started Jul 03 06:17:21 PM PDT 24
Finished Jul 03 06:41:45 PM PDT 24
Peak memory 273636 kb
Host smart-1fe4e7af-ebdf-4e6f-a6ae-55159486e9e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104909620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4104909620
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.848394917
Short name T592
Test name
Test status
Simulation time 406572319 ps
CPU time 14.12 seconds
Started Jul 03 06:17:16 PM PDT 24
Finished Jul 03 06:17:31 PM PDT 24
Peak memory 249316 kb
Host smart-435f0f0c-0593-4113-b860-03e0f2f7835e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84839
4917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.848394917
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.890418874
Short name T333
Test name
Test status
Simulation time 348826586 ps
CPU time 14.06 seconds
Started Jul 03 06:17:14 PM PDT 24
Finished Jul 03 06:17:28 PM PDT 24
Peak memory 255736 kb
Host smart-47636be1-6054-479c-b154-8e22871ade91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89041
8874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.890418874
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2168528681
Short name T384
Test name
Test status
Simulation time 1268422016 ps
CPU time 67.66 seconds
Started Jul 03 06:17:15 PM PDT 24
Finished Jul 03 06:18:23 PM PDT 24
Peak memory 257468 kb
Host smart-6ec9502e-e745-4e7a-add5-12346ec0a6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21685
28681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2168528681
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1616618065
Short name T587
Test name
Test status
Simulation time 44384234 ps
CPU time 4.36 seconds
Started Jul 03 06:17:15 PM PDT 24
Finished Jul 03 06:17:19 PM PDT 24
Peak memory 249152 kb
Host smart-74b10d67-61b0-486f-b771-9c2397b2304b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16166
18065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1616618065
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.4252200897
Short name T186
Test name
Test status
Simulation time 14638483 ps
CPU time 2.64 seconds
Started Jul 03 06:17:28 PM PDT 24
Finished Jul 03 06:17:31 PM PDT 24
Peak memory 249576 kb
Host smart-466d3911-d218-4791-a248-88f20eafce67
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4252200897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4252200897
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2487721245
Short name T491
Test name
Test status
Simulation time 139365010631 ps
CPU time 2131.79 seconds
Started Jul 03 06:17:23 PM PDT 24
Finished Jul 03 06:52:56 PM PDT 24
Peak memory 289832 kb
Host smart-27e2f8a6-616d-4cb0-ae58-f74bcef44be9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487721245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2487721245
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2600011265
Short name T515
Test name
Test status
Simulation time 129848335 ps
CPU time 7.97 seconds
Started Jul 03 06:17:27 PM PDT 24
Finished Jul 03 06:17:35 PM PDT 24
Peak memory 249304 kb
Host smart-bc9f955b-3736-49e6-b5e4-55802ff1b3b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2600011265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2600011265
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3397144117
Short name T586
Test name
Test status
Simulation time 1746555875 ps
CPU time 96.9 seconds
Started Jul 03 06:17:24 PM PDT 24
Finished Jul 03 06:19:01 PM PDT 24
Peak memory 256632 kb
Host smart-1e6ae2f4-6083-4004-ba87-c3bd6b55d106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33971
44117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3397144117
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2837291756
Short name T565
Test name
Test status
Simulation time 797301555 ps
CPU time 53.09 seconds
Started Jul 03 06:17:24 PM PDT 24
Finished Jul 03 06:18:17 PM PDT 24
Peak memory 257468 kb
Host smart-daa5360e-ac73-46d3-8613-7e09394939ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
91756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2837291756
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1074307700
Short name T315
Test name
Test status
Simulation time 28520002588 ps
CPU time 1642.83 seconds
Started Jul 03 06:17:24 PM PDT 24
Finished Jul 03 06:44:47 PM PDT 24
Peak memory 283772 kb
Host smart-5e54fd28-7cb0-4006-ac36-9ea54448a536
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074307700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1074307700
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2544881662
Short name T419
Test name
Test status
Simulation time 51802380035 ps
CPU time 2903.17 seconds
Started Jul 03 06:17:23 PM PDT 24
Finished Jul 03 07:05:46 PM PDT 24
Peak memory 289584 kb
Host smart-48dfe459-263d-4f5e-9078-80ed1434c2f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544881662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2544881662
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4072839353
Short name T390
Test name
Test status
Simulation time 4877566824 ps
CPU time 38.98 seconds
Started Jul 03 06:17:20 PM PDT 24
Finished Jul 03 06:17:59 PM PDT 24
Peak memory 257564 kb
Host smart-57a749fb-5a34-46e1-8092-e39dc0ac120f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40728
39353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4072839353
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1628078142
Short name T612
Test name
Test status
Simulation time 1058329533 ps
CPU time 59.22 seconds
Started Jul 03 06:17:22 PM PDT 24
Finished Jul 03 06:18:21 PM PDT 24
Peak memory 249268 kb
Host smart-fc81529c-ed4d-4abc-bb4b-893f217e77b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16280
78142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1628078142
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1923773047
Short name T96
Test name
Test status
Simulation time 825751797 ps
CPU time 16.86 seconds
Started Jul 03 06:17:24 PM PDT 24
Finished Jul 03 06:17:41 PM PDT 24
Peak memory 256708 kb
Host smart-731f102a-6326-4deb-8a6c-defa22a2287a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237
73047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1923773047
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2467828608
Short name T496
Test name
Test status
Simulation time 641318157 ps
CPU time 39.94 seconds
Started Jul 03 06:17:21 PM PDT 24
Finished Jul 03 06:18:01 PM PDT 24
Peak memory 257500 kb
Host smart-c50946b0-17f6-4b26-97e1-9a6efee05462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24678
28608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2467828608
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.4213515583
Short name T648
Test name
Test status
Simulation time 24566930506 ps
CPU time 1036.96 seconds
Started Jul 03 06:17:27 PM PDT 24
Finished Jul 03 06:34:45 PM PDT 24
Peak memory 285260 kb
Host smart-ee6bc472-603e-42cc-9adf-1f6d017e70ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213515583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.4213515583
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2126058705
Short name T19
Test name
Test status
Simulation time 140009058 ps
CPU time 3.87 seconds
Started Jul 03 06:17:37 PM PDT 24
Finished Jul 03 06:17:41 PM PDT 24
Peak memory 249600 kb
Host smart-482f3166-6bd8-4a7e-ad07-347bd7d91083
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2126058705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2126058705
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1513947873
Short name T613
Test name
Test status
Simulation time 14623399169 ps
CPU time 896.59 seconds
Started Jul 03 06:17:35 PM PDT 24
Finished Jul 03 06:32:32 PM PDT 24
Peak memory 273764 kb
Host smart-434090b1-30d5-4734-a17f-99dc7f5b2830
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513947873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1513947873
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3996172518
Short name T510
Test name
Test status
Simulation time 444074294 ps
CPU time 20.93 seconds
Started Jul 03 06:17:33 PM PDT 24
Finished Jul 03 06:17:54 PM PDT 24
Peak memory 249244 kb
Host smart-4c1481e5-cfb4-4512-84a2-75455fffbd5a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3996172518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3996172518
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.264953751
Short name T640
Test name
Test status
Simulation time 2098415709 ps
CPU time 166.22 seconds
Started Jul 03 06:17:29 PM PDT 24
Finished Jul 03 06:20:16 PM PDT 24
Peak memory 257520 kb
Host smart-7b7da1f2-f73e-44ff-83e2-7f0d39ff992a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26495
3751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.264953751
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.279117453
Short name T589
Test name
Test status
Simulation time 2126720041 ps
CPU time 38.33 seconds
Started Jul 03 06:17:32 PM PDT 24
Finished Jul 03 06:18:11 PM PDT 24
Peak memory 248964 kb
Host smart-3533cb6e-47c4-4fb4-9a53-139061c8ea32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27911
7453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.279117453
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1463503451
Short name T528
Test name
Test status
Simulation time 269540358176 ps
CPU time 2039.98 seconds
Started Jul 03 06:17:35 PM PDT 24
Finished Jul 03 06:51:36 PM PDT 24
Peak memory 273976 kb
Host smart-e18f9f30-de70-491c-a8cd-02d29a4a1052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463503451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1463503451
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2872602364
Short name T299
Test name
Test status
Simulation time 236523409861 ps
CPU time 2729.2 seconds
Started Jul 03 06:17:34 PM PDT 24
Finished Jul 03 07:03:03 PM PDT 24
Peak memory 290184 kb
Host smart-3ad241a3-8a59-40a0-a1b0-25018b71bb8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872602364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2872602364
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1463154953
Short name T667
Test name
Test status
Simulation time 6508468529 ps
CPU time 257.16 seconds
Started Jul 03 06:17:36 PM PDT 24
Finished Jul 03 06:21:53 PM PDT 24
Peak memory 249420 kb
Host smart-aee12d6e-586d-49b2-a1b5-03d695e3b9aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463154953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1463154953
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2354281006
Short name T652
Test name
Test status
Simulation time 1287381618 ps
CPU time 30.79 seconds
Started Jul 03 06:17:28 PM PDT 24
Finished Jul 03 06:17:59 PM PDT 24
Peak memory 257392 kb
Host smart-8644dfec-1aae-438f-bec9-24862d53b702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23542
81006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2354281006
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3079064349
Short name T200
Test name
Test status
Simulation time 6642482891 ps
CPU time 65.21 seconds
Started Jul 03 06:17:30 PM PDT 24
Finished Jul 03 06:18:36 PM PDT 24
Peak memory 250368 kb
Host smart-05c3ef69-c5c1-4a1f-acde-e7f36fd41d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30790
64349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3079064349
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3795170564
Short name T621
Test name
Test status
Simulation time 4155762922 ps
CPU time 68.59 seconds
Started Jul 03 06:17:29 PM PDT 24
Finished Jul 03 06:18:37 PM PDT 24
Peak memory 257076 kb
Host smart-6f308812-6776-438b-a3d7-6b1d410f1b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37951
70564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3795170564
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.252313855
Short name T596
Test name
Test status
Simulation time 171992100 ps
CPU time 19.26 seconds
Started Jul 03 06:17:29 PM PDT 24
Finished Jul 03 06:17:49 PM PDT 24
Peak memory 257428 kb
Host smart-cf0f4514-83da-486a-afa3-be06c9f4591b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25231
3855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.252313855
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2629935309
Short name T89
Test name
Test status
Simulation time 360066079065 ps
CPU time 3862.61 seconds
Started Jul 03 06:17:39 PM PDT 24
Finished Jul 03 07:22:02 PM PDT 24
Peak memory 303612 kb
Host smart-98f6d2d7-596f-4810-aff7-4284f7065496
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629935309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2629935309
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.145439931
Short name T60
Test name
Test status
Simulation time 56165248614 ps
CPU time 4847.83 seconds
Started Jul 03 06:17:38 PM PDT 24
Finished Jul 03 07:38:26 PM PDT 24
Peak memory 338024 kb
Host smart-bfb6d008-f05e-4c0a-814f-a0ec775d3653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145439931 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.145439931
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4030929420
Short name T193
Test name
Test status
Simulation time 132865112 ps
CPU time 3.33 seconds
Started Jul 03 06:17:46 PM PDT 24
Finished Jul 03 06:17:50 PM PDT 24
Peak memory 249508 kb
Host smart-d5a0dc14-3b01-4d80-a1eb-b7f1d1948a74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4030929420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4030929420
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3150127027
Short name T380
Test name
Test status
Simulation time 18822629056 ps
CPU time 1270.98 seconds
Started Jul 03 06:17:40 PM PDT 24
Finished Jul 03 06:38:51 PM PDT 24
Peak memory 273596 kb
Host smart-5a881f58-79fd-43fe-b804-3ae6499c0993
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150127027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3150127027
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1724609391
Short name T625
Test name
Test status
Simulation time 1856125901 ps
CPU time 21.75 seconds
Started Jul 03 06:17:45 PM PDT 24
Finished Jul 03 06:18:07 PM PDT 24
Peak memory 249168 kb
Host smart-b53453ab-87d0-435c-990d-f3f7548df37e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1724609391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1724609391
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.516826416
Short name T360
Test name
Test status
Simulation time 2357071100 ps
CPU time 26.92 seconds
Started Jul 03 06:17:39 PM PDT 24
Finished Jul 03 06:18:06 PM PDT 24
Peak memory 257124 kb
Host smart-f453ad80-70a0-42fe-910a-ce187bd0a2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51682
6416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.516826416
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2703356923
Short name T357
Test name
Test status
Simulation time 1339957514 ps
CPU time 32.33 seconds
Started Jul 03 06:17:37 PM PDT 24
Finished Jul 03 06:18:09 PM PDT 24
Peak memory 249228 kb
Host smart-e83990be-c535-467d-a154-7154d71d0422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27033
56923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2703356923
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2144725869
Short name T669
Test name
Test status
Simulation time 99102689523 ps
CPU time 2888.93 seconds
Started Jul 03 06:17:40 PM PDT 24
Finished Jul 03 07:05:50 PM PDT 24
Peak memory 290316 kb
Host smart-fef5ba72-eb76-4ab1-80d7-5e496206f280
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144725869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2144725869
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2416614019
Short name T521
Test name
Test status
Simulation time 189355173534 ps
CPU time 2909.28 seconds
Started Jul 03 06:17:40 PM PDT 24
Finished Jul 03 07:06:10 PM PDT 24
Peak memory 290240 kb
Host smart-08e26787-0469-4519-99af-270263204708
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416614019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2416614019
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1076097832
Short name T399
Test name
Test status
Simulation time 3474276301 ps
CPU time 45.22 seconds
Started Jul 03 06:17:39 PM PDT 24
Finished Jul 03 06:18:25 PM PDT 24
Peak memory 256656 kb
Host smart-364db334-de01-47a5-b358-a22ae07cb883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760
97832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1076097832
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1528757703
Short name T504
Test name
Test status
Simulation time 1276638310 ps
CPU time 26.55 seconds
Started Jul 03 06:17:40 PM PDT 24
Finished Jul 03 06:18:07 PM PDT 24
Peak memory 256856 kb
Host smart-37fb726b-7d97-49f6-be10-35c40b1c4f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15287
57703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1528757703
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2252110216
Short name T462
Test name
Test status
Simulation time 1619231923 ps
CPU time 34.18 seconds
Started Jul 03 06:17:39 PM PDT 24
Finished Jul 03 06:18:13 PM PDT 24
Peak memory 257464 kb
Host smart-a89c4238-d7bc-46e5-9c07-41b2048abf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22521
10216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2252110216
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.376805094
Short name T102
Test name
Test status
Simulation time 2324503176 ps
CPU time 10.2 seconds
Started Jul 03 06:17:45 PM PDT 24
Finished Jul 03 06:17:55 PM PDT 24
Peak memory 255924 kb
Host smart-181ab20d-a991-4a00-96bc-1e6af94e1916
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376805094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.376805094
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1374944043
Short name T183
Test name
Test status
Simulation time 75617625 ps
CPU time 3.7 seconds
Started Jul 03 06:17:50 PM PDT 24
Finished Jul 03 06:17:54 PM PDT 24
Peak memory 249512 kb
Host smart-e65e8138-0049-4176-909a-9b8ad8483dc9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1374944043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1374944043
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.160198802
Short name T56
Test name
Test status
Simulation time 183897013282 ps
CPU time 1837.17 seconds
Started Jul 03 06:17:47 PM PDT 24
Finished Jul 03 06:48:25 PM PDT 24
Peak memory 284148 kb
Host smart-7e76f37f-968e-4d4f-b9b8-27d5b5d4a9ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160198802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.160198802
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.566837997
Short name T209
Test name
Test status
Simulation time 297451205 ps
CPU time 9.24 seconds
Started Jul 03 06:17:53 PM PDT 24
Finished Jul 03 06:18:03 PM PDT 24
Peak memory 249168 kb
Host smart-bdfe921b-91a8-488c-be1d-e1b4d1a4019d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=566837997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.566837997
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4083098698
Short name T484
Test name
Test status
Simulation time 612415909 ps
CPU time 13.57 seconds
Started Jul 03 06:17:51 PM PDT 24
Finished Jul 03 06:18:04 PM PDT 24
Peak memory 257512 kb
Host smart-46c9cdf7-ff97-49dc-b27f-c2a77700f00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830
98698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4083098698
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3442490401
Short name T581
Test name
Test status
Simulation time 236025333 ps
CPU time 9.69 seconds
Started Jul 03 06:17:48 PM PDT 24
Finished Jul 03 06:17:58 PM PDT 24
Peak memory 248804 kb
Host smart-1b0121b4-6c56-4c41-9e4d-624b19e72de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
90401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3442490401
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.278281673
Short name T316
Test name
Test status
Simulation time 139931304232 ps
CPU time 1903.87 seconds
Started Jul 03 06:17:54 PM PDT 24
Finished Jul 03 06:49:39 PM PDT 24
Peak memory 274028 kb
Host smart-86753599-f7c8-4f29-89aa-bc0cfe9364e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278281673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.278281673
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3832175039
Short name T591
Test name
Test status
Simulation time 32400642966 ps
CPU time 1801.5 seconds
Started Jul 03 06:17:52 PM PDT 24
Finished Jul 03 06:47:53 PM PDT 24
Peak memory 286804 kb
Host smart-201fa89e-2031-4c1b-ae82-78d0e68fd04c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832175039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3832175039
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2137082084
Short name T552
Test name
Test status
Simulation time 20764454047 ps
CPU time 212.62 seconds
Started Jul 03 06:17:54 PM PDT 24
Finished Jul 03 06:21:27 PM PDT 24
Peak memory 249384 kb
Host smart-c1a12e33-91e8-442b-af06-9e63644ead6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137082084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2137082084
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.91823545
Short name T672
Test name
Test status
Simulation time 571291660 ps
CPU time 27.59 seconds
Started Jul 03 06:17:48 PM PDT 24
Finished Jul 03 06:18:16 PM PDT 24
Peak memory 249264 kb
Host smart-9477c0c0-9f4b-4132-b393-0b4718b059c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91823
545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.91823545
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.817930803
Short name T437
Test name
Test status
Simulation time 3332826570 ps
CPU time 54.2 seconds
Started Jul 03 06:17:50 PM PDT 24
Finished Jul 03 06:18:44 PM PDT 24
Peak memory 248988 kb
Host smart-505bea36-3fc7-45ca-943d-56973351a5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81793
0803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.817930803
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2526945264
Short name T92
Test name
Test status
Simulation time 727253488 ps
CPU time 24.28 seconds
Started Jul 03 06:17:49 PM PDT 24
Finished Jul 03 06:18:13 PM PDT 24
Peak memory 257404 kb
Host smart-c89df61d-0545-4203-81ca-aef9ab4b1302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25269
45264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2526945264
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2173803835
Short name T374
Test name
Test status
Simulation time 2265075018 ps
CPU time 64.45 seconds
Started Jul 03 06:17:49 PM PDT 24
Finished Jul 03 06:18:54 PM PDT 24
Peak memory 257592 kb
Host smart-1de429fe-4d73-4f69-8ae6-97a48fef8f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21738
03835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2173803835
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1172246970
Short name T514
Test name
Test status
Simulation time 71130281060 ps
CPU time 4428.34 seconds
Started Jul 03 06:17:56 PM PDT 24
Finished Jul 03 07:31:45 PM PDT 24
Peak memory 305760 kb
Host smart-d630f540-aa83-4859-9c4c-1eaf69aad5ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172246970 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1172246970
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2040149798
Short name T184
Test name
Test status
Simulation time 68679073 ps
CPU time 3.91 seconds
Started Jul 03 06:18:00 PM PDT 24
Finished Jul 03 06:18:04 PM PDT 24
Peak memory 249552 kb
Host smart-c326f2a1-d9b6-4ab8-a5f4-6f651b73acad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2040149798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2040149798
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2167128889
Short name T351
Test name
Test status
Simulation time 22295248503 ps
CPU time 982.35 seconds
Started Jul 03 06:17:56 PM PDT 24
Finished Jul 03 06:34:18 PM PDT 24
Peak memory 268756 kb
Host smart-67ade90e-27c8-482e-b60a-6d8acceda377
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167128889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2167128889
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.292701935
Short name T627
Test name
Test status
Simulation time 2078818110 ps
CPU time 22.5 seconds
Started Jul 03 06:18:01 PM PDT 24
Finished Jul 03 06:18:24 PM PDT 24
Peak memory 249264 kb
Host smart-fec2d4d3-693d-415f-946d-8d04ed7aa097
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=292701935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.292701935
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1309691300
Short name T424
Test name
Test status
Simulation time 5013914862 ps
CPU time 260.77 seconds
Started Jul 03 06:17:58 PM PDT 24
Finished Jul 03 06:22:19 PM PDT 24
Peak memory 252560 kb
Host smart-28709015-69b7-4476-8b7b-98aa4ce92025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13096
91300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1309691300
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3869773678
Short name T61
Test name
Test status
Simulation time 355156007 ps
CPU time 32.13 seconds
Started Jul 03 06:17:57 PM PDT 24
Finished Jul 03 06:18:29 PM PDT 24
Peak memory 249324 kb
Host smart-4b0f80cf-d514-4b15-85fb-9f3c464f2b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
73678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3869773678
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.442246118
Short name T391
Test name
Test status
Simulation time 91910151419 ps
CPU time 1531.59 seconds
Started Jul 03 06:17:57 PM PDT 24
Finished Jul 03 06:43:29 PM PDT 24
Peak memory 268864 kb
Host smart-536a532f-e7e2-4b7b-a78c-2a4cd03ad685
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442246118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.442246118
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.353363286
Short name T553
Test name
Test status
Simulation time 32391179795 ps
CPU time 347.94 seconds
Started Jul 03 06:17:57 PM PDT 24
Finished Jul 03 06:23:46 PM PDT 24
Peak memory 249204 kb
Host smart-29bb7e78-4bb7-472e-a017-68a8628f1201
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353363286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.353363286
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.569336031
Short name T537
Test name
Test status
Simulation time 100521454 ps
CPU time 5.47 seconds
Started Jul 03 06:17:57 PM PDT 24
Finished Jul 03 06:18:03 PM PDT 24
Peak memory 249168 kb
Host smart-afb81e2e-f39b-4a46-9e29-4762cfc98edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56933
6031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.569336031
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3036518024
Short name T541
Test name
Test status
Simulation time 1220492933 ps
CPU time 11.51 seconds
Started Jul 03 06:17:57 PM PDT 24
Finished Jul 03 06:18:09 PM PDT 24
Peak memory 249248 kb
Host smart-e04134ca-be37-4804-be7e-3fb0beae9fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30365
18024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3036518024
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1816797862
Short name T237
Test name
Test status
Simulation time 830603509 ps
CPU time 29.61 seconds
Started Jul 03 06:17:55 PM PDT 24
Finished Jul 03 06:18:25 PM PDT 24
Peak memory 249272 kb
Host smart-b38874f2-edb4-4f4d-999c-0f9ee74259be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167
97862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1816797862
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1896040780
Short name T594
Test name
Test status
Simulation time 2220973742 ps
CPU time 9.55 seconds
Started Jul 03 06:17:55 PM PDT 24
Finished Jul 03 06:18:05 PM PDT 24
Peak memory 253996 kb
Host smart-627144bd-85b1-4c79-a48e-2ee10c3b710d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18960
40780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1896040780
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2170632697
Short name T99
Test name
Test status
Simulation time 16385346231 ps
CPU time 1584.85 seconds
Started Jul 03 06:18:00 PM PDT 24
Finished Jul 03 06:44:25 PM PDT 24
Peak memory 290240 kb
Host smart-3a75241a-c98e-4651-9e70-5176e38877fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170632697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2170632697
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3662687281
Short name T91
Test name
Test status
Simulation time 17400289596 ps
CPU time 1799.19 seconds
Started Jul 03 06:17:59 PM PDT 24
Finished Jul 03 06:47:59 PM PDT 24
Peak memory 290208 kb
Host smart-6f181396-a1aa-472c-914e-be9873c1095e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662687281 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3662687281
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2570324886
Short name T168
Test name
Test status
Simulation time 32116744 ps
CPU time 3.43 seconds
Started Jul 03 06:15:27 PM PDT 24
Finished Jul 03 06:15:31 PM PDT 24
Peak memory 249576 kb
Host smart-58ffc3ba-602a-4885-bee1-c0b4453bb96e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2570324886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2570324886
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.60993129
Short name T407
Test name
Test status
Simulation time 92149057091 ps
CPU time 2285.82 seconds
Started Jul 03 06:15:19 PM PDT 24
Finished Jul 03 06:53:25 PM PDT 24
Peak memory 282124 kb
Host smart-8bf6158a-dc0b-47d7-8d8b-636be392b884
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60993129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.60993129
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.548382152
Short name T614
Test name
Test status
Simulation time 527496022 ps
CPU time 23.47 seconds
Started Jul 03 06:15:28 PM PDT 24
Finished Jul 03 06:15:52 PM PDT 24
Peak memory 249264 kb
Host smart-7462b791-d34d-4c92-a857-7eed19950aa1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=548382152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.548382152
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.4245335706
Short name T653
Test name
Test status
Simulation time 17678911463 ps
CPU time 255.43 seconds
Started Jul 03 06:15:18 PM PDT 24
Finished Jul 03 06:19:34 PM PDT 24
Peak memory 252484 kb
Host smart-f7a78a38-19a8-481b-9926-9f67c9f413fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
35706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.4245335706
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3264106334
Short name T523
Test name
Test status
Simulation time 38655982946 ps
CPU time 1187.55 seconds
Started Jul 03 06:15:26 PM PDT 24
Finished Jul 03 06:35:14 PM PDT 24
Peak memory 283660 kb
Host smart-7425c992-11d8-4033-8657-c0e3d948e7f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264106334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3264106334
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4160661058
Short name T575
Test name
Test status
Simulation time 8607038012 ps
CPU time 907.54 seconds
Started Jul 03 06:15:27 PM PDT 24
Finished Jul 03 06:30:35 PM PDT 24
Peak memory 273956 kb
Host smart-a5818b57-db11-4feb-8757-f5da27f76159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160661058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4160661058
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1127081449
Short name T271
Test name
Test status
Simulation time 77912572879 ps
CPU time 647.22 seconds
Started Jul 03 06:15:21 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 257056 kb
Host smart-a739c0a6-f36a-4899-848f-66f4f30248f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127081449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1127081449
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3821294452
Short name T370
Test name
Test status
Simulation time 663216617 ps
CPU time 41.32 seconds
Started Jul 03 06:15:15 PM PDT 24
Finished Jul 03 06:15:57 PM PDT 24
Peak memory 249276 kb
Host smart-5dd7deaa-2f9f-4579-ba0b-cef8174f44aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38212
94452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3821294452
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.719639529
Short name T75
Test name
Test status
Simulation time 149092871 ps
CPU time 16.85 seconds
Started Jul 03 06:15:19 PM PDT 24
Finished Jul 03 06:15:36 PM PDT 24
Peak memory 248716 kb
Host smart-8891a3bd-8316-46a5-b365-d42ac2b4101f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71963
9529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.719639529
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3451517849
Short name T32
Test name
Test status
Simulation time 2060863321 ps
CPU time 20.57 seconds
Started Jul 03 06:15:29 PM PDT 24
Finished Jul 03 06:15:49 PM PDT 24
Peak memory 270684 kb
Host smart-90d54aa1-008d-4f58-8799-5c8e082c90f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3451517849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3451517849
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.437236486
Short name T330
Test name
Test status
Simulation time 238140488 ps
CPU time 9.2 seconds
Started Jul 03 06:15:17 PM PDT 24
Finished Jul 03 06:15:27 PM PDT 24
Peak memory 252216 kb
Host smart-85817fd6-695b-43bf-a973-91a0ecc3fc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43723
6486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.437236486
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3616392021
Short name T670
Test name
Test status
Simulation time 91432281 ps
CPU time 6.23 seconds
Started Jul 03 06:15:17 PM PDT 24
Finished Jul 03 06:15:23 PM PDT 24
Peak memory 249180 kb
Host smart-bdfa1d7a-2a64-42fc-b90e-b229a093b7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36163
92021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3616392021
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2654506510
Short name T410
Test name
Test status
Simulation time 515757986 ps
CPU time 32.36 seconds
Started Jul 03 06:15:27 PM PDT 24
Finished Jul 03 06:16:00 PM PDT 24
Peak memory 257072 kb
Host smart-6bca97d7-699e-4081-a746-bf4f939e9576
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654506510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2654506510
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2295401681
Short name T459
Test name
Test status
Simulation time 103303491328 ps
CPU time 1543.89 seconds
Started Jul 03 06:18:06 PM PDT 24
Finished Jul 03 06:43:50 PM PDT 24
Peak memory 273788 kb
Host smart-8c220fa2-3f10-4a83-8b4c-0ac094a2eb63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295401681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2295401681
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1863204255
Short name T406
Test name
Test status
Simulation time 4176775348 ps
CPU time 270.3 seconds
Started Jul 03 06:18:03 PM PDT 24
Finished Jul 03 06:22:33 PM PDT 24
Peak memory 252392 kb
Host smart-ec8b225e-ba60-4fe7-896a-8105274c1b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18632
04255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1863204255
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1529618948
Short name T353
Test name
Test status
Simulation time 141674397 ps
CPU time 9.75 seconds
Started Jul 03 06:18:04 PM PDT 24
Finished Jul 03 06:18:14 PM PDT 24
Peak memory 252152 kb
Host smart-a0464d72-d958-4d60-b967-233181ca3c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
18948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1529618948
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.427902288
Short name T304
Test name
Test status
Simulation time 14529773630 ps
CPU time 1420.56 seconds
Started Jul 03 06:18:07 PM PDT 24
Finished Jul 03 06:41:48 PM PDT 24
Peak memory 290336 kb
Host smart-557f6fc4-27fe-4b68-9626-14defa7771d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427902288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.427902288
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1649148683
Short name T539
Test name
Test status
Simulation time 14310378266 ps
CPU time 901.32 seconds
Started Jul 03 06:18:04 PM PDT 24
Finished Jul 03 06:33:06 PM PDT 24
Peak memory 273944 kb
Host smart-157ff3db-e73b-40b5-a670-65c2b07b97c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649148683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1649148683
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3079454019
Short name T260
Test name
Test status
Simulation time 54368804388 ps
CPU time 482.02 seconds
Started Jul 03 06:18:07 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 249412 kb
Host smart-0e14bc94-6fef-4474-b1d9-566ef055ffa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079454019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3079454019
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1433284081
Short name T598
Test name
Test status
Simulation time 1039431476 ps
CPU time 7.25 seconds
Started Jul 03 06:17:57 PM PDT 24
Finished Jul 03 06:18:05 PM PDT 24
Peak memory 254800 kb
Host smart-7842df64-f52b-4e61-81a4-bf227c9c9a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14332
84081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1433284081
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.194267064
Short name T37
Test name
Test status
Simulation time 1040526991 ps
CPU time 14.14 seconds
Started Jul 03 06:18:00 PM PDT 24
Finished Jul 03 06:18:15 PM PDT 24
Peak memory 248308 kb
Host smart-1961c87b-ef2d-468d-895b-bed73dc8ff2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19426
7064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.194267064
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1978344430
Short name T617
Test name
Test status
Simulation time 359849121 ps
CPU time 42.22 seconds
Started Jul 03 06:18:05 PM PDT 24
Finished Jul 03 06:18:47 PM PDT 24
Peak memory 256480 kb
Host smart-36f3ccbf-00c4-498a-8ac8-e36b74a37654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19783
44430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1978344430
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1454166138
Short name T34
Test name
Test status
Simulation time 427321422 ps
CPU time 7.73 seconds
Started Jul 03 06:17:59 PM PDT 24
Finished Jul 03 06:18:07 PM PDT 24
Peak memory 251256 kb
Host smart-3b359cdb-24f2-4030-9bbc-c0ea7fea3174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14541
66138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1454166138
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.587551669
Short name T88
Test name
Test status
Simulation time 40633756112 ps
CPU time 1006.8 seconds
Started Jul 03 06:18:13 PM PDT 24
Finished Jul 03 06:35:01 PM PDT 24
Peak memory 284404 kb
Host smart-6128127f-ee1a-4cef-962e-5ab299f52145
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587551669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.587551669
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2292966506
Short name T577
Test name
Test status
Simulation time 10558139813 ps
CPU time 163.95 seconds
Started Jul 03 06:18:14 PM PDT 24
Finished Jul 03 06:20:58 PM PDT 24
Peak memory 257124 kb
Host smart-57bf420f-5a70-4faa-8d7c-644de841272a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
66506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2292966506
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2323401665
Short name T508
Test name
Test status
Simulation time 148222298 ps
CPU time 9.41 seconds
Started Jul 03 06:18:14 PM PDT 24
Finished Jul 03 06:18:24 PM PDT 24
Peak memory 252840 kb
Host smart-21499750-e01f-4ace-9b13-68b5d0096d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234
01665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2323401665
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1546165816
Short name T305
Test name
Test status
Simulation time 39080241329 ps
CPU time 1185.6 seconds
Started Jul 03 06:18:12 PM PDT 24
Finished Jul 03 06:37:58 PM PDT 24
Peak memory 273044 kb
Host smart-a7dfc9e2-c3bf-42b5-a5ae-95e989a5717f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546165816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1546165816
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.61191877
Short name T499
Test name
Test status
Simulation time 37715675964 ps
CPU time 1630.81 seconds
Started Jul 03 06:18:13 PM PDT 24
Finished Jul 03 06:45:25 PM PDT 24
Peak memory 290064 kb
Host smart-8f820a3b-7862-4b25-9c6e-c0ebaffcc797
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61191877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.61191877
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.578006550
Short name T259
Test name
Test status
Simulation time 4110429699 ps
CPU time 89.31 seconds
Started Jul 03 06:18:13 PM PDT 24
Finished Jul 03 06:19:43 PM PDT 24
Peak memory 249240 kb
Host smart-8c958a37-d152-4df7-be51-6d83645ef1f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578006550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.578006550
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1420713127
Short name T71
Test name
Test status
Simulation time 225997224 ps
CPU time 24.38 seconds
Started Jul 03 06:18:11 PM PDT 24
Finished Jul 03 06:18:35 PM PDT 24
Peak memory 248820 kb
Host smart-bb4d9fae-c181-4d08-8967-286a6ef15126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14207
13127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1420713127
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3371714422
Short name T495
Test name
Test status
Simulation time 1323046868 ps
CPU time 24.7 seconds
Started Jul 03 06:18:13 PM PDT 24
Finished Jul 03 06:18:38 PM PDT 24
Peak memory 256744 kb
Host smart-2adaa03a-857f-450a-aeb4-dea4d4a3955a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33717
14422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3371714422
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2810401471
Short name T561
Test name
Test status
Simulation time 255698201 ps
CPU time 5.96 seconds
Started Jul 03 06:18:10 PM PDT 24
Finished Jul 03 06:18:16 PM PDT 24
Peak memory 251508 kb
Host smart-d57a8e1d-c869-4b1f-b0dc-f8078bb59708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28104
01471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2810401471
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2980307771
Short name T252
Test name
Test status
Simulation time 44711255135 ps
CPU time 2605.82 seconds
Started Jul 03 06:18:15 PM PDT 24
Finished Jul 03 07:01:41 PM PDT 24
Peak memory 290048 kb
Host smart-b67dacf2-8d48-42c4-8663-267d13150c6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980307771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2980307771
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.257365318
Short name T289
Test name
Test status
Simulation time 3078033089 ps
CPU time 283.96 seconds
Started Jul 03 06:18:17 PM PDT 24
Finished Jul 03 06:23:01 PM PDT 24
Peak memory 269260 kb
Host smart-02edfcfd-77d8-4e32-9bce-ea0f0ba07376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257365318 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.257365318
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.845808210
Short name T618
Test name
Test status
Simulation time 20191732468 ps
CPU time 700.01 seconds
Started Jul 03 06:18:23 PM PDT 24
Finished Jul 03 06:30:04 PM PDT 24
Peak memory 273952 kb
Host smart-4b6de8d0-5088-488c-a8dc-edd23cd90e7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845808210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.845808210
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2920488991
Short name T408
Test name
Test status
Simulation time 942257540 ps
CPU time 77.53 seconds
Started Jul 03 06:18:17 PM PDT 24
Finished Jul 03 06:19:35 PM PDT 24
Peak memory 257044 kb
Host smart-b573945e-e1dd-4160-83c5-0047f5f6c526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29204
88991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2920488991
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.50427556
Short name T393
Test name
Test status
Simulation time 154780556 ps
CPU time 3.57 seconds
Started Jul 03 06:18:19 PM PDT 24
Finished Jul 03 06:18:23 PM PDT 24
Peak memory 241092 kb
Host smart-37d2c218-71a1-4a34-bd61-2060e20c5a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50427
556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.50427556
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3972517015
Short name T247
Test name
Test status
Simulation time 17751825432 ps
CPU time 1198.91 seconds
Started Jul 03 06:18:28 PM PDT 24
Finished Jul 03 06:38:27 PM PDT 24
Peak memory 273884 kb
Host smart-da5b6f48-084c-4d86-b52d-aa08980c0f32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972517015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3972517015
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.179441386
Short name T500
Test name
Test status
Simulation time 116111494933 ps
CPU time 1940.59 seconds
Started Jul 03 06:18:28 PM PDT 24
Finished Jul 03 06:50:49 PM PDT 24
Peak memory 283252 kb
Host smart-3347edc7-60dc-4769-8dfe-fa3ff82d1142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179441386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.179441386
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1917914746
Short name T646
Test name
Test status
Simulation time 274913699 ps
CPU time 17.69 seconds
Started Jul 03 06:18:22 PM PDT 24
Finished Jul 03 06:18:40 PM PDT 24
Peak memory 249268 kb
Host smart-92743074-29c8-46a5-b135-a33b9318d85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19179
14746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1917914746
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.534211079
Short name T46
Test name
Test status
Simulation time 970205712 ps
CPU time 63.54 seconds
Started Jul 03 06:18:20 PM PDT 24
Finished Jul 03 06:19:24 PM PDT 24
Peak memory 256960 kb
Host smart-f35e0e2e-db79-48d8-9219-28f3a84c3f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53421
1079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.534211079
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.281739299
Short name T250
Test name
Test status
Simulation time 1466503669 ps
CPU time 45.15 seconds
Started Jul 03 06:18:24 PM PDT 24
Finished Jul 03 06:19:10 PM PDT 24
Peak memory 249268 kb
Host smart-1eca9a4f-6493-4162-93a8-a8417e489747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28173
9299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.281739299
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.787841758
Short name T526
Test name
Test status
Simulation time 104453208 ps
CPU time 9.97 seconds
Started Jul 03 06:18:16 PM PDT 24
Finished Jul 03 06:18:26 PM PDT 24
Peak memory 256012 kb
Host smart-52b4c4db-bce3-4689-b8bc-df29ae19e632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78784
1758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.787841758
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2707492878
Short name T228
Test name
Test status
Simulation time 4795146735 ps
CPU time 285.04 seconds
Started Jul 03 06:18:27 PM PDT 24
Finished Jul 03 06:23:12 PM PDT 24
Peak memory 257500 kb
Host smart-a9707c29-10ab-4a39-bba9-88f200131d32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707492878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2707492878
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4197632977
Short name T210
Test name
Test status
Simulation time 18547898218 ps
CPU time 1221.97 seconds
Started Jul 03 06:18:29 PM PDT 24
Finished Jul 03 06:38:51 PM PDT 24
Peak memory 271512 kb
Host smart-7650c177-3c5a-444f-a0db-57d9c43040ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197632977 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4197632977
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3677718130
Short name T545
Test name
Test status
Simulation time 35853994802 ps
CPU time 2154.65 seconds
Started Jul 03 06:18:28 PM PDT 24
Finished Jul 03 06:54:23 PM PDT 24
Peak memory 289364 kb
Host smart-7f480f7e-6f07-44b8-b40f-b62bbdea2a45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677718130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3677718130
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1747235634
Short name T352
Test name
Test status
Simulation time 7029857932 ps
CPU time 161.11 seconds
Started Jul 03 06:18:30 PM PDT 24
Finished Jul 03 06:21:11 PM PDT 24
Peak memory 252656 kb
Host smart-0a14e559-4dff-43e1-b7d2-2abe3cfc5695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
35634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1747235634
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2980950815
Short name T234
Test name
Test status
Simulation time 1438112482 ps
CPU time 20.3 seconds
Started Jul 03 06:18:32 PM PDT 24
Finished Jul 03 06:18:53 PM PDT 24
Peak memory 248784 kb
Host smart-2958574b-4551-477a-91a5-c3f26f217349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809
50815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2980950815
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4212173685
Short name T679
Test name
Test status
Simulation time 32647996720 ps
CPU time 1729.5 seconds
Started Jul 03 06:18:34 PM PDT 24
Finished Jul 03 06:47:24 PM PDT 24
Peak memory 286136 kb
Host smart-639807d9-25a8-4246-8fce-f3b041e228bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212173685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4212173685
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.342374001
Short name T255
Test name
Test status
Simulation time 49412605305 ps
CPU time 482.59 seconds
Started Jul 03 06:18:35 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 248236 kb
Host smart-e034eb1c-ba96-4dca-a354-dc8ea91694ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342374001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.342374001
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2759949020
Short name T436
Test name
Test status
Simulation time 11464618901 ps
CPU time 47.09 seconds
Started Jul 03 06:18:27 PM PDT 24
Finished Jul 03 06:19:14 PM PDT 24
Peak memory 256740 kb
Host smart-1c87abc4-dfe3-409f-9b68-93b538efafb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599
49020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2759949020
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2415038970
Short name T602
Test name
Test status
Simulation time 4975797982 ps
CPU time 47.01 seconds
Started Jul 03 06:18:27 PM PDT 24
Finished Jul 03 06:19:14 PM PDT 24
Peak memory 257484 kb
Host smart-5659f90d-394e-439e-a022-6e803e1f5101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24150
38970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2415038970
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4098935580
Short name T53
Test name
Test status
Simulation time 236580574 ps
CPU time 29.73 seconds
Started Jul 03 06:18:28 PM PDT 24
Finished Jul 03 06:18:58 PM PDT 24
Peak memory 249268 kb
Host smart-07934efa-6ece-4583-816c-986b1702dc0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40989
35580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4098935580
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2851051778
Short name T639
Test name
Test status
Simulation time 1257007581 ps
CPU time 7.82 seconds
Started Jul 03 06:18:30 PM PDT 24
Finished Jul 03 06:18:38 PM PDT 24
Peak memory 252256 kb
Host smart-7ef239a7-b2cc-4318-bd85-d5b509632dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
51778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2851051778
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4251201987
Short name T203
Test name
Test status
Simulation time 17624933920 ps
CPU time 1749.86 seconds
Started Jul 03 06:18:36 PM PDT 24
Finished Jul 03 06:47:47 PM PDT 24
Peak memory 290368 kb
Host smart-b57e9c96-08fb-4686-ba92-e9e0a3434e1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251201987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4251201987
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1817238123
Short name T69
Test name
Test status
Simulation time 14525602538 ps
CPU time 602.13 seconds
Started Jul 03 06:18:35 PM PDT 24
Finished Jul 03 06:28:38 PM PDT 24
Peak memory 265644 kb
Host smart-518c3405-449f-4439-bd96-6ff29fd6d3c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817238123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1817238123
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2338445360
Short name T554
Test name
Test status
Simulation time 4135894179 ps
CPU time 96.2 seconds
Started Jul 03 06:18:38 PM PDT 24
Finished Jul 03 06:20:15 PM PDT 24
Peak memory 257092 kb
Host smart-8f9810a7-17f6-477d-a1e5-064193fa8ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
45360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2338445360
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.438829972
Short name T411
Test name
Test status
Simulation time 326055963 ps
CPU time 31.11 seconds
Started Jul 03 06:18:38 PM PDT 24
Finished Jul 03 06:19:09 PM PDT 24
Peak memory 256860 kb
Host smart-1af4878f-3059-4f15-834c-355c7b8e18db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43882
9972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.438829972
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3965361727
Short name T72
Test name
Test status
Simulation time 75912922855 ps
CPU time 1260.33 seconds
Started Jul 03 06:18:41 PM PDT 24
Finished Jul 03 06:39:42 PM PDT 24
Peak memory 273304 kb
Host smart-e3f46197-b1c1-4071-a70b-4d6b9049f027
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965361727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3965361727
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3128344053
Short name T461
Test name
Test status
Simulation time 52696307953 ps
CPU time 1326.21 seconds
Started Jul 03 06:18:40 PM PDT 24
Finished Jul 03 06:40:47 PM PDT 24
Peak memory 267780 kb
Host smart-d3ea7320-d9b6-4b88-b4e0-4a2d788a574d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128344053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3128344053
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3357918742
Short name T637
Test name
Test status
Simulation time 81050999 ps
CPU time 6.66 seconds
Started Jul 03 06:18:37 PM PDT 24
Finished Jul 03 06:18:44 PM PDT 24
Peak memory 249244 kb
Host smart-d3af2450-717a-4661-80d0-2d53e6560897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33579
18742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3357918742
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3746730626
Short name T349
Test name
Test status
Simulation time 280922781 ps
CPU time 22.72 seconds
Started Jul 03 06:18:36 PM PDT 24
Finished Jul 03 06:18:59 PM PDT 24
Peak memory 256688 kb
Host smart-cb6d719d-58b5-4f6e-b626-1a3aace58ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37467
30626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3746730626
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.364289225
Short name T547
Test name
Test status
Simulation time 1618992110 ps
CPU time 67.7 seconds
Started Jul 03 06:18:37 PM PDT 24
Finished Jul 03 06:19:45 PM PDT 24
Peak memory 257400 kb
Host smart-ffbdc16e-d152-4f29-8136-e1e4a10a1b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
9225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.364289225
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3302576306
Short name T58
Test name
Test status
Simulation time 1031455506 ps
CPU time 23.28 seconds
Started Jul 03 06:18:35 PM PDT 24
Finished Jul 03 06:18:59 PM PDT 24
Peak memory 257420 kb
Host smart-7e9c505b-1f71-4a84-b49a-6deec8ca6619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33025
76306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3302576306
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2161282986
Short name T557
Test name
Test status
Simulation time 50485021461 ps
CPU time 1076.88 seconds
Started Jul 03 06:18:40 PM PDT 24
Finished Jul 03 06:36:37 PM PDT 24
Peak memory 290164 kb
Host smart-497d51ff-869a-4646-b0a4-e0a827cc0587
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161282986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2161282986
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1035919658
Short name T687
Test name
Test status
Simulation time 200945048944 ps
CPU time 2493.52 seconds
Started Jul 03 06:18:46 PM PDT 24
Finished Jul 03 07:00:20 PM PDT 24
Peak memory 288256 kb
Host smart-ec1b95c3-b55e-48f6-bda3-e25559a9110f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035919658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1035919658
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3047293920
Short name T346
Test name
Test status
Simulation time 8380128367 ps
CPU time 105.9 seconds
Started Jul 03 06:18:44 PM PDT 24
Finished Jul 03 06:20:30 PM PDT 24
Peak memory 257644 kb
Host smart-8335bd13-8e25-469a-bfac-f8e4d4ef962c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30472
93920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3047293920
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2663296552
Short name T582
Test name
Test status
Simulation time 2936841973 ps
CPU time 57.11 seconds
Started Jul 03 06:18:44 PM PDT 24
Finished Jul 03 06:19:41 PM PDT 24
Peak memory 257576 kb
Host smart-fa1c409f-ff03-4056-ab07-505a256cfc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26632
96552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2663296552
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1174101271
Short name T318
Test name
Test status
Simulation time 34400969432 ps
CPU time 642.9 seconds
Started Jul 03 06:18:48 PM PDT 24
Finished Jul 03 06:29:31 PM PDT 24
Peak memory 273444 kb
Host smart-b0d6bc5c-977c-463b-9bf8-8885b8968886
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174101271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1174101271
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2174539953
Short name T295
Test name
Test status
Simulation time 13416990177 ps
CPU time 729.99 seconds
Started Jul 03 06:18:47 PM PDT 24
Finished Jul 03 06:30:57 PM PDT 24
Peak memory 273840 kb
Host smart-dcec3597-57d1-44e0-b425-20caf36cd22b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174539953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2174539953
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1382452910
Short name T212
Test name
Test status
Simulation time 11344657739 ps
CPU time 502.92 seconds
Started Jul 03 06:18:46 PM PDT 24
Finished Jul 03 06:27:09 PM PDT 24
Peak memory 249364 kb
Host smart-9c2dc784-f7bd-4041-b364-4c27d743e2f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382452910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1382452910
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3833716782
Short name T689
Test name
Test status
Simulation time 2311052950 ps
CPU time 38.51 seconds
Started Jul 03 06:18:43 PM PDT 24
Finished Jul 03 06:19:22 PM PDT 24
Peak memory 256860 kb
Host smart-bbe3dd91-49e2-441a-b831-93bfa72a2f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38337
16782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3833716782
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3729063532
Short name T460
Test name
Test status
Simulation time 652610665 ps
CPU time 34.94 seconds
Started Jul 03 06:18:44 PM PDT 24
Finished Jul 03 06:19:19 PM PDT 24
Peak memory 256920 kb
Host smart-4885c4c8-6c43-42cf-b63c-30e1992f23af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37290
63532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3729063532
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2965573684
Short name T447
Test name
Test status
Simulation time 239469851 ps
CPU time 16.14 seconds
Started Jul 03 06:18:43 PM PDT 24
Finished Jul 03 06:19:00 PM PDT 24
Peak memory 256544 kb
Host smart-ce96e3dc-3906-4f4a-b2e6-0e7d7115eeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29655
73684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2965573684
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.879636758
Short name T440
Test name
Test status
Simulation time 501663243 ps
CPU time 26.47 seconds
Started Jul 03 06:18:38 PM PDT 24
Finished Jul 03 06:19:05 PM PDT 24
Peak memory 257456 kb
Host smart-99c1ba74-cca8-4120-824d-d44db7991074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87963
6758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.879636758
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1144255966
Short name T363
Test name
Test status
Simulation time 506857745 ps
CPU time 49.63 seconds
Started Jul 03 06:18:47 PM PDT 24
Finished Jul 03 06:19:36 PM PDT 24
Peak memory 257476 kb
Host smart-20721316-98cf-4c66-98cb-8a1534808346
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144255966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1144255966
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4247636441
Short name T558
Test name
Test status
Simulation time 184155419053 ps
CPU time 2983.11 seconds
Started Jul 03 06:18:51 PM PDT 24
Finished Jul 03 07:08:35 PM PDT 24
Peak memory 285696 kb
Host smart-fa49d6f3-20d8-45ae-b044-2fc289535416
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247636441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4247636441
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2265342447
Short name T576
Test name
Test status
Simulation time 8473349183 ps
CPU time 167.8 seconds
Started Jul 03 06:18:52 PM PDT 24
Finished Jul 03 06:21:40 PM PDT 24
Peak memory 256780 kb
Host smart-f3036ae3-d77c-4ee7-b475-2a2d6c1644bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22653
42447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2265342447
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1745165177
Short name T519
Test name
Test status
Simulation time 321024741 ps
CPU time 26.76 seconds
Started Jul 03 06:18:52 PM PDT 24
Finished Jul 03 06:19:19 PM PDT 24
Peak memory 257444 kb
Host smart-4e83f043-ac6b-428a-8bc8-cbaf803dbe42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17451
65177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1745165177
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.647043527
Short name T584
Test name
Test status
Simulation time 43461726611 ps
CPU time 1326.7 seconds
Started Jul 03 06:18:56 PM PDT 24
Finished Jul 03 06:41:03 PM PDT 24
Peak memory 273744 kb
Host smart-b705b2d8-ccff-46cb-91a3-4d0e7c8754fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647043527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.647043527
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3951283268
Short name T481
Test name
Test status
Simulation time 13582281293 ps
CPU time 1019.7 seconds
Started Jul 03 06:18:55 PM PDT 24
Finished Jul 03 06:35:55 PM PDT 24
Peak memory 283960 kb
Host smart-93e75110-fba2-4a23-93d6-4400a9084398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951283268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3951283268
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3367054804
Short name T690
Test name
Test status
Simulation time 16828305356 ps
CPU time 216.87 seconds
Started Jul 03 06:18:51 PM PDT 24
Finished Jul 03 06:22:28 PM PDT 24
Peak memory 249428 kb
Host smart-2541e162-aca2-4b2d-b46f-286e044ccac7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367054804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3367054804
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3981836121
Short name T341
Test name
Test status
Simulation time 302492112 ps
CPU time 26.41 seconds
Started Jul 03 06:18:50 PM PDT 24
Finished Jul 03 06:19:17 PM PDT 24
Peak memory 256700 kb
Host smart-0f22a0e7-1adf-406c-8bbd-a072902538e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
36121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3981836121
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3728596886
Short name T635
Test name
Test status
Simulation time 1101189334 ps
CPU time 34.3 seconds
Started Jul 03 06:18:51 PM PDT 24
Finished Jul 03 06:19:26 PM PDT 24
Peak memory 248640 kb
Host smart-3bcf3ba3-ae3c-48f3-9d8c-b6ff350f10df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37285
96886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3728596886
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.149141643
Short name T229
Test name
Test status
Simulation time 386328938 ps
CPU time 23.52 seconds
Started Jul 03 06:18:50 PM PDT 24
Finished Jul 03 06:19:14 PM PDT 24
Peak memory 249760 kb
Host smart-807f6117-0335-4155-a787-246da8e5a9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
1643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.149141643
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4230810411
Short name T381
Test name
Test status
Simulation time 760562241 ps
CPU time 14.25 seconds
Started Jul 03 06:18:47 PM PDT 24
Finished Jul 03 06:19:02 PM PDT 24
Peak memory 255744 kb
Host smart-1dbe0cd7-c44b-461f-a626-a1af5bed8ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42308
10411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4230810411
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2973124377
Short name T207
Test name
Test status
Simulation time 12070627222 ps
CPU time 1077.95 seconds
Started Jul 03 06:18:59 PM PDT 24
Finished Jul 03 06:36:57 PM PDT 24
Peak memory 288368 kb
Host smart-3437fbf5-637e-411d-be5b-b8776888c6a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973124377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2973124377
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1808455416
Short name T571
Test name
Test status
Simulation time 56024472689 ps
CPU time 6914.1 seconds
Started Jul 03 06:18:58 PM PDT 24
Finished Jul 03 08:14:13 PM PDT 24
Peak memory 354668 kb
Host smart-0550a02d-0e45-470b-bff3-225b1f96bb2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808455416 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1808455416
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.4083622114
Short name T658
Test name
Test status
Simulation time 10181861716 ps
CPU time 1085.84 seconds
Started Jul 03 06:19:02 PM PDT 24
Finished Jul 03 06:37:08 PM PDT 24
Peak memory 287076 kb
Host smart-119c285c-a8d6-41ed-b8d1-d58bc1b727b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083622114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.4083622114
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.493383753
Short name T22
Test name
Test status
Simulation time 2385898671 ps
CPU time 49.28 seconds
Started Jul 03 06:19:00 PM PDT 24
Finished Jul 03 06:19:49 PM PDT 24
Peak memory 257024 kb
Host smart-1882d5a1-ca98-47c0-b060-8a03b89a8b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49338
3753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.493383753
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.4023477393
Short name T336
Test name
Test status
Simulation time 903294630 ps
CPU time 38.82 seconds
Started Jul 03 06:18:58 PM PDT 24
Finished Jul 03 06:19:37 PM PDT 24
Peak memory 249204 kb
Host smart-eca858f8-c0be-4758-a0be-458827a31522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40234
77393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.4023477393
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4184731156
Short name T246
Test name
Test status
Simulation time 102574480474 ps
CPU time 1554.26 seconds
Started Jul 03 06:19:05 PM PDT 24
Finished Jul 03 06:45:00 PM PDT 24
Peak memory 282188 kb
Host smart-87ca2add-05ac-4085-a962-feca68987471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184731156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4184731156
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.877487402
Short name T373
Test name
Test status
Simulation time 54230329295 ps
CPU time 3315.01 seconds
Started Jul 03 06:19:09 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 289596 kb
Host smart-0b416789-e4a7-4f8a-8f31-a3ae0f90411c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877487402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.877487402
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2031793488
Short name T258
Test name
Test status
Simulation time 6355828709 ps
CPU time 257.36 seconds
Started Jul 03 06:19:06 PM PDT 24
Finished Jul 03 06:23:24 PM PDT 24
Peak memory 256804 kb
Host smart-1d417aa2-f8aa-4ce3-8241-9259758d67cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031793488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2031793488
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3323098550
Short name T543
Test name
Test status
Simulation time 117334861 ps
CPU time 8.57 seconds
Started Jul 03 06:19:00 PM PDT 24
Finished Jul 03 06:19:09 PM PDT 24
Peak memory 249280 kb
Host smart-4054803c-e2c2-4505-8d84-78a94d19f34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33230
98550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3323098550
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2003169183
Short name T608
Test name
Test status
Simulation time 2540809811 ps
CPU time 39.47 seconds
Started Jul 03 06:18:59 PM PDT 24
Finished Jul 03 06:19:39 PM PDT 24
Peak memory 249400 kb
Host smart-84841a59-ac6f-4b62-8f3d-a43f70f28bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
69183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2003169183
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.477757774
Short name T555
Test name
Test status
Simulation time 161231430 ps
CPU time 16.55 seconds
Started Jul 03 06:19:03 PM PDT 24
Finished Jul 03 06:19:20 PM PDT 24
Peak memory 256728 kb
Host smart-344aaa15-7c7b-4ae7-899b-126bd2108d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47775
7774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.477757774
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.219170840
Short name T699
Test name
Test status
Simulation time 860105399 ps
CPU time 45.62 seconds
Started Jul 03 06:18:59 PM PDT 24
Finished Jul 03 06:19:45 PM PDT 24
Peak memory 256964 kb
Host smart-fcc434f2-0382-49e2-9f76-fd9e017bcfe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21917
0840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.219170840
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.302803912
Short name T47
Test name
Test status
Simulation time 70726615009 ps
CPU time 2353.62 seconds
Started Jul 03 06:19:11 PM PDT 24
Finished Jul 03 06:58:25 PM PDT 24
Peak memory 290408 kb
Host smart-fcb24d5b-b1dd-4bc9-b64d-3c0a37d30323
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302803912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.302803912
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1373633600
Short name T597
Test name
Test status
Simulation time 8812031610 ps
CPU time 153.4 seconds
Started Jul 03 06:19:13 PM PDT 24
Finished Jul 03 06:21:46 PM PDT 24
Peak memory 257548 kb
Host smart-e8847e80-11dd-4a3f-8b42-2205505a172c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13736
33600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1373633600
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.131970413
Short name T348
Test name
Test status
Simulation time 1666972578 ps
CPU time 36.02 seconds
Started Jul 03 06:19:14 PM PDT 24
Finished Jul 03 06:19:50 PM PDT 24
Peak memory 249208 kb
Host smart-20b0d312-13af-41a9-be15-8dbf9fe1b781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13197
0413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.131970413
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1416028073
Short name T298
Test name
Test status
Simulation time 32694590376 ps
CPU time 1848.35 seconds
Started Jul 03 06:19:15 PM PDT 24
Finished Jul 03 06:50:03 PM PDT 24
Peak memory 273836 kb
Host smart-e04efa9f-4366-4dea-9f99-95b6f8275c97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416028073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1416028073
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.4038686306
Short name T503
Test name
Test status
Simulation time 75821680068 ps
CPU time 1180.16 seconds
Started Jul 03 06:19:16 PM PDT 24
Finished Jul 03 06:38:57 PM PDT 24
Peak memory 265740 kb
Host smart-4aaad1a7-e412-4598-9caf-83922c28d74c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038686306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4038686306
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4224552698
Short name T274
Test name
Test status
Simulation time 39362392940 ps
CPU time 483.2 seconds
Started Jul 03 06:19:16 PM PDT 24
Finished Jul 03 06:27:20 PM PDT 24
Peak memory 257076 kb
Host smart-2a4267eb-3560-40d1-9697-add4fe7b1a26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224552698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4224552698
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1139493381
Short name T57
Test name
Test status
Simulation time 687297710 ps
CPU time 11.14 seconds
Started Jul 03 06:19:11 PM PDT 24
Finished Jul 03 06:19:22 PM PDT 24
Peak memory 249300 kb
Host smart-b899ac17-871c-4b70-aa85-f44549cc4641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11394
93381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1139493381
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.524713787
Short name T79
Test name
Test status
Simulation time 300984456 ps
CPU time 21.9 seconds
Started Jul 03 06:19:10 PM PDT 24
Finished Jul 03 06:19:32 PM PDT 24
Peak memory 249216 kb
Host smart-cd193cc2-16dc-4f63-97e9-9000e3f81564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52471
3787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.524713787
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.351478185
Short name T282
Test name
Test status
Simulation time 343276031 ps
CPU time 19.08 seconds
Started Jul 03 06:19:13 PM PDT 24
Finished Jul 03 06:19:32 PM PDT 24
Peak memory 249308 kb
Host smart-51581b3f-95e6-4f6b-ae55-ac51ae43250b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147
8185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.351478185
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2897445158
Short name T331
Test name
Test status
Simulation time 131383471 ps
CPU time 3.49 seconds
Started Jul 03 06:19:11 PM PDT 24
Finished Jul 03 06:19:15 PM PDT 24
Peak memory 251448 kb
Host smart-6fbdaf9d-c8ee-4b6c-9f27-d04c21befc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
45158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2897445158
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2847082565
Short name T90
Test name
Test status
Simulation time 12490825289 ps
CPU time 1632.26 seconds
Started Jul 03 06:19:17 PM PDT 24
Finished Jul 03 06:46:30 PM PDT 24
Peak memory 290132 kb
Host smart-4efb6afa-fd9c-4073-9052-3c7b9bddb0e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847082565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2847082565
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2138091053
Short name T465
Test name
Test status
Simulation time 67153153689 ps
CPU time 7316.14 seconds
Started Jul 03 06:19:21 PM PDT 24
Finished Jul 03 08:21:19 PM PDT 24
Peak memory 370896 kb
Host smart-647bf510-1506-4796-9b35-41e32dfab08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138091053 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2138091053
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1547127310
Short name T448
Test name
Test status
Simulation time 54147423124 ps
CPU time 3331.75 seconds
Started Jul 03 06:19:24 PM PDT 24
Finished Jul 03 07:14:56 PM PDT 24
Peak memory 290112 kb
Host smart-d3092f18-efe9-4b25-a789-46bc678b2879
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547127310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1547127310
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.847780
Short name T566
Test name
Test status
Simulation time 6717603364 ps
CPU time 205.43 seconds
Started Jul 03 06:19:20 PM PDT 24
Finished Jul 03 06:22:46 PM PDT 24
Peak memory 257152 kb
Host smart-9d4e2be8-0703-4eba-aa54-619a178ebc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84778
0 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.847780
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2430350092
Short name T339
Test name
Test status
Simulation time 821468063 ps
CPU time 51.82 seconds
Started Jul 03 06:19:22 PM PDT 24
Finished Jul 03 06:20:14 PM PDT 24
Peak memory 249232 kb
Host smart-cb0471f3-5ead-41f4-a342-c5e3fffbc094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
50092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2430350092
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3748892629
Short name T309
Test name
Test status
Simulation time 125573198422 ps
CPU time 1746.02 seconds
Started Jul 03 06:19:31 PM PDT 24
Finished Jul 03 06:48:38 PM PDT 24
Peak memory 273892 kb
Host smart-6e9453b3-7bb5-4a3f-896c-035890e727ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748892629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3748892629
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.860439228
Short name T590
Test name
Test status
Simulation time 107595312254 ps
CPU time 1615.25 seconds
Started Jul 03 06:19:27 PM PDT 24
Finished Jul 03 06:46:23 PM PDT 24
Peak memory 273080 kb
Host smart-9dcb212c-7c38-4589-b7a8-19c2d7d1ba8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860439228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.860439228
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.863659264
Short name T262
Test name
Test status
Simulation time 49285646207 ps
CPU time 555.03 seconds
Started Jul 03 06:19:29 PM PDT 24
Finished Jul 03 06:28:44 PM PDT 24
Peak memory 249140 kb
Host smart-3806c04e-77af-4456-a7c9-707f56ac09e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863659264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.863659264
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.689464861
Short name T467
Test name
Test status
Simulation time 50364959 ps
CPU time 5.24 seconds
Started Jul 03 06:19:21 PM PDT 24
Finished Jul 03 06:19:27 PM PDT 24
Peak memory 241068 kb
Host smart-357ffe6c-a4bb-4383-a33c-f917eebf5927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68946
4861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.689464861
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2032458016
Short name T454
Test name
Test status
Simulation time 288632241 ps
CPU time 31.54 seconds
Started Jul 03 06:19:22 PM PDT 24
Finished Jul 03 06:19:53 PM PDT 24
Peak memory 249340 kb
Host smart-4eb90546-6a90-48bd-9376-a2eea58cd335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20324
58016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2032458016
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1142607472
Short name T235
Test name
Test status
Simulation time 693445810 ps
CPU time 49.59 seconds
Started Jul 03 06:19:26 PM PDT 24
Finished Jul 03 06:20:16 PM PDT 24
Peak memory 256988 kb
Host smart-74729dcf-1fc3-4f6b-9d11-96c9a3be2b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11426
07472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1142607472
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2957413961
Short name T435
Test name
Test status
Simulation time 12537102376 ps
CPU time 46.69 seconds
Started Jul 03 06:19:21 PM PDT 24
Finished Jul 03 06:20:08 PM PDT 24
Peak memory 257480 kb
Host smart-cf6adf8f-7c31-4779-8866-1e2c491ff8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574
13961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2957413961
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.480788242
Short name T194
Test name
Test status
Simulation time 35266494 ps
CPU time 3.5 seconds
Started Jul 03 06:15:38 PM PDT 24
Finished Jul 03 06:15:42 PM PDT 24
Peak memory 249548 kb
Host smart-29b87d59-ac6c-4e65-a4fa-9f4cd3774551
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=480788242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.480788242
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2608848606
Short name T466
Test name
Test status
Simulation time 77123022155 ps
CPU time 2687.12 seconds
Started Jul 03 06:15:33 PM PDT 24
Finished Jul 03 07:00:20 PM PDT 24
Peak memory 289272 kb
Host smart-6dff11ce-b512-4969-8fa0-4846409fa6a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608848606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2608848606
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.368965217
Short name T444
Test name
Test status
Simulation time 599755320 ps
CPU time 26.8 seconds
Started Jul 03 06:15:40 PM PDT 24
Finished Jul 03 06:16:07 PM PDT 24
Peak memory 249168 kb
Host smart-d4371c83-cf2d-4f8d-8f6c-2c66c68745d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=368965217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.368965217
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3596458457
Short name T599
Test name
Test status
Simulation time 563408808 ps
CPU time 13.94 seconds
Started Jul 03 06:15:34 PM PDT 24
Finished Jul 03 06:15:48 PM PDT 24
Peak memory 256344 kb
Host smart-77dba1b0-06cf-47d8-8ac9-276bae339341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35964
58457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3596458457
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1089081603
Short name T63
Test name
Test status
Simulation time 1456275978 ps
CPU time 49.19 seconds
Started Jul 03 06:15:37 PM PDT 24
Finished Jul 03 06:16:27 PM PDT 24
Peak memory 248820 kb
Host smart-d1d6b1de-b9eb-4380-bb14-fe4cd182fecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
81603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1089081603
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.456687514
Short name T103
Test name
Test status
Simulation time 109551791996 ps
CPU time 1460.19 seconds
Started Jul 03 06:15:37 PM PDT 24
Finished Jul 03 06:39:58 PM PDT 24
Peak memory 273588 kb
Host smart-84579689-e75f-4759-b87e-c399ce153fb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456687514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.456687514
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.210838887
Short name T568
Test name
Test status
Simulation time 6105223844 ps
CPU time 237.85 seconds
Started Jul 03 06:15:35 PM PDT 24
Finished Jul 03 06:19:33 PM PDT 24
Peak memory 249364 kb
Host smart-3dc2d827-c20e-400c-b29b-9f74e90e33f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210838887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.210838887
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1853983204
Short name T468
Test name
Test status
Simulation time 792450646 ps
CPU time 16.51 seconds
Started Jul 03 06:15:29 PM PDT 24
Finished Jul 03 06:15:46 PM PDT 24
Peak memory 249216 kb
Host smart-d9eec983-ada5-4f70-aac8-90a601ffcf99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18539
83204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1853983204
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4153798323
Short name T441
Test name
Test status
Simulation time 3999455065 ps
CPU time 55.61 seconds
Started Jul 03 06:15:34 PM PDT 24
Finished Jul 03 06:16:30 PM PDT 24
Peak memory 249376 kb
Host smart-bfd0ae37-7fff-4e19-8a99-a15043532a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537
98323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4153798323
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2203699800
Short name T236
Test name
Test status
Simulation time 681741896 ps
CPU time 12.8 seconds
Started Jul 03 06:15:34 PM PDT 24
Finished Jul 03 06:15:47 PM PDT 24
Peak memory 249812 kb
Host smart-d6599292-b3b0-42f4-92e2-4292aea3d9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22036
99800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2203699800
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1960940620
Short name T623
Test name
Test status
Simulation time 88699885 ps
CPU time 5.85 seconds
Started Jul 03 06:15:30 PM PDT 24
Finished Jul 03 06:15:36 PM PDT 24
Peak memory 255664 kb
Host smart-c111a7a3-1143-43f5-bb0d-0dcdc694413a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19609
40620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1960940620
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.817577317
Short name T644
Test name
Test status
Simulation time 2367312979 ps
CPU time 214.15 seconds
Started Jul 03 06:15:40 PM PDT 24
Finished Jul 03 06:19:14 PM PDT 24
Peak memory 257568 kb
Host smart-947dc61f-97f8-44a4-be3d-f8d0651fddcb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817577317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.817577317
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1001401637
Short name T632
Test name
Test status
Simulation time 51180422232 ps
CPU time 1250.3 seconds
Started Jul 03 06:19:36 PM PDT 24
Finished Jul 03 06:40:27 PM PDT 24
Peak memory 286216 kb
Host smart-9965c7a0-8747-4568-bf8f-4314181a6d37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001401637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1001401637
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4140549189
Short name T451
Test name
Test status
Simulation time 4168038567 ps
CPU time 260.57 seconds
Started Jul 03 06:19:35 PM PDT 24
Finished Jul 03 06:23:56 PM PDT 24
Peak memory 251788 kb
Host smart-8a94e996-6869-4f20-8d97-7bef365d8721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41405
49189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4140549189
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3048940092
Short name T560
Test name
Test status
Simulation time 1627578105 ps
CPU time 26.22 seconds
Started Jul 03 06:19:36 PM PDT 24
Finished Jul 03 06:20:02 PM PDT 24
Peak memory 248808 kb
Host smart-5078522f-30da-4336-80d0-3644f02749ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30489
40092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3048940092
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3919334130
Short name T303
Test name
Test status
Simulation time 52774353501 ps
CPU time 3115.47 seconds
Started Jul 03 06:19:42 PM PDT 24
Finished Jul 03 07:11:38 PM PDT 24
Peak memory 289672 kb
Host smart-ae97bd31-b1a7-486c-b526-bccb0b8e9304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919334130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3919334130
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.916314339
Short name T671
Test name
Test status
Simulation time 16641534078 ps
CPU time 926.39 seconds
Started Jul 03 06:19:45 PM PDT 24
Finished Jul 03 06:35:12 PM PDT 24
Peak memory 273668 kb
Host smart-968570a9-774d-43ef-894a-26f0d76a2c0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916314339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.916314339
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1440129688
Short name T254
Test name
Test status
Simulation time 8003775282 ps
CPU time 346.3 seconds
Started Jul 03 06:19:35 PM PDT 24
Finished Jul 03 06:25:22 PM PDT 24
Peak memory 256392 kb
Host smart-7729ac49-435b-49fb-bc50-151daab3a5af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440129688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1440129688
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.312163190
Short name T479
Test name
Test status
Simulation time 54505587 ps
CPU time 6.61 seconds
Started Jul 03 06:19:33 PM PDT 24
Finished Jul 03 06:19:40 PM PDT 24
Peak memory 253908 kb
Host smart-14fb4448-7a3c-4e43-82e3-e2ac444deba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31216
3190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.312163190
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2602348774
Short name T489
Test name
Test status
Simulation time 874226097 ps
CPU time 15.22 seconds
Started Jul 03 06:19:34 PM PDT 24
Finished Jul 03 06:19:49 PM PDT 24
Peak memory 254456 kb
Host smart-22cb25ee-f5c0-43d0-8fe3-37f87d41fa37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26023
48774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2602348774
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.4050293006
Short name T422
Test name
Test status
Simulation time 142520095 ps
CPU time 10.66 seconds
Started Jul 03 06:19:35 PM PDT 24
Finished Jul 03 06:19:46 PM PDT 24
Peak memory 248624 kb
Host smart-be29ffae-f816-4a74-b8b5-1401417700c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40502
93006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.4050293006
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.278733326
Short name T430
Test name
Test status
Simulation time 206969107 ps
CPU time 11.37 seconds
Started Jul 03 06:19:32 PM PDT 24
Finished Jul 03 06:19:44 PM PDT 24
Peak memory 257432 kb
Host smart-f3d3fa00-3fdc-455c-8a3a-9bc2456e8f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27873
3326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.278733326
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.157572909
Short name T663
Test name
Test status
Simulation time 88889781133 ps
CPU time 2554.63 seconds
Started Jul 03 06:19:44 PM PDT 24
Finished Jul 03 07:02:19 PM PDT 24
Peak memory 290080 kb
Host smart-798cb281-e596-4280-a7fa-268a8378bc93
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157572909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.157572909
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1955065552
Short name T476
Test name
Test status
Simulation time 29400898121 ps
CPU time 1923.64 seconds
Started Jul 03 06:19:48 PM PDT 24
Finished Jul 03 06:51:52 PM PDT 24
Peak memory 274020 kb
Host smart-8775276c-3a8c-4988-a0a4-577229a43479
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955065552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1955065552
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3657484124
Short name T657
Test name
Test status
Simulation time 4025652362 ps
CPU time 81.87 seconds
Started Jul 03 06:19:49 PM PDT 24
Finished Jul 03 06:21:11 PM PDT 24
Peak memory 256956 kb
Host smart-8641c283-5d30-4392-bb88-6e214da5242a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
84124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3657484124
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3405405193
Short name T369
Test name
Test status
Simulation time 186695218 ps
CPU time 21.33 seconds
Started Jul 03 06:19:48 PM PDT 24
Finished Jul 03 06:20:10 PM PDT 24
Peak memory 249280 kb
Host smart-dd606948-d460-49c0-888a-c0a65d4ec614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34054
05193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3405405193
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.841165280
Short name T630
Test name
Test status
Simulation time 29718092380 ps
CPU time 1396.86 seconds
Started Jul 03 06:19:52 PM PDT 24
Finished Jul 03 06:43:09 PM PDT 24
Peak memory 273916 kb
Host smart-555be5fb-66e5-4490-b647-bf1cbd269568
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841165280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.841165280
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.4294458712
Short name T268
Test name
Test status
Simulation time 4884022051 ps
CPU time 100.11 seconds
Started Jul 03 06:19:48 PM PDT 24
Finished Jul 03 06:21:29 PM PDT 24
Peak memory 249364 kb
Host smart-2773dddd-a079-47af-80d4-b1178a294ce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294458712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4294458712
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1089059396
Short name T580
Test name
Test status
Simulation time 267187001 ps
CPU time 25.9 seconds
Started Jul 03 06:19:47 PM PDT 24
Finished Jul 03 06:20:13 PM PDT 24
Peak memory 256752 kb
Host smart-0f710f90-e895-4f57-9289-729129578a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
59396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1089059396
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3815477873
Short name T80
Test name
Test status
Simulation time 163796712 ps
CPU time 20.77 seconds
Started Jul 03 06:19:49 PM PDT 24
Finished Jul 03 06:20:10 PM PDT 24
Peak memory 248536 kb
Host smart-242a456f-e7ed-4527-90aa-85f36472e4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
77873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3815477873
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3899687876
Short name T425
Test name
Test status
Simulation time 2765183978 ps
CPU time 10.15 seconds
Started Jul 03 06:19:48 PM PDT 24
Finished Jul 03 06:19:58 PM PDT 24
Peak memory 249524 kb
Host smart-f85c4d9d-1da3-4ea1-8eb5-c6ef904ed025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
87876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3899687876
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2318289566
Short name T509
Test name
Test status
Simulation time 231126470 ps
CPU time 21.33 seconds
Started Jul 03 06:19:42 PM PDT 24
Finished Jul 03 06:20:04 PM PDT 24
Peak memory 257476 kb
Host smart-752c65c4-df86-4174-8616-20e29617e2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23182
89566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2318289566
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.632157066
Short name T105
Test name
Test status
Simulation time 23104909145 ps
CPU time 1313.73 seconds
Started Jul 03 06:19:53 PM PDT 24
Finished Jul 03 06:41:47 PM PDT 24
Peak memory 287252 kb
Host smart-fed5dca7-9d04-471a-a74e-947e34e52006
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632157066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.632157066
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1918557943
Short name T398
Test name
Test status
Simulation time 122728724435 ps
CPU time 1872.49 seconds
Started Jul 03 06:19:57 PM PDT 24
Finished Jul 03 06:51:10 PM PDT 24
Peak memory 273648 kb
Host smart-8921a529-c629-4207-af83-2b3ca2cc4191
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918557943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1918557943
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.491735444
Short name T673
Test name
Test status
Simulation time 4468935831 ps
CPU time 267.37 seconds
Started Jul 03 06:19:55 PM PDT 24
Finished Jul 03 06:24:23 PM PDT 24
Peak memory 256880 kb
Host smart-974b38ee-be4c-4963-9edf-9852d1957096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49173
5444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.491735444
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1648871822
Short name T684
Test name
Test status
Simulation time 628826417 ps
CPU time 41.16 seconds
Started Jul 03 06:19:56 PM PDT 24
Finished Jul 03 06:20:38 PM PDT 24
Peak memory 257256 kb
Host smart-0144543f-74ea-4090-a96a-188a6a98f877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16488
71822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1648871822
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2560707755
Short name T245
Test name
Test status
Simulation time 46658930993 ps
CPU time 888.46 seconds
Started Jul 03 06:19:58 PM PDT 24
Finished Jul 03 06:34:47 PM PDT 24
Peak memory 274020 kb
Host smart-5669a502-eeef-41c0-999e-552efea2f4a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560707755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2560707755
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4210991285
Short name T397
Test name
Test status
Simulation time 28878971651 ps
CPU time 1777.82 seconds
Started Jul 03 06:19:59 PM PDT 24
Finished Jul 03 06:49:38 PM PDT 24
Peak memory 290164 kb
Host smart-9f66dc04-2052-476d-a921-2ec9fb0dff4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210991285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4210991285
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3364115814
Short name T439
Test name
Test status
Simulation time 6148773342 ps
CPU time 24.38 seconds
Started Jul 03 06:19:54 PM PDT 24
Finished Jul 03 06:20:19 PM PDT 24
Peak memory 256008 kb
Host smart-8b931cc3-518b-4e9f-8f19-dfc25512b42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33641
15814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3364115814
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.283690988
Short name T654
Test name
Test status
Simulation time 836212314 ps
CPU time 18.94 seconds
Started Jul 03 06:19:55 PM PDT 24
Finished Jul 03 06:20:14 PM PDT 24
Peak memory 256568 kb
Host smart-2ea15f63-7df7-44e9-a6d5-9333ef567cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369
0988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.283690988
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3249587261
Short name T409
Test name
Test status
Simulation time 250520283 ps
CPU time 32.68 seconds
Started Jul 03 06:19:55 PM PDT 24
Finished Jul 03 06:20:27 PM PDT 24
Peak memory 249332 kb
Host smart-13a264cc-27cc-45e5-9da0-00aa378cb894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32495
87261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3249587261
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2172114413
Short name T473
Test name
Test status
Simulation time 1467683794 ps
CPU time 64.79 seconds
Started Jul 03 06:19:51 PM PDT 24
Finished Jul 03 06:20:56 PM PDT 24
Peak memory 256648 kb
Host smart-bcae6c2b-3c22-457d-a0a0-6ddb1bc94db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21721
14413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2172114413
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2407140909
Short name T225
Test name
Test status
Simulation time 168006207719 ps
CPU time 2279.87 seconds
Started Jul 03 06:19:58 PM PDT 24
Finished Jul 03 06:57:58 PM PDT 24
Peak memory 289780 kb
Host smart-c2e10097-d89b-4e0e-b34a-7abde0cacfc1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407140909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2407140909
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.853613882
Short name T54
Test name
Test status
Simulation time 202245894896 ps
CPU time 7993.65 seconds
Started Jul 03 06:20:01 PM PDT 24
Finished Jul 03 08:33:16 PM PDT 24
Peak memory 339448 kb
Host smart-cf150183-58e5-494e-8557-cafdc2177388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853613882 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.853613882
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3403632056
Short name T45
Test name
Test status
Simulation time 31221573432 ps
CPU time 1873.35 seconds
Started Jul 03 06:20:05 PM PDT 24
Finished Jul 03 06:51:19 PM PDT 24
Peak memory 273604 kb
Host smart-bf73dd89-33b8-47d0-abd1-def2d1f8e02a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403632056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3403632056
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1288861329
Short name T362
Test name
Test status
Simulation time 11449059951 ps
CPU time 161.72 seconds
Started Jul 03 06:20:06 PM PDT 24
Finished Jul 03 06:22:48 PM PDT 24
Peak memory 257032 kb
Host smart-d5b20ed3-5083-4844-a014-c8cd2f7fa7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12888
61329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1288861329
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3695735903
Short name T386
Test name
Test status
Simulation time 1116031774 ps
CPU time 65.46 seconds
Started Jul 03 06:20:06 PM PDT 24
Finished Jul 03 06:21:12 PM PDT 24
Peak memory 249700 kb
Host smart-203c28dd-eabe-432d-ae9a-8c261e967c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36957
35903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3695735903
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3717953984
Short name T317
Test name
Test status
Simulation time 48577244869 ps
CPU time 2581.33 seconds
Started Jul 03 06:20:10 PM PDT 24
Finished Jul 03 07:03:12 PM PDT 24
Peak memory 290364 kb
Host smart-3f2e16a1-b514-453d-9fae-af91727994b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717953984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3717953984
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2070315928
Short name T525
Test name
Test status
Simulation time 72359773809 ps
CPU time 2090.24 seconds
Started Jul 03 06:20:10 PM PDT 24
Finished Jul 03 06:55:01 PM PDT 24
Peak memory 289784 kb
Host smart-dc271e30-49dc-48b1-ad45-223b2bd8c100
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070315928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2070315928
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3063125973
Short name T277
Test name
Test status
Simulation time 74771781220 ps
CPU time 428.42 seconds
Started Jul 03 06:20:11 PM PDT 24
Finished Jul 03 06:27:20 PM PDT 24
Peak memory 249376 kb
Host smart-768cce0e-3725-48bf-974d-b09218463f5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063125973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3063125973
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1501982742
Short name T378
Test name
Test status
Simulation time 724837719 ps
CPU time 16.05 seconds
Started Jul 03 06:20:09 PM PDT 24
Finished Jul 03 06:20:25 PM PDT 24
Peak memory 256800 kb
Host smart-465e5b5a-fec5-478b-add8-8b4b7c5d7367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15019
82742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1501982742
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1191404123
Short name T50
Test name
Test status
Simulation time 635197912 ps
CPU time 35.46 seconds
Started Jul 03 06:20:07 PM PDT 24
Finished Jul 03 06:20:43 PM PDT 24
Peak memory 249316 kb
Host smart-5624ceab-ad53-4291-b14f-2d4e4a7ca9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11914
04123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1191404123
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1205414454
Short name T28
Test name
Test status
Simulation time 669557421 ps
CPU time 52.75 seconds
Started Jul 03 06:20:06 PM PDT 24
Finished Jul 03 06:20:59 PM PDT 24
Peak memory 257180 kb
Host smart-c101289a-7e43-4f17-b4ad-f3500c3a52a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12054
14454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1205414454
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.19171793
Short name T417
Test name
Test status
Simulation time 328408774 ps
CPU time 10.64 seconds
Started Jul 03 06:20:02 PM PDT 24
Finished Jul 03 06:20:13 PM PDT 24
Peak memory 249704 kb
Host smart-42a7e309-27e7-4dd5-badc-22d307dabeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171
793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.19171793
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.501661436
Short name T240
Test name
Test status
Simulation time 49562526899 ps
CPU time 2962.92 seconds
Started Jul 03 06:20:10 PM PDT 24
Finished Jul 03 07:09:33 PM PDT 24
Peak memory 298468 kb
Host smart-6d9eb9a8-feea-49a6-b86f-ccfaead12c87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501661436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.501661436
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3858488679
Short name T486
Test name
Test status
Simulation time 65248121021 ps
CPU time 1488.86 seconds
Started Jul 03 06:20:17 PM PDT 24
Finished Jul 03 06:45:07 PM PDT 24
Peak memory 286668 kb
Host smart-1ec47ddc-88af-4433-86bc-d8a688e7930c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858488679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3858488679
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3224359359
Short name T455
Test name
Test status
Simulation time 3832113226 ps
CPU time 108.74 seconds
Started Jul 03 06:20:14 PM PDT 24
Finished Jul 03 06:22:04 PM PDT 24
Peak memory 257016 kb
Host smart-19e3a551-2956-486b-8d93-4a8d11958c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32243
59359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3224359359
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.515655441
Short name T400
Test name
Test status
Simulation time 1559636744 ps
CPU time 33.28 seconds
Started Jul 03 06:20:11 PM PDT 24
Finished Jul 03 06:20:45 PM PDT 24
Peak memory 248772 kb
Host smart-47d9d4e9-01f3-446f-b941-2c3ef2261338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51565
5441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.515655441
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.4143778258
Short name T609
Test name
Test status
Simulation time 91350432338 ps
CPU time 2485.49 seconds
Started Jul 03 06:20:19 PM PDT 24
Finished Jul 03 07:01:45 PM PDT 24
Peak memory 289600 kb
Host smart-c5a93bba-407d-4968-a970-10b102bb24ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143778258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.4143778258
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2842282168
Short name T676
Test name
Test status
Simulation time 58861018982 ps
CPU time 1064.77 seconds
Started Jul 03 06:20:14 PM PDT 24
Finished Jul 03 06:38:00 PM PDT 24
Peak memory 273416 kb
Host smart-1c6d6639-42fe-454c-9c9c-68c9d5fcfaa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842282168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2842282168
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.4247355120
Short name T265
Test name
Test status
Simulation time 10323842847 ps
CPU time 109.14 seconds
Started Jul 03 06:20:16 PM PDT 24
Finished Jul 03 06:22:05 PM PDT 24
Peak memory 249032 kb
Host smart-d39ea042-25a0-4794-8981-623a69336ac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247355120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.4247355120
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1028670018
Short name T628
Test name
Test status
Simulation time 702567797 ps
CPU time 35.27 seconds
Started Jul 03 06:20:11 PM PDT 24
Finished Jul 03 06:20:47 PM PDT 24
Peak memory 256780 kb
Host smart-1139e81f-9c10-41f9-86ff-fa00a204c10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10286
70018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1028670018
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.487070221
Short name T86
Test name
Test status
Simulation time 257943017 ps
CPU time 8.17 seconds
Started Jul 03 06:20:11 PM PDT 24
Finished Jul 03 06:20:19 PM PDT 24
Peak memory 254164 kb
Host smart-ebb6b511-475f-411a-bfff-41334042595a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48707
0221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.487070221
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.127662106
Short name T531
Test name
Test status
Simulation time 4256428312 ps
CPU time 46.32 seconds
Started Jul 03 06:20:15 PM PDT 24
Finished Jul 03 06:21:02 PM PDT 24
Peak memory 257072 kb
Host smart-935d2dbf-257b-4039-9e4f-b3c4777a14af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12766
2106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.127662106
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1523756842
Short name T472
Test name
Test status
Simulation time 101064102 ps
CPU time 10.22 seconds
Started Jul 03 06:20:11 PM PDT 24
Finished Jul 03 06:20:22 PM PDT 24
Peak memory 256232 kb
Host smart-7d53c749-ea63-456e-b9ca-aec1a0362c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
56842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1523756842
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.878918779
Short name T232
Test name
Test status
Simulation time 62992910904 ps
CPU time 3483.6 seconds
Started Jul 03 06:20:18 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 298996 kb
Host smart-575715ce-ceb2-471a-bd54-25437048df0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878918779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.878918779
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3371525116
Short name T68
Test name
Test status
Simulation time 83565108600 ps
CPU time 5623.88 seconds
Started Jul 03 06:20:18 PM PDT 24
Finished Jul 03 07:54:03 PM PDT 24
Peak memory 333328 kb
Host smart-4ab19d9c-db6f-4a38-b487-3156e0ff0a86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371525116 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3371525116
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2916161957
Short name T170
Test name
Test status
Simulation time 12861929215 ps
CPU time 733.45 seconds
Started Jul 03 06:20:22 PM PDT 24
Finished Jul 03 06:32:36 PM PDT 24
Peak memory 273480 kb
Host smart-6f539478-6d75-4eb0-933e-e4e8f342be39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916161957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2916161957
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.4002326229
Short name T585
Test name
Test status
Simulation time 2512639403 ps
CPU time 111.92 seconds
Started Jul 03 06:20:23 PM PDT 24
Finished Jul 03 06:22:15 PM PDT 24
Peak memory 256804 kb
Host smart-23a0eb84-b8fe-447d-ac16-c20204240b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40023
26229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4002326229
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.78942735
Short name T464
Test name
Test status
Simulation time 414713273 ps
CPU time 26.79 seconds
Started Jul 03 06:20:23 PM PDT 24
Finished Jul 03 06:20:51 PM PDT 24
Peak memory 256540 kb
Host smart-5937e311-bd89-4fbd-b2cc-e53bbb7048cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78942
735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.78942735
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2242774276
Short name T512
Test name
Test status
Simulation time 72615614024 ps
CPU time 1530.83 seconds
Started Jul 03 06:20:27 PM PDT 24
Finished Jul 03 06:45:58 PM PDT 24
Peak memory 290068 kb
Host smart-496b12ca-ff41-4b5a-97f2-f417d64f053d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242774276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2242774276
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.213746652
Short name T266
Test name
Test status
Simulation time 7689973554 ps
CPU time 310.45 seconds
Started Jul 03 06:20:27 PM PDT 24
Finished Jul 03 06:25:37 PM PDT 24
Peak memory 249420 kb
Host smart-5a88614b-4af9-47c1-a4e3-973de2193acd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213746652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.213746652
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.9191513
Short name T505
Test name
Test status
Simulation time 571106614 ps
CPU time 22.62 seconds
Started Jul 03 06:20:18 PM PDT 24
Finished Jul 03 06:20:41 PM PDT 24
Peak memory 249276 kb
Host smart-5033ddac-492a-4404-ad6b-036c1cc3d9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91915
13 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.9191513
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.686214107
Short name T343
Test name
Test status
Simulation time 3244283614 ps
CPU time 45.77 seconds
Started Jul 03 06:20:18 PM PDT 24
Finished Jul 03 06:21:04 PM PDT 24
Peak memory 249108 kb
Host smart-e10b78b6-8d21-49a6-9bfd-3b1aa4ed4f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68621
4107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.686214107
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4277907273
Short name T21
Test name
Test status
Simulation time 45304898 ps
CPU time 4.48 seconds
Started Jul 03 06:20:24 PM PDT 24
Finished Jul 03 06:20:28 PM PDT 24
Peak memory 240616 kb
Host smart-1fdf44f5-df49-4249-8885-232ee2e9560b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42779
07273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4277907273
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2994711164
Short name T458
Test name
Test status
Simulation time 157283312 ps
CPU time 3.62 seconds
Started Jul 03 06:20:16 PM PDT 24
Finished Jul 03 06:20:20 PM PDT 24
Peak memory 241052 kb
Host smart-c3a31dbf-d2c7-4f24-8e6b-b46a43d0c338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29947
11164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2994711164
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2011298836
Short name T94
Test name
Test status
Simulation time 18946491918 ps
CPU time 1520.5 seconds
Started Jul 03 06:20:46 PM PDT 24
Finished Jul 03 06:46:06 PM PDT 24
Peak memory 290320 kb
Host smart-aad1374b-4962-4962-a136-634379c13de2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011298836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2011298836
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2560497110
Short name T693
Test name
Test status
Simulation time 951905682 ps
CPU time 91.03 seconds
Started Jul 03 06:20:40 PM PDT 24
Finished Jul 03 06:22:11 PM PDT 24
Peak memory 257440 kb
Host smart-75eadfc5-31e6-4a9d-940b-98897342b3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25604
97110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2560497110
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.593961285
Short name T431
Test name
Test status
Simulation time 3105586733 ps
CPU time 50.45 seconds
Started Jul 03 06:20:40 PM PDT 24
Finished Jul 03 06:21:30 PM PDT 24
Peak memory 256596 kb
Host smart-7ed0d05a-ba35-4e3b-bdcb-8d4805c0dda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59396
1285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.593961285
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1985261817
Short name T677
Test name
Test status
Simulation time 18601976397 ps
CPU time 740.81 seconds
Started Jul 03 06:20:43 PM PDT 24
Finished Jul 03 06:33:04 PM PDT 24
Peak memory 273872 kb
Host smart-557ae2ce-3b0c-4187-a079-c918ab75585f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985261817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1985261817
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.323205771
Short name T101
Test name
Test status
Simulation time 54080054518 ps
CPU time 1978.78 seconds
Started Jul 03 06:20:43 PM PDT 24
Finished Jul 03 06:53:42 PM PDT 24
Peak memory 290136 kb
Host smart-bc0e8a6f-9453-42ce-a5e1-bb9b239af4e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323205771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.323205771
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1501296864
Short name T201
Test name
Test status
Simulation time 7665971826 ps
CPU time 244.06 seconds
Started Jul 03 06:20:43 PM PDT 24
Finished Jul 03 06:24:47 PM PDT 24
Peak memory 249388 kb
Host smart-6e775fb4-38ca-42a2-9e38-bedd4ea0c342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501296864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1501296864
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3550897052
Short name T482
Test name
Test status
Simulation time 10229627162 ps
CPU time 54.62 seconds
Started Jul 03 06:20:37 PM PDT 24
Finished Jul 03 06:21:32 PM PDT 24
Peak memory 256736 kb
Host smart-e8290fb5-b32c-418d-be76-d83f7a2a4b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35508
97052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3550897052
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1312816200
Short name T659
Test name
Test status
Simulation time 2759619579 ps
CPU time 48.07 seconds
Started Jul 03 06:20:39 PM PDT 24
Finished Jul 03 06:21:28 PM PDT 24
Peak memory 256692 kb
Host smart-234fe42f-8ca7-42ca-933a-71ae42961336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13128
16200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1312816200
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1548428504
Short name T662
Test name
Test status
Simulation time 853330310 ps
CPU time 54.2 seconds
Started Jul 03 06:20:44 PM PDT 24
Finished Jul 03 06:21:39 PM PDT 24
Peak memory 257072 kb
Host smart-d05b2083-888f-4eb2-9260-f259a878a447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15484
28504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1548428504
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1510567434
Short name T334
Test name
Test status
Simulation time 610907364 ps
CPU time 11.86 seconds
Started Jul 03 06:20:36 PM PDT 24
Finished Jul 03 06:20:48 PM PDT 24
Peak memory 257400 kb
Host smart-6ba78085-41db-41a0-8836-b825fd8dde61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15105
67434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1510567434
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4271798539
Short name T74
Test name
Test status
Simulation time 24289964137 ps
CPU time 541.55 seconds
Started Jul 03 06:20:50 PM PDT 24
Finished Jul 03 06:29:52 PM PDT 24
Peak memory 265828 kb
Host smart-f9f38b44-0727-43bc-a353-343090baf3a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271798539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4271798539
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.4157153018
Short name T166
Test name
Test status
Simulation time 317667386347 ps
CPU time 8976.18 seconds
Started Jul 03 06:20:46 PM PDT 24
Finished Jul 03 08:50:24 PM PDT 24
Peak memory 413400 kb
Host smart-f06db087-aac4-4962-bd2c-819edbadd078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157153018 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.4157153018
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4174216602
Short name T415
Test name
Test status
Simulation time 52095426883 ps
CPU time 1667.9 seconds
Started Jul 03 06:20:52 PM PDT 24
Finished Jul 03 06:48:40 PM PDT 24
Peak memory 273432 kb
Host smart-c46d297d-168b-438d-881d-fe0f7f318404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174216602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4174216602
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.296299172
Short name T402
Test name
Test status
Simulation time 15328374463 ps
CPU time 225.15 seconds
Started Jul 03 06:20:49 PM PDT 24
Finished Jul 03 06:24:34 PM PDT 24
Peak memory 257012 kb
Host smart-643eb81a-5ab5-4389-a19e-751cef1c9688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29629
9172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.296299172
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1616665539
Short name T588
Test name
Test status
Simulation time 455696384 ps
CPU time 24.25 seconds
Started Jul 03 06:20:47 PM PDT 24
Finished Jul 03 06:21:11 PM PDT 24
Peak memory 249248 kb
Host smart-cac3142c-5e66-4d6f-8126-6f22b458e7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16166
65539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1616665539
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.923631263
Short name T313
Test name
Test status
Simulation time 85851069386 ps
CPU time 2654.73 seconds
Started Jul 03 06:20:53 PM PDT 24
Finished Jul 03 07:05:08 PM PDT 24
Peak memory 284380 kb
Host smart-e5b86ce7-83e6-48ad-908c-b7d67f8367d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923631263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.923631263
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.98802896
Short name T396
Test name
Test status
Simulation time 39629213703 ps
CPU time 2367.57 seconds
Started Jul 03 06:20:53 PM PDT 24
Finished Jul 03 07:00:21 PM PDT 24
Peak memory 273948 kb
Host smart-ca23acb6-e072-4902-838b-c9065e3279c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98802896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.98802896
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2037920328
Short name T686
Test name
Test status
Simulation time 26502701945 ps
CPU time 297.76 seconds
Started Jul 03 06:20:49 PM PDT 24
Finished Jul 03 06:25:47 PM PDT 24
Peak memory 249388 kb
Host smart-7e2921a5-0728-4900-8b35-8eb02d80ab5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037920328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2037920328
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1814203692
Short name T3
Test name
Test status
Simulation time 138577116 ps
CPU time 9.56 seconds
Started Jul 03 06:20:48 PM PDT 24
Finished Jul 03 06:20:58 PM PDT 24
Peak memory 256764 kb
Host smart-ca54e9ae-fa51-4619-bba7-e357eaa76e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
03692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1814203692
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.809058370
Short name T340
Test name
Test status
Simulation time 383484421 ps
CPU time 12.04 seconds
Started Jul 03 06:20:49 PM PDT 24
Finished Jul 03 06:21:02 PM PDT 24
Peak memory 255808 kb
Host smart-ede319b8-99f8-4111-9a8e-e1ee2604b0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80905
8370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.809058370
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2199640613
Short name T221
Test name
Test status
Simulation time 2739681845 ps
CPU time 52.75 seconds
Started Jul 03 06:20:51 PM PDT 24
Finished Jul 03 06:21:44 PM PDT 24
Peak memory 249124 kb
Host smart-4cb37d4a-a7f7-439f-b101-3aaf77f2307b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21996
40613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2199640613
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1067268598
Short name T527
Test name
Test status
Simulation time 10505899460 ps
CPU time 44.08 seconds
Started Jul 03 06:20:46 PM PDT 24
Finished Jul 03 06:21:30 PM PDT 24
Peak memory 257384 kb
Host smart-7eb00669-cdb0-405f-b3cf-f8539d76a14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
68598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1067268598
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3215386525
Short name T43
Test name
Test status
Simulation time 127370102429 ps
CPU time 1348.33 seconds
Started Jul 03 06:20:57 PM PDT 24
Finished Jul 03 06:43:26 PM PDT 24
Peak memory 273692 kb
Host smart-8c04622d-d7f1-4cb0-b437-1d3d8ab9fcc1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215386525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3215386525
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3979283651
Short name T443
Test name
Test status
Simulation time 79727796857 ps
CPU time 1299.54 seconds
Started Jul 03 06:21:04 PM PDT 24
Finished Jul 03 06:42:44 PM PDT 24
Peak memory 273968 kb
Host smart-07398eb5-663c-4cac-b96d-e383effd0ccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979283651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3979283651
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2554846662
Short name T593
Test name
Test status
Simulation time 1148385619 ps
CPU time 30.42 seconds
Started Jul 03 06:21:00 PM PDT 24
Finished Jul 03 06:21:31 PM PDT 24
Peak memory 257452 kb
Host smart-53651901-da0d-484c-96b8-95a8e7a1ab7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25548
46662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2554846662
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2457292165
Short name T426
Test name
Test status
Simulation time 71903506 ps
CPU time 12.6 seconds
Started Jul 03 06:20:57 PM PDT 24
Finished Jul 03 06:21:10 PM PDT 24
Peak memory 248672 kb
Host smart-67e5ad2f-5796-4b18-b4ca-9872638ff017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24572
92165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2457292165
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1895373117
Short name T682
Test name
Test status
Simulation time 79533926263 ps
CPU time 2254.26 seconds
Started Jul 03 06:21:07 PM PDT 24
Finished Jul 03 06:58:41 PM PDT 24
Peak memory 273876 kb
Host smart-5b3c779a-25e2-4ff9-aa27-586e61837ebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895373117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1895373117
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3261347503
Short name T389
Test name
Test status
Simulation time 18282758145 ps
CPU time 1176.97 seconds
Started Jul 03 06:21:07 PM PDT 24
Finished Jul 03 06:40:44 PM PDT 24
Peak memory 265780 kb
Host smart-bfd7b128-c118-4e44-ba57-3b59f46b51c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261347503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3261347503
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1127146216
Short name T257
Test name
Test status
Simulation time 8091588712 ps
CPU time 176.48 seconds
Started Jul 03 06:21:04 PM PDT 24
Finished Jul 03 06:24:00 PM PDT 24
Peak memory 249128 kb
Host smart-61460d7e-17aa-4672-a2d7-82139cb3196d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127146216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1127146216
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2577696976
Short name T607
Test name
Test status
Simulation time 4339166871 ps
CPU time 71.37 seconds
Started Jul 03 06:20:55 PM PDT 24
Finished Jul 03 06:22:06 PM PDT 24
Peak memory 256928 kb
Host smart-210e9fb0-bd12-42cb-8ed7-25be5fe78413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25776
96976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2577696976
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1296025686
Short name T432
Test name
Test status
Simulation time 15749916842 ps
CPU time 53.3 seconds
Started Jul 03 06:20:58 PM PDT 24
Finished Jul 03 06:21:51 PM PDT 24
Peak memory 249332 kb
Host smart-9fee1043-cd78-4f96-a0f5-03a2349212dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12960
25686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1296025686
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2070883090
Short name T355
Test name
Test status
Simulation time 7112063812 ps
CPU time 51.59 seconds
Started Jul 03 06:21:03 PM PDT 24
Finished Jul 03 06:21:55 PM PDT 24
Peak memory 249404 kb
Host smart-d22b0797-b4aa-404a-ba95-d699f34edc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708
83090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2070883090
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3427361970
Short name T383
Test name
Test status
Simulation time 541285819 ps
CPU time 35.58 seconds
Started Jul 03 06:20:54 PM PDT 24
Finished Jul 03 06:21:29 PM PDT 24
Peak memory 256468 kb
Host smart-6982911b-fcce-4234-ab02-840baaeb06ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
61970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3427361970
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4277027274
Short name T287
Test name
Test status
Simulation time 41662215207 ps
CPU time 872.9 seconds
Started Jul 03 06:21:11 PM PDT 24
Finished Jul 03 06:35:44 PM PDT 24
Peak memory 274056 kb
Host smart-b0450e96-987f-4a80-ba55-b0c651647c3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277027274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4277027274
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3601302454
Short name T100
Test name
Test status
Simulation time 205767515564 ps
CPU time 3123.46 seconds
Started Jul 03 06:21:08 PM PDT 24
Finished Jul 03 07:13:13 PM PDT 24
Peak memory 306216 kb
Host smart-19634818-9cef-422a-b63d-6b256d794ca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601302454 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3601302454
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2110872322
Short name T291
Test name
Test status
Simulation time 20312402150 ps
CPU time 1213.83 seconds
Started Jul 03 06:21:23 PM PDT 24
Finished Jul 03 06:41:37 PM PDT 24
Peak memory 273976 kb
Host smart-f3816aa1-aa7b-4d48-b280-a68fd88d3354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110872322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2110872322
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1318570619
Short name T485
Test name
Test status
Simulation time 6451431940 ps
CPU time 179.85 seconds
Started Jul 03 06:21:19 PM PDT 24
Finished Jul 03 06:24:19 PM PDT 24
Peak memory 252500 kb
Host smart-473b2dcb-1fc2-4512-bd34-4b9cf567c4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
70619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1318570619
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3701809214
Short name T1
Test name
Test status
Simulation time 104169060 ps
CPU time 11.11 seconds
Started Jul 03 06:21:18 PM PDT 24
Finished Jul 03 06:21:30 PM PDT 24
Peak memory 249688 kb
Host smart-f2fac230-0b23-4405-a6f7-a76f24f1b4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
09214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3701809214
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.857256225
Short name T655
Test name
Test status
Simulation time 149141874860 ps
CPU time 2227.77 seconds
Started Jul 03 06:21:24 PM PDT 24
Finished Jul 03 06:58:33 PM PDT 24
Peak memory 285420 kb
Host smart-56bd026e-ad3d-46a1-b130-db227df9b434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857256225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.857256225
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2647213451
Short name T76
Test name
Test status
Simulation time 73631247654 ps
CPU time 2536.45 seconds
Started Jul 03 06:21:28 PM PDT 24
Finished Jul 03 07:03:45 PM PDT 24
Peak memory 290256 kb
Host smart-9047549a-50e0-4d5b-848c-1390cb0fb572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647213451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2647213451
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2140470475
Short name T251
Test name
Test status
Simulation time 32889902427 ps
CPU time 317.13 seconds
Started Jul 03 06:21:19 PM PDT 24
Finished Jul 03 06:26:36 PM PDT 24
Peak memory 255936 kb
Host smart-147c2411-cc47-4f0d-99be-ccf1122a8927
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140470475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2140470475
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.101622493
Short name T98
Test name
Test status
Simulation time 3515707725 ps
CPU time 40.24 seconds
Started Jul 03 06:21:15 PM PDT 24
Finished Jul 03 06:21:55 PM PDT 24
Peak memory 257188 kb
Host smart-641300d6-89e2-4d12-b911-ba8f891096dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10162
2493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.101622493
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2416240356
Short name T456
Test name
Test status
Simulation time 977305781 ps
CPU time 58.28 seconds
Started Jul 03 06:21:18 PM PDT 24
Finished Jul 03 06:22:17 PM PDT 24
Peak memory 256804 kb
Host smart-f9ae4bca-b0f3-4422-a6f9-462360117819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24162
40356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2416240356
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3070638181
Short name T20
Test name
Test status
Simulation time 2536609809 ps
CPU time 10.53 seconds
Started Jul 03 06:21:21 PM PDT 24
Finished Jul 03 06:21:32 PM PDT 24
Peak memory 248840 kb
Host smart-5fb71278-2f42-430b-8c81-c43b01b69f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30706
38181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3070638181
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.351143110
Short name T367
Test name
Test status
Simulation time 5739178170 ps
CPU time 84.62 seconds
Started Jul 03 06:21:14 PM PDT 24
Finished Jul 03 06:22:39 PM PDT 24
Peak memory 257596 kb
Host smart-4a4df2ad-0710-46ac-b6c4-e3bffad01ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35114
3110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.351143110
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2035783597
Short name T296
Test name
Test status
Simulation time 60329691205 ps
CPU time 1596.71 seconds
Started Jul 03 06:21:29 PM PDT 24
Finished Jul 03 06:48:06 PM PDT 24
Peak memory 290380 kb
Host smart-f0814a99-107f-46d1-a04f-99649e250777
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035783597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2035783597
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4021412967
Short name T195
Test name
Test status
Simulation time 52588906 ps
CPU time 2.67 seconds
Started Jul 03 06:15:57 PM PDT 24
Finished Jul 03 06:16:00 PM PDT 24
Peak memory 249500 kb
Host smart-72cf5e3f-18df-443f-bfb5-bfa8c2f3745c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4021412967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4021412967
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2070836227
Short name T6
Test name
Test status
Simulation time 191422577641 ps
CPU time 2771.84 seconds
Started Jul 03 06:15:45 PM PDT 24
Finished Jul 03 07:01:58 PM PDT 24
Peak memory 290036 kb
Host smart-51765f76-7c75-4668-976f-5b05973c4cc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070836227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2070836227
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2916582688
Short name T338
Test name
Test status
Simulation time 10419222696 ps
CPU time 32.63 seconds
Started Jul 03 06:15:56 PM PDT 24
Finished Jul 03 06:16:29 PM PDT 24
Peak memory 249384 kb
Host smart-ace509cc-898b-4740-9e53-7df8be54b83c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2916582688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2916582688
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4074672528
Short name T332
Test name
Test status
Simulation time 1589270735 ps
CPU time 127.79 seconds
Started Jul 03 06:15:47 PM PDT 24
Finished Jul 03 06:17:55 PM PDT 24
Peak memory 256992 kb
Host smart-e262593a-65f0-480e-b45b-48c0549841b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40746
72528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4074672528
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3974989667
Short name T372
Test name
Test status
Simulation time 317377398 ps
CPU time 28.85 seconds
Started Jul 03 06:15:45 PM PDT 24
Finished Jul 03 06:16:15 PM PDT 24
Peak memory 257016 kb
Host smart-c5002ad3-f814-45f1-85a0-9b6df5a665b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39749
89667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3974989667
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.196650490
Short name T319
Test name
Test status
Simulation time 76613635219 ps
CPU time 2127.87 seconds
Started Jul 03 06:15:50 PM PDT 24
Finished Jul 03 06:51:18 PM PDT 24
Peak memory 283156 kb
Host smart-d6f6d58d-7cde-4cee-a466-671235b66ff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196650490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.196650490
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2121099674
Short name T604
Test name
Test status
Simulation time 45264208068 ps
CPU time 1825.57 seconds
Started Jul 03 06:15:53 PM PDT 24
Finished Jul 03 06:46:19 PM PDT 24
Peak memory 289496 kb
Host smart-744ca907-2216-4a2f-adaa-e82e6e0643eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121099674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2121099674
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3342424150
Short name T9
Test name
Test status
Simulation time 34710168359 ps
CPU time 361.44 seconds
Started Jul 03 06:15:49 PM PDT 24
Finished Jul 03 06:21:51 PM PDT 24
Peak memory 249368 kb
Host smart-f36adb33-a684-46c5-9897-3d5df146671c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342424150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3342424150
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.271540949
Short name T619
Test name
Test status
Simulation time 873382028 ps
CPU time 59.14 seconds
Started Jul 03 06:15:42 PM PDT 24
Finished Jul 03 06:16:42 PM PDT 24
Peak memory 256556 kb
Host smart-de73adab-08d3-44aa-bf81-a92a654cfea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27154
0949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.271540949
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3976570987
Short name T702
Test name
Test status
Simulation time 983211790 ps
CPU time 23.92 seconds
Started Jul 03 06:15:46 PM PDT 24
Finished Jul 03 06:16:10 PM PDT 24
Peak memory 248820 kb
Host smart-0d6c4932-b823-4ee8-ac42-954d5b153923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
70987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3976570987
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2213927264
Short name T14
Test name
Test status
Simulation time 674985203 ps
CPU time 30.49 seconds
Started Jul 03 06:15:56 PM PDT 24
Finished Jul 03 06:16:27 PM PDT 24
Peak memory 271204 kb
Host smart-7026bdca-530d-4199-a6ab-4ad2c019d524
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2213927264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2213927264
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1471448486
Short name T328
Test name
Test status
Simulation time 506418072 ps
CPU time 18.39 seconds
Started Jul 03 06:15:43 PM PDT 24
Finished Jul 03 06:16:02 PM PDT 24
Peak memory 256360 kb
Host smart-b4df9ebc-1e53-46e0-b56b-965399ebc36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
48486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1471448486
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2253554365
Short name T683
Test name
Test status
Simulation time 24759805317 ps
CPU time 2510.51 seconds
Started Jul 03 06:15:55 PM PDT 24
Finished Jul 03 06:57:46 PM PDT 24
Peak memory 305536 kb
Host smart-650bbda6-2cc8-46db-870f-3cea01594ed5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253554365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2253554365
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1890736978
Short name T83
Test name
Test status
Simulation time 52704885207 ps
CPU time 3647.41 seconds
Started Jul 03 06:15:56 PM PDT 24
Finished Jul 03 07:16:44 PM PDT 24
Peak memory 298676 kb
Host smart-4334c97f-621c-4a74-adb7-c88a8f35c1cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890736978 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1890736978
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4143352704
Short name T497
Test name
Test status
Simulation time 86959959698 ps
CPU time 1482.52 seconds
Started Jul 03 06:21:35 PM PDT 24
Finished Jul 03 06:46:18 PM PDT 24
Peak memory 289796 kb
Host smart-6801c79c-62b7-4f87-8e87-aa7cff1307a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143352704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4143352704
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3388548806
Short name T474
Test name
Test status
Simulation time 8045796610 ps
CPU time 176.26 seconds
Started Jul 03 06:21:35 PM PDT 24
Finished Jul 03 06:24:31 PM PDT 24
Peak memory 257492 kb
Host smart-fec58ee8-cd25-4436-ae82-a1a49ea3bb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33885
48806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3388548806
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3563253567
Short name T433
Test name
Test status
Simulation time 405387080 ps
CPU time 18.55 seconds
Started Jul 03 06:21:32 PM PDT 24
Finished Jul 03 06:21:51 PM PDT 24
Peak memory 248680 kb
Host smart-b636e7b9-90a9-4ee4-afc7-54850f261bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35632
53567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3563253567
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1878582723
Short name T311
Test name
Test status
Simulation time 39099957722 ps
CPU time 1206.85 seconds
Started Jul 03 06:21:39 PM PDT 24
Finished Jul 03 06:41:46 PM PDT 24
Peak memory 273992 kb
Host smart-1a017b28-6425-45a0-93be-e8168b9de900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878582723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1878582723
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1319002295
Short name T701
Test name
Test status
Simulation time 36465428982 ps
CPU time 1092.77 seconds
Started Jul 03 06:21:38 PM PDT 24
Finished Jul 03 06:39:51 PM PDT 24
Peak memory 266032 kb
Host smart-147ac661-17d4-4d32-adc2-35262ad6425b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319002295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1319002295
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.313401024
Short name T263
Test name
Test status
Simulation time 8687871398 ps
CPU time 90.63 seconds
Started Jul 03 06:21:37 PM PDT 24
Finished Jul 03 06:23:08 PM PDT 24
Peak memory 249428 kb
Host smart-23ab90d5-957e-47ff-8ab8-b25b67deb22b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313401024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.313401024
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1616515121
Short name T661
Test name
Test status
Simulation time 274749191 ps
CPU time 24.63 seconds
Started Jul 03 06:21:32 PM PDT 24
Finished Jul 03 06:21:57 PM PDT 24
Peak memory 256688 kb
Host smart-d687826d-5b5c-44b4-913c-a22ebfb6b968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16165
15121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1616515121
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2237245895
Short name T44
Test name
Test status
Simulation time 1773259493 ps
CPU time 33.66 seconds
Started Jul 03 06:21:34 PM PDT 24
Finished Jul 03 06:22:08 PM PDT 24
Peak memory 255824 kb
Host smart-ac324f30-24b9-4316-8247-12a6324c561a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22372
45895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2237245895
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4044520286
Short name T563
Test name
Test status
Simulation time 1043367552 ps
CPU time 34.57 seconds
Started Jul 03 06:21:34 PM PDT 24
Finished Jul 03 06:22:09 PM PDT 24
Peak memory 249288 kb
Host smart-b980cc8b-499c-4169-b655-abf0d6c8374f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40445
20286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4044520286
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.396908270
Short name T517
Test name
Test status
Simulation time 114315948386 ps
CPU time 2103.96 seconds
Started Jul 03 06:21:39 PM PDT 24
Finished Jul 03 06:56:44 PM PDT 24
Peak memory 289488 kb
Host smart-4a0fb440-4b77-4ae5-b35a-7012c689a477
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396908270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.396908270
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.661606146
Short name T48
Test name
Test status
Simulation time 401218254651 ps
CPU time 3729.99 seconds
Started Jul 03 06:21:39 PM PDT 24
Finished Jul 03 07:23:49 PM PDT 24
Peak memory 306636 kb
Host smart-1e2fd1c9-249d-48f8-920c-514399570e9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661606146 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.661606146
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.868743865
Short name T645
Test name
Test status
Simulation time 33850470469 ps
CPU time 1521.46 seconds
Started Jul 03 06:21:51 PM PDT 24
Finished Jul 03 06:47:13 PM PDT 24
Peak memory 290084 kb
Host smart-0a4a0bdf-662c-47ee-9e70-a51bae9b5abf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868743865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.868743865
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.668595234
Short name T337
Test name
Test status
Simulation time 1210483482 ps
CPU time 108.25 seconds
Started Jul 03 06:21:51 PM PDT 24
Finished Jul 03 06:23:39 PM PDT 24
Peak memory 256652 kb
Host smart-1bde5f07-1093-4e60-89b7-ba25f5d55f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66859
5234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.668595234
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3906715440
Short name T25
Test name
Test status
Simulation time 173017805 ps
CPU time 22.64 seconds
Started Jul 03 06:21:48 PM PDT 24
Finished Jul 03 06:22:11 PM PDT 24
Peak memory 256992 kb
Host smart-5e23091b-805f-4d94-80c8-0e7b48046a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
15440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3906715440
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.674938565
Short name T248
Test name
Test status
Simulation time 79050890357 ps
CPU time 1260.36 seconds
Started Jul 03 06:21:51 PM PDT 24
Finished Jul 03 06:42:51 PM PDT 24
Peak memory 273424 kb
Host smart-807cc2cb-e8a2-4a61-ae54-db34a1b6a3f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674938565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.674938565
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1928775785
Short name T583
Test name
Test status
Simulation time 35037869079 ps
CPU time 2430.87 seconds
Started Jul 03 06:21:49 PM PDT 24
Finished Jul 03 07:02:21 PM PDT 24
Peak memory 289500 kb
Host smart-fbdca236-00b4-489c-9640-e4b8983b1187
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928775785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1928775785
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4127306124
Short name T600
Test name
Test status
Simulation time 15833227224 ps
CPU time 164.31 seconds
Started Jul 03 06:21:47 PM PDT 24
Finished Jul 03 06:24:31 PM PDT 24
Peak memory 249384 kb
Host smart-866e3c0f-7a96-464b-9390-ebc6efed57a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127306124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4127306124
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.4173928888
Short name T199
Test name
Test status
Simulation time 1660282768 ps
CPU time 49.01 seconds
Started Jul 03 06:21:51 PM PDT 24
Finished Jul 03 06:22:40 PM PDT 24
Peak memory 256756 kb
Host smart-45dc53ac-7017-43d9-b65e-e2ef1c9e3eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41739
28888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.4173928888
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2619161764
Short name T107
Test name
Test status
Simulation time 593826339 ps
CPU time 45.4 seconds
Started Jul 03 06:21:48 PM PDT 24
Finished Jul 03 06:22:34 PM PDT 24
Peak memory 249024 kb
Host smart-8ef33c52-e9ea-4e26-980b-54950702d298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26191
61764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2619161764
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2028410293
Short name T106
Test name
Test status
Simulation time 407779867 ps
CPU time 40.5 seconds
Started Jul 03 06:21:46 PM PDT 24
Finished Jul 03 06:22:27 PM PDT 24
Peak memory 257448 kb
Host smart-a0f02d80-2ade-4ad2-939e-7c0562828cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20284
10293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2028410293
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.238789946
Short name T559
Test name
Test status
Simulation time 381681147 ps
CPU time 14.91 seconds
Started Jul 03 06:21:51 PM PDT 24
Finished Jul 03 06:22:06 PM PDT 24
Peak memory 249180 kb
Host smart-7e95dc00-33e7-4530-8fff-bcae9b301887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
9946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.238789946
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.657919577
Short name T438
Test name
Test status
Simulation time 34902564616 ps
CPU time 2125.81 seconds
Started Jul 03 06:22:05 PM PDT 24
Finished Jul 03 06:57:31 PM PDT 24
Peak memory 282096 kb
Host smart-8d30e471-df28-468e-8c7e-ad49af55ef21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657919577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.657919577
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2022059450
Short name T631
Test name
Test status
Simulation time 1570297992 ps
CPU time 60.33 seconds
Started Jul 03 06:22:01 PM PDT 24
Finished Jul 03 06:23:02 PM PDT 24
Peak memory 256856 kb
Host smart-e1a16288-fc1f-440f-a1e9-fbbf7d756170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20220
59450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2022059450
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1703405495
Short name T364
Test name
Test status
Simulation time 1601942192 ps
CPU time 35.36 seconds
Started Jul 03 06:22:00 PM PDT 24
Finished Jul 03 06:22:36 PM PDT 24
Peak memory 249264 kb
Host smart-a5d414cb-6d8b-4e79-bd50-95b39b38649c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
05495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1703405495
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3295520754
Short name T603
Test name
Test status
Simulation time 41430218802 ps
CPU time 2530.15 seconds
Started Jul 03 06:22:05 PM PDT 24
Finished Jul 03 07:04:16 PM PDT 24
Peak memory 289476 kb
Host smart-ecde3cf1-44ce-4eba-99c3-9f079f91b9a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295520754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3295520754
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2292570635
Short name T40
Test name
Test status
Simulation time 36066863365 ps
CPU time 806.67 seconds
Started Jul 03 06:22:03 PM PDT 24
Finished Jul 03 06:35:30 PM PDT 24
Peak memory 273988 kb
Host smart-603ca2e4-61bd-4af8-a85d-f325d3c71c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292570635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2292570635
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3102113594
Short name T629
Test name
Test status
Simulation time 8464180143 ps
CPU time 350.58 seconds
Started Jul 03 06:22:05 PM PDT 24
Finished Jul 03 06:27:56 PM PDT 24
Peak memory 249364 kb
Host smart-a56a576a-b772-4028-87e0-288d40a6943d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102113594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3102113594
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4277177653
Short name T660
Test name
Test status
Simulation time 265612862 ps
CPU time 21.89 seconds
Started Jul 03 06:22:01 PM PDT 24
Finished Jul 03 06:22:24 PM PDT 24
Peak memory 257360 kb
Host smart-089edd28-d147-41b7-8ecb-a54219292768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42771
77653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4277177653
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.479028755
Short name T551
Test name
Test status
Simulation time 3777234895 ps
CPU time 57.71 seconds
Started Jul 03 06:22:01 PM PDT 24
Finished Jul 03 06:22:59 PM PDT 24
Peak memory 257580 kb
Host smart-511826a5-d7ca-4b9c-84d9-796ef3e08b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47902
8755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.479028755
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.942008708
Short name T354
Test name
Test status
Simulation time 577461724 ps
CPU time 14.87 seconds
Started Jul 03 06:22:04 PM PDT 24
Finished Jul 03 06:22:19 PM PDT 24
Peak memory 256768 kb
Host smart-ea1c303d-ecba-424d-9d27-3a945761b2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94200
8708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.942008708
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2061431983
Short name T564
Test name
Test status
Simulation time 5843858741 ps
CPU time 30.15 seconds
Started Jul 03 06:22:01 PM PDT 24
Finished Jul 03 06:22:31 PM PDT 24
Peak memory 257244 kb
Host smart-86369c28-7566-4c3f-a683-237dab52e83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20614
31983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2061431983
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2251630637
Short name T42
Test name
Test status
Simulation time 145416715052 ps
CPU time 2581.64 seconds
Started Jul 03 06:22:05 PM PDT 24
Finished Jul 03 07:05:07 PM PDT 24
Peak memory 289940 kb
Host smart-539ad94d-5132-49b3-aec7-ea295e528380
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251630637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2251630637
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.582702227
Short name T206
Test name
Test status
Simulation time 30955480768 ps
CPU time 1835.13 seconds
Started Jul 03 06:22:13 PM PDT 24
Finished Jul 03 06:52:49 PM PDT 24
Peak memory 273796 kb
Host smart-b48aa8a4-7121-4e16-b3aa-db5c53bd0c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582702227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.582702227
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.663280176
Short name T550
Test name
Test status
Simulation time 7032560643 ps
CPU time 108.8 seconds
Started Jul 03 06:22:13 PM PDT 24
Finished Jul 03 06:24:02 PM PDT 24
Peak memory 257620 kb
Host smart-13cb0825-7e80-4c76-8923-e042a7fd25e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66328
0176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.663280176
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3297136245
Short name T365
Test name
Test status
Simulation time 3455899679 ps
CPU time 59.98 seconds
Started Jul 03 06:22:13 PM PDT 24
Finished Jul 03 06:23:13 PM PDT 24
Peak memory 249284 kb
Host smart-abc80df9-1d7f-4a9c-a8cf-4e64989ba703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32971
36245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3297136245
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.393017047
Short name T310
Test name
Test status
Simulation time 146504566140 ps
CPU time 1492.33 seconds
Started Jul 03 06:22:15 PM PDT 24
Finished Jul 03 06:47:08 PM PDT 24
Peak memory 274020 kb
Host smart-9913d1d3-433b-4eb4-bac6-075cd989d6b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393017047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.393017047
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.806593977
Short name T412
Test name
Test status
Simulation time 134531967965 ps
CPU time 2357.15 seconds
Started Jul 03 06:22:19 PM PDT 24
Finished Jul 03 07:01:36 PM PDT 24
Peak memory 286384 kb
Host smart-4a91f6d7-f348-44e2-add5-e4077bee316e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806593977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.806593977
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.4189780646
Short name T269
Test name
Test status
Simulation time 16960625062 ps
CPU time 357.08 seconds
Started Jul 03 06:22:15 PM PDT 24
Finished Jul 03 06:28:13 PM PDT 24
Peak memory 249400 kb
Host smart-b767449c-102f-4e67-a07c-33811c4a885e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189780646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.4189780646
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2326053463
Short name T33
Test name
Test status
Simulation time 158012948 ps
CPU time 7.55 seconds
Started Jul 03 06:22:05 PM PDT 24
Finished Jul 03 06:22:13 PM PDT 24
Peak memory 252980 kb
Host smart-3de91072-94d6-47c8-bb72-f6d2409151f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23260
53463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2326053463
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3869730017
Short name T518
Test name
Test status
Simulation time 53951425 ps
CPU time 3.58 seconds
Started Jul 03 06:22:11 PM PDT 24
Finished Jul 03 06:22:15 PM PDT 24
Peak memory 240648 kb
Host smart-37ebbccc-7f91-432d-99cc-b1c29f4bc910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
30017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3869730017
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2278139558
Short name T404
Test name
Test status
Simulation time 740228643 ps
CPU time 42.39 seconds
Started Jul 03 06:22:12 PM PDT 24
Finished Jul 03 06:22:54 PM PDT 24
Peak memory 248960 kb
Host smart-6b1e1b24-dacd-4dad-b9a6-9c3744f66bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
39558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2278139558
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.685221405
Short name T601
Test name
Test status
Simulation time 190585604 ps
CPU time 7.05 seconds
Started Jul 03 06:22:05 PM PDT 24
Finished Jul 03 06:22:12 PM PDT 24
Peak memory 249204 kb
Host smart-3733cbea-7945-4e39-a46a-e991361df179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68522
1405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.685221405
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3860529678
Short name T641
Test name
Test status
Simulation time 128253320995 ps
CPU time 1272.62 seconds
Started Jul 03 06:22:18 PM PDT 24
Finished Jul 03 06:43:31 PM PDT 24
Peak memory 282216 kb
Host smart-147605ad-0c1f-4d43-91ff-571941e4a245
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860529678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3860529678
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3883541693
Short name T524
Test name
Test status
Simulation time 30586586973 ps
CPU time 218.26 seconds
Started Jul 03 06:22:27 PM PDT 24
Finished Jul 03 06:26:05 PM PDT 24
Peak memory 251440 kb
Host smart-37a6e9d9-b061-4c0d-b17a-08f959c4d3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38835
41693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3883541693
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3998783882
Short name T204
Test name
Test status
Simulation time 880158998 ps
CPU time 22.85 seconds
Started Jul 03 06:22:25 PM PDT 24
Finished Jul 03 06:22:48 PM PDT 24
Peak memory 249228 kb
Host smart-4e1a830d-bc8d-4dd4-84c5-a6f51dc9a5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39987
83882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3998783882
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2733843486
Short name T301
Test name
Test status
Simulation time 39428780672 ps
CPU time 895.17 seconds
Started Jul 03 06:22:31 PM PDT 24
Finished Jul 03 06:37:26 PM PDT 24
Peak memory 273832 kb
Host smart-6fe5c740-5b3a-4814-9702-7305f4794acd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733843486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2733843486
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4138897231
Short name T470
Test name
Test status
Simulation time 69621112589 ps
CPU time 1042.4 seconds
Started Jul 03 06:22:31 PM PDT 24
Finished Jul 03 06:39:53 PM PDT 24
Peak memory 273700 kb
Host smart-7cf6c892-2b02-483a-8673-d831a7827bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138897231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4138897231
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2773616744
Short name T578
Test name
Test status
Simulation time 9943384638 ps
CPU time 406.94 seconds
Started Jul 03 06:22:31 PM PDT 24
Finished Jul 03 06:29:18 PM PDT 24
Peak memory 248224 kb
Host smart-3dd9222a-32dc-400f-86b6-70603e46a291
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773616744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2773616744
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4088355563
Short name T498
Test name
Test status
Simulation time 3277726680 ps
CPU time 54.58 seconds
Started Jul 03 06:22:23 PM PDT 24
Finished Jul 03 06:23:17 PM PDT 24
Peak memory 256564 kb
Host smart-90aac021-c530-4ac1-a846-c5b8666b03f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883
55563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4088355563
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.503868904
Short name T290
Test name
Test status
Simulation time 6136194589 ps
CPU time 47.83 seconds
Started Jul 03 06:22:23 PM PDT 24
Finished Jul 03 06:23:11 PM PDT 24
Peak memory 257540 kb
Host smart-df451d1c-7448-4881-b442-5c3d3de31ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50386
8904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.503868904
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3251987760
Short name T220
Test name
Test status
Simulation time 295079574 ps
CPU time 10.2 seconds
Started Jul 03 06:22:27 PM PDT 24
Finished Jul 03 06:22:37 PM PDT 24
Peak memory 249304 kb
Host smart-9b973699-ce39-41d7-8473-57b3eea2dbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32519
87760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3251987760
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3088846567
Short name T446
Test name
Test status
Simulation time 144307276 ps
CPU time 15.6 seconds
Started Jul 03 06:22:23 PM PDT 24
Finished Jul 03 06:22:39 PM PDT 24
Peak memory 257368 kb
Host smart-862afb9a-f695-4daa-80a4-240be6280592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30888
46567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3088846567
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1670660859
Short name T480
Test name
Test status
Simulation time 12000763089 ps
CPU time 1209.2 seconds
Started Jul 03 06:22:37 PM PDT 24
Finished Jul 03 06:42:47 PM PDT 24
Peak memory 286156 kb
Host smart-233c4578-0e58-46ed-b738-af9b493f0df1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670660859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1670660859
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2977081203
Short name T535
Test name
Test status
Simulation time 269031278411 ps
CPU time 2976.38 seconds
Started Jul 03 06:22:41 PM PDT 24
Finished Jul 03 07:12:18 PM PDT 24
Peak memory 289696 kb
Host smart-9c133b8d-0fb4-45e3-9d04-9158d8931f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977081203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2977081203
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1327029985
Short name T394
Test name
Test status
Simulation time 1972994941 ps
CPU time 174.91 seconds
Started Jul 03 06:22:41 PM PDT 24
Finished Jul 03 06:25:36 PM PDT 24
Peak memory 252384 kb
Host smart-641c761b-25a6-4fb5-b551-ba0726dd5048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13270
29985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1327029985
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.51354949
Short name T649
Test name
Test status
Simulation time 580316274 ps
CPU time 26.81 seconds
Started Jul 03 06:22:43 PM PDT 24
Finished Jul 03 06:23:10 PM PDT 24
Peak memory 249588 kb
Host smart-c77fdfa9-c97d-4051-b8e1-112e928d6f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51354
949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.51354949
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.786475164
Short name T273
Test name
Test status
Simulation time 307610112617 ps
CPU time 3169.61 seconds
Started Jul 03 06:22:43 PM PDT 24
Finished Jul 03 07:15:33 PM PDT 24
Peak memory 287416 kb
Host smart-25901b45-bf48-4fdd-a00e-c0d46bfa871a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786475164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.786475164
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1895208406
Short name T414
Test name
Test status
Simulation time 114252599776 ps
CPU time 1499.99 seconds
Started Jul 03 06:22:45 PM PDT 24
Finished Jul 03 06:47:45 PM PDT 24
Peak memory 273524 kb
Host smart-682e9d8d-8758-4f0d-9c90-adf6a688ebb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895208406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1895208406
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3741144016
Short name T620
Test name
Test status
Simulation time 285488395 ps
CPU time 5.97 seconds
Started Jul 03 06:22:41 PM PDT 24
Finished Jul 03 06:22:47 PM PDT 24
Peak memory 241028 kb
Host smart-591f0097-ea47-4190-90e8-e6eb4a5238a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37411
44016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3741144016
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3174365997
Short name T379
Test name
Test status
Simulation time 252265293 ps
CPU time 16.43 seconds
Started Jul 03 06:22:40 PM PDT 24
Finished Jul 03 06:22:56 PM PDT 24
Peak memory 256148 kb
Host smart-ea69b18b-ff95-4fb1-8e68-29e196a0d01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743
65997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3174365997
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2698034690
Short name T67
Test name
Test status
Simulation time 172786215 ps
CPU time 19.46 seconds
Started Jul 03 06:22:39 PM PDT 24
Finished Jul 03 06:22:58 PM PDT 24
Peak memory 256864 kb
Host smart-287a9553-849f-4996-ba5c-1f90a9c8cb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26980
34690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2698034690
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.387889212
Short name T171
Test name
Test status
Simulation time 3069110629 ps
CPU time 35.56 seconds
Started Jul 03 06:22:43 PM PDT 24
Finished Jul 03 06:23:19 PM PDT 24
Peak memory 257492 kb
Host smart-df31097c-12a5-4f8d-845a-2a5a77e0527e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38788
9212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.387889212
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3032186655
Short name T218
Test name
Test status
Simulation time 69843273243 ps
CPU time 3995.08 seconds
Started Jul 03 06:22:45 PM PDT 24
Finished Jul 03 07:29:20 PM PDT 24
Peak memory 306196 kb
Host smart-7d5b2060-df09-4a94-beed-bb3ea5e04832
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032186655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3032186655
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2337576766
Short name T180
Test name
Test status
Simulation time 83269202125 ps
CPU time 5919.81 seconds
Started Jul 03 06:22:44 PM PDT 24
Finished Jul 03 08:01:25 PM PDT 24
Peak memory 368896 kb
Host smart-3c8db1c5-abcd-4b48-951d-ef4a3d3e1ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337576766 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2337576766
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.563644415
Short name T87
Test name
Test status
Simulation time 35739362037 ps
CPU time 1243.88 seconds
Started Jul 03 06:22:50 PM PDT 24
Finished Jul 03 06:43:35 PM PDT 24
Peak memory 289676 kb
Host smart-ab6d5a61-e92d-43f4-9660-f50083d7785f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563644415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.563644415
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2994459074
Short name T666
Test name
Test status
Simulation time 258563396 ps
CPU time 24.89 seconds
Started Jul 03 06:22:48 PM PDT 24
Finished Jul 03 06:23:13 PM PDT 24
Peak memory 257256 kb
Host smart-b7eafbaa-477b-4f6e-a4fb-023c862623f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29944
59074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2994459074
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3087377154
Short name T651
Test name
Test status
Simulation time 2053692787 ps
CPU time 40.02 seconds
Started Jul 03 06:22:49 PM PDT 24
Finished Jul 03 06:23:29 PM PDT 24
Peak memory 249280 kb
Host smart-ad58230b-0197-4eb3-b19c-b8a2150f7b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
77154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3087377154
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2575919363
Short name T493
Test name
Test status
Simulation time 14806764107 ps
CPU time 855.16 seconds
Started Jul 03 06:22:53 PM PDT 24
Finished Jul 03 06:37:08 PM PDT 24
Peak memory 273824 kb
Host smart-019eb9a6-c8c0-4b97-86be-864c23dbe707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575919363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2575919363
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2667172986
Short name T264
Test name
Test status
Simulation time 43440004824 ps
CPU time 385.25 seconds
Started Jul 03 06:22:52 PM PDT 24
Finished Jul 03 06:29:18 PM PDT 24
Peak memory 256280 kb
Host smart-e25b297b-cba3-43ce-a3fd-874a35ff5f98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667172986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2667172986
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1052814601
Short name T611
Test name
Test status
Simulation time 2605344284 ps
CPU time 34.95 seconds
Started Jul 03 06:22:43 PM PDT 24
Finished Jul 03 06:23:18 PM PDT 24
Peak memory 257216 kb
Host smart-87cd2e1b-d524-43c8-9882-6ff9b4a1c564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528
14601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1052814601
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2501324788
Short name T538
Test name
Test status
Simulation time 596429982 ps
CPU time 44.35 seconds
Started Jul 03 06:22:48 PM PDT 24
Finished Jul 03 06:23:33 PM PDT 24
Peak memory 256560 kb
Host smart-78a82f86-7bb7-4b57-9afc-59ed2eb24c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25013
24788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2501324788
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1043425428
Short name T51
Test name
Test status
Simulation time 266191296 ps
CPU time 32.11 seconds
Started Jul 03 06:22:48 PM PDT 24
Finished Jul 03 06:23:21 PM PDT 24
Peak memory 249336 kb
Host smart-c1d17f58-eb10-4594-a8bf-5f53cd828a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10434
25428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1043425428
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1404701246
Short name T610
Test name
Test status
Simulation time 255314129 ps
CPU time 16.99 seconds
Started Jul 03 06:22:45 PM PDT 24
Finished Jul 03 06:23:02 PM PDT 24
Peak memory 256656 kb
Host smart-efab04f5-04b2-45b2-bfc4-a3e3887aa6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
01246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1404701246
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3445391038
Short name T93
Test name
Test status
Simulation time 180855211793 ps
CPU time 3009.81 seconds
Started Jul 03 06:22:51 PM PDT 24
Finished Jul 03 07:13:02 PM PDT 24
Peak memory 290372 kb
Host smart-54f7d5b6-edf3-4f52-bde1-6a0bb7a35249
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445391038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3445391038
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2994170203
Short name T674
Test name
Test status
Simulation time 61936918650 ps
CPU time 1988.24 seconds
Started Jul 03 06:23:04 PM PDT 24
Finished Jul 03 06:56:12 PM PDT 24
Peak memory 285236 kb
Host smart-618fcd38-7865-4598-8b19-6571654abdbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994170203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2994170203
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3684506046
Short name T286
Test name
Test status
Simulation time 5818035436 ps
CPU time 71.83 seconds
Started Jul 03 06:23:03 PM PDT 24
Finished Jul 03 06:24:15 PM PDT 24
Peak memory 257556 kb
Host smart-cb803fb8-969b-4a9e-a7a8-f3ad6781cb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36845
06046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3684506046
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3668863999
Short name T395
Test name
Test status
Simulation time 6722342413 ps
CPU time 58.52 seconds
Started Jul 03 06:22:57 PM PDT 24
Finished Jul 03 06:23:55 PM PDT 24
Peak memory 249396 kb
Host smart-01939077-5345-4c83-b84b-d453d0c48742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36688
63999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3668863999
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2811757853
Short name T297
Test name
Test status
Simulation time 69605870242 ps
CPU time 2069.22 seconds
Started Jul 03 06:23:07 PM PDT 24
Finished Jul 03 06:57:37 PM PDT 24
Peak memory 273980 kb
Host smart-501f4600-2b5a-487e-be4f-f18fca65cde4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811757853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2811757853
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2179080583
Short name T542
Test name
Test status
Simulation time 140493190505 ps
CPU time 2119.22 seconds
Started Jul 03 06:23:06 PM PDT 24
Finished Jul 03 06:58:26 PM PDT 24
Peak memory 274020 kb
Host smart-bccc6a61-70c4-4e77-9141-047dda325beb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179080583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2179080583
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.536349063
Short name T279
Test name
Test status
Simulation time 47980827883 ps
CPU time 213.71 seconds
Started Jul 03 06:23:06 PM PDT 24
Finished Jul 03 06:26:40 PM PDT 24
Peak memory 249384 kb
Host smart-c39dcf0b-99ac-48c5-9bdf-4a46e55844f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536349063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.536349063
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.730642654
Short name T562
Test name
Test status
Simulation time 6470445515 ps
CPU time 68.73 seconds
Started Jul 03 06:22:54 PM PDT 24
Finished Jul 03 06:24:03 PM PDT 24
Peak memory 257320 kb
Host smart-e985f2ed-e534-4813-ac62-b8b64425cfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73064
2654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.730642654
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2262484731
Short name T605
Test name
Test status
Simulation time 1465887169 ps
CPU time 26.08 seconds
Started Jul 03 06:22:59 PM PDT 24
Finished Jul 03 06:23:26 PM PDT 24
Peak memory 257024 kb
Host smart-69879fc7-6b60-49b8-8aa0-0a4bd9e79988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22624
84731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2262484731
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2900791102
Short name T548
Test name
Test status
Simulation time 1780916945 ps
CPU time 31.36 seconds
Started Jul 03 06:23:03 PM PDT 24
Finished Jul 03 06:23:34 PM PDT 24
Peak memory 257224 kb
Host smart-25079a74-a77f-4c0b-bc25-c8f1d32fdfe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29007
91102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2900791102
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1059896342
Short name T506
Test name
Test status
Simulation time 1133180664 ps
CPU time 33.49 seconds
Started Jul 03 06:22:55 PM PDT 24
Finished Jul 03 06:23:28 PM PDT 24
Peak memory 256484 kb
Host smart-868978f2-e0c0-425f-b052-a0e0810ebf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10598
96342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1059896342
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.493131880
Short name T704
Test name
Test status
Simulation time 11559064036 ps
CPU time 1001.24 seconds
Started Jul 03 06:23:11 PM PDT 24
Finished Jul 03 06:39:53 PM PDT 24
Peak memory 273988 kb
Host smart-165ae8eb-8c31-4728-931b-41afcb41f61a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493131880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.493131880
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3882337481
Short name T284
Test name
Test status
Simulation time 46805691842 ps
CPU time 2486.45 seconds
Started Jul 03 06:23:11 PM PDT 24
Finished Jul 03 07:04:38 PM PDT 24
Peak memory 306820 kb
Host smart-e527b976-a702-4cd7-9486-c176a759ae09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882337481 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3882337481
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.484873307
Short name T403
Test name
Test status
Simulation time 547881052854 ps
CPU time 2777.9 seconds
Started Jul 03 06:23:17 PM PDT 24
Finished Jul 03 07:09:36 PM PDT 24
Peak memory 290372 kb
Host smart-8f37eca5-d704-4d54-a941-e8ca9ffc6fbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484873307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.484873307
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3758626992
Short name T513
Test name
Test status
Simulation time 3045152283 ps
CPU time 156.71 seconds
Started Jul 03 06:23:15 PM PDT 24
Finished Jul 03 06:25:52 PM PDT 24
Peak memory 257536 kb
Host smart-33777faf-0b17-43e2-9c54-c68e21cd4e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37586
26992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3758626992
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2342168225
Short name T205
Test name
Test status
Simulation time 722070354 ps
CPU time 13.68 seconds
Started Jul 03 06:23:14 PM PDT 24
Finished Jul 03 06:23:28 PM PDT 24
Peak memory 255932 kb
Host smart-19a3c403-dff6-4b72-98f8-41c86b011cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23421
68225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2342168225
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2634690062
Short name T85
Test name
Test status
Simulation time 17634254923 ps
CPU time 1182.24 seconds
Started Jul 03 06:23:18 PM PDT 24
Finished Jul 03 06:43:00 PM PDT 24
Peak memory 265808 kb
Host smart-c8ee36ba-8c4b-48f9-acec-55c417c37db1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634690062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2634690062
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2471021346
Short name T249
Test name
Test status
Simulation time 10662622405 ps
CPU time 350.83 seconds
Started Jul 03 06:23:17 PM PDT 24
Finished Jul 03 06:29:09 PM PDT 24
Peak memory 257272 kb
Host smart-50e013a8-cefb-4066-9ea9-1b75bec6ca31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471021346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2471021346
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.4088343099
Short name T344
Test name
Test status
Simulation time 351040667 ps
CPU time 30.58 seconds
Started Jul 03 06:23:13 PM PDT 24
Finished Jul 03 06:23:44 PM PDT 24
Peak memory 249344 kb
Host smart-bd553cb4-94b3-4fc7-97dc-b339c908554a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883
43099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4088343099
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2310023638
Short name T359
Test name
Test status
Simulation time 749206821 ps
CPU time 26.99 seconds
Started Jul 03 06:23:14 PM PDT 24
Finished Jul 03 06:23:41 PM PDT 24
Peak memory 257096 kb
Host smart-e4bf969f-8c6a-432b-ab9d-51a01aae3c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23100
23638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2310023638
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3639287595
Short name T223
Test name
Test status
Simulation time 1393240580 ps
CPU time 46.13 seconds
Started Jul 03 06:23:14 PM PDT 24
Finished Jul 03 06:24:00 PM PDT 24
Peak memory 256632 kb
Host smart-63e95869-7065-4547-b837-0643ee555116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36392
87595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3639287595
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.26229594
Short name T26
Test name
Test status
Simulation time 614037900 ps
CPU time 13.65 seconds
Started Jul 03 06:23:11 PM PDT 24
Finished Jul 03 06:23:25 PM PDT 24
Peak memory 255512 kb
Host smart-1f49d94d-6c62-4721-b7de-425349d56c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26229
594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.26229594
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2711852376
Short name T700
Test name
Test status
Simulation time 52521399212 ps
CPU time 3090.24 seconds
Started Jul 03 06:23:37 PM PDT 24
Finished Jul 03 07:15:08 PM PDT 24
Peak memory 290124 kb
Host smart-7ffe7412-51dd-4ca4-a559-e1e4c8564c0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711852376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2711852376
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3886317214
Short name T172
Test name
Test status
Simulation time 3976839438 ps
CPU time 262.58 seconds
Started Jul 03 06:23:26 PM PDT 24
Finished Jul 03 06:27:49 PM PDT 24
Peak memory 257628 kb
Host smart-a0ca8fdd-93da-4146-9ed1-bdbff4a6721d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
17214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3886317214
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2713756141
Short name T382
Test name
Test status
Simulation time 626842844 ps
CPU time 14.19 seconds
Started Jul 03 06:23:25 PM PDT 24
Finished Jul 03 06:23:40 PM PDT 24
Peak memory 249588 kb
Host smart-3dc69cdc-79c6-4ae7-8e75-1fd221e1a33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27137
56141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2713756141
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.926806840
Short name T81
Test name
Test status
Simulation time 18993931762 ps
CPU time 1540.02 seconds
Started Jul 03 06:23:33 PM PDT 24
Finished Jul 03 06:49:13 PM PDT 24
Peak memory 287796 kb
Host smart-b5d295d9-e786-45da-82be-533e67951bcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926806840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.926806840
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2137046682
Short name T281
Test name
Test status
Simulation time 27575558312 ps
CPU time 1764.09 seconds
Started Jul 03 06:23:31 PM PDT 24
Finished Jul 03 06:52:55 PM PDT 24
Peak memory 273364 kb
Host smart-6de2c705-6db2-4708-95ef-1f47ed47992f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137046682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2137046682
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2174440487
Short name T270
Test name
Test status
Simulation time 21846237324 ps
CPU time 224.5 seconds
Started Jul 03 06:23:37 PM PDT 24
Finished Jul 03 06:27:22 PM PDT 24
Peak memory 256744 kb
Host smart-9d1d9e73-bae9-4f79-bf5c-83593ce8546d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174440487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2174440487
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1746586064
Short name T376
Test name
Test status
Simulation time 2139423523 ps
CPU time 73.68 seconds
Started Jul 03 06:23:20 PM PDT 24
Finished Jul 03 06:24:34 PM PDT 24
Peak memory 249152 kb
Host smart-d4dff0d1-3b40-4f25-98a6-63cf51824ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17465
86064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1746586064
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.208676187
Short name T634
Test name
Test status
Simulation time 662331638 ps
CPU time 27.05 seconds
Started Jul 03 06:23:24 PM PDT 24
Finished Jul 03 06:23:51 PM PDT 24
Peak memory 249320 kb
Host smart-fa80de79-8ef8-4cfd-a296-b7d3a747161a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20867
6187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.208676187
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2020638749
Short name T345
Test name
Test status
Simulation time 1205487662 ps
CPU time 35.18 seconds
Started Jul 03 06:23:26 PM PDT 24
Finished Jul 03 06:24:01 PM PDT 24
Peak memory 257444 kb
Host smart-adcfef94-6b0a-4494-b42f-e4fbd66e0bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20206
38749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2020638749
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1734871542
Short name T197
Test name
Test status
Simulation time 265455326 ps
CPU time 15.28 seconds
Started Jul 03 06:23:24 PM PDT 24
Finished Jul 03 06:23:39 PM PDT 24
Peak memory 249304 kb
Host smart-cb248840-43b1-486d-8e1d-6a05d157f2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17348
71542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1734871542
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1890530550
Short name T29
Test name
Test status
Simulation time 132609822638 ps
CPU time 2079.65 seconds
Started Jul 03 06:23:34 PM PDT 24
Finished Jul 03 06:58:14 PM PDT 24
Peak memory 306188 kb
Host smart-990469c1-f604-4a06-ba6e-b30c1faadfde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890530550 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1890530550
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3072250567
Short name T191
Test name
Test status
Simulation time 50865375 ps
CPU time 2.64 seconds
Started Jul 03 06:16:03 PM PDT 24
Finished Jul 03 06:16:06 PM PDT 24
Peak memory 249560 kb
Host smart-36a6549a-8b2c-4da2-8074-85b68d3e8e53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3072250567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3072250567
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1434279364
Short name T375
Test name
Test status
Simulation time 31027507722 ps
CPU time 1457.16 seconds
Started Jul 03 06:16:03 PM PDT 24
Finished Jul 03 06:40:20 PM PDT 24
Peak memory 289660 kb
Host smart-94dafd9d-b43a-412b-8080-ea9217499838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434279364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1434279364
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.568224910
Short name T570
Test name
Test status
Simulation time 515283358 ps
CPU time 14.81 seconds
Started Jul 03 06:16:03 PM PDT 24
Finished Jul 03 06:16:18 PM PDT 24
Peak memory 249220 kb
Host smart-9d3d268a-4355-40b0-94ec-97dcc394ca1b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=568224910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.568224910
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3239861411
Short name T216
Test name
Test status
Simulation time 1395498749 ps
CPU time 130.54 seconds
Started Jul 03 06:16:01 PM PDT 24
Finished Jul 03 06:18:12 PM PDT 24
Peak memory 257428 kb
Host smart-c878313e-e417-4c08-8928-8c25a0dcdb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32398
61411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3239861411
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1878201419
Short name T342
Test name
Test status
Simulation time 389460118 ps
CPU time 19.35 seconds
Started Jul 03 06:15:58 PM PDT 24
Finished Jul 03 06:16:18 PM PDT 24
Peak memory 249908 kb
Host smart-6f20cf7a-f976-4907-9b8c-819497ec9d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18782
01419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1878201419
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3363375913
Short name T511
Test name
Test status
Simulation time 18627903609 ps
CPU time 684.25 seconds
Started Jul 03 06:16:03 PM PDT 24
Finished Jul 03 06:27:28 PM PDT 24
Peak memory 271700 kb
Host smart-859fa758-71c9-43a0-a32a-907d97d45670
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363375913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3363375913
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.90558094
Short name T84
Test name
Test status
Simulation time 21740808279 ps
CPU time 759.74 seconds
Started Jul 03 06:16:04 PM PDT 24
Finished Jul 03 06:28:44 PM PDT 24
Peak memory 273056 kb
Host smart-ef01489f-03ca-4205-aa85-6b0c3cd9961c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90558094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.90558094
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2000757326
Short name T275
Test name
Test status
Simulation time 36005067023 ps
CPU time 380.04 seconds
Started Jul 03 06:15:58 PM PDT 24
Finished Jul 03 06:22:18 PM PDT 24
Peak memory 249408 kb
Host smart-546f0731-7f53-4327-a7ad-9f13f0c8606e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000757326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2000757326
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3140964331
Short name T420
Test name
Test status
Simulation time 618003563 ps
CPU time 22.5 seconds
Started Jul 03 06:16:00 PM PDT 24
Finished Jul 03 06:16:23 PM PDT 24
Peak memory 249292 kb
Host smart-78f05093-8c72-402a-803c-20a23ff7992a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
64331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3140964331
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.4034492834
Short name T38
Test name
Test status
Simulation time 711624321 ps
CPU time 50.02 seconds
Started Jul 03 06:16:01 PM PDT 24
Finished Jul 03 06:16:51 PM PDT 24
Peak memory 256904 kb
Host smart-f56fb60f-bc70-4fd4-b9e2-28b6e227c71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40344
92834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4034492834
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.811494121
Short name T452
Test name
Test status
Simulation time 609390127 ps
CPU time 20.48 seconds
Started Jul 03 06:16:00 PM PDT 24
Finished Jul 03 06:16:21 PM PDT 24
Peak memory 257456 kb
Host smart-ad6cead4-71b4-4d88-bd68-f63af5ab6950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81149
4121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.811494121
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.110642209
Short name T457
Test name
Test status
Simulation time 27425739 ps
CPU time 3.76 seconds
Started Jul 03 06:16:00 PM PDT 24
Finished Jul 03 06:16:04 PM PDT 24
Peak memory 251544 kb
Host smart-ca83f077-6d4c-4644-950c-68af0e120861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
2209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.110642209
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3261405846
Short name T239
Test name
Test status
Simulation time 86159304564 ps
CPU time 2629.17 seconds
Started Jul 03 06:16:01 PM PDT 24
Finished Jul 03 06:59:50 PM PDT 24
Peak memory 285324 kb
Host smart-a5df848e-71ce-4fa0-8670-c4cc16b46077
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261405846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3261405846
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1790313424
Short name T182
Test name
Test status
Simulation time 55695558 ps
CPU time 3.15 seconds
Started Jul 03 06:16:10 PM PDT 24
Finished Jul 03 06:16:14 PM PDT 24
Peak memory 249548 kb
Host smart-840c2ad6-68d8-47e4-bd55-533e0b8474be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1790313424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1790313424
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.338621501
Short name T697
Test name
Test status
Simulation time 187270525552 ps
CPU time 2756.34 seconds
Started Jul 03 06:16:06 PM PDT 24
Finished Jul 03 07:02:03 PM PDT 24
Peak memory 285600 kb
Host smart-801d5410-fc88-4e47-a3d0-9fe7e959125e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338621501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.338621501
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.4014214807
Short name T488
Test name
Test status
Simulation time 338390132 ps
CPU time 13.88 seconds
Started Jul 03 06:16:10 PM PDT 24
Finished Jul 03 06:16:24 PM PDT 24
Peak memory 249300 kb
Host smart-7310fa47-e9e6-4118-a427-b329488b8bab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4014214807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.4014214807
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3845606491
Short name T361
Test name
Test status
Simulation time 508026777 ps
CPU time 32.06 seconds
Started Jul 03 06:16:08 PM PDT 24
Finished Jul 03 06:16:40 PM PDT 24
Peak memory 257024 kb
Host smart-81b54eb9-d339-4fbb-bbc3-9b295c084e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38456
06491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3845606491
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2648962906
Short name T64
Test name
Test status
Simulation time 1556747851 ps
CPU time 25.93 seconds
Started Jul 03 06:16:10 PM PDT 24
Finished Jul 03 06:16:36 PM PDT 24
Peak memory 249152 kb
Host smart-c388d069-02a2-45d6-a9f7-02f584f91fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26489
62906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2648962906
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.803206966
Short name T244
Test name
Test status
Simulation time 12156334064 ps
CPU time 1250 seconds
Started Jul 03 06:16:09 PM PDT 24
Finished Jul 03 06:36:59 PM PDT 24
Peak memory 282128 kb
Host smart-650f5277-98e1-4774-b923-49a8a4cf4d07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803206966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.803206966
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3976799291
Short name T5
Test name
Test status
Simulation time 138856021805 ps
CPU time 2353.47 seconds
Started Jul 03 06:16:10 PM PDT 24
Finished Jul 03 06:55:24 PM PDT 24
Peak memory 287312 kb
Host smart-269d7bb1-99b4-4dd7-965a-b6cbd91939a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976799291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3976799291
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1872128649
Short name T530
Test name
Test status
Simulation time 12993797608 ps
CPU time 286.63 seconds
Started Jul 03 06:16:10 PM PDT 24
Finished Jul 03 06:20:57 PM PDT 24
Peak memory 249396 kb
Host smart-57c6ec2e-acac-44cb-adfb-7cabb1533732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872128649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1872128649
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1256265074
Short name T492
Test name
Test status
Simulation time 43605134 ps
CPU time 4 seconds
Started Jul 03 06:16:07 PM PDT 24
Finished Jul 03 06:16:11 PM PDT 24
Peak memory 240996 kb
Host smart-696b7478-f8dc-4257-b877-25a80a56013a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
65074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1256265074
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1848089049
Short name T405
Test name
Test status
Simulation time 221961995 ps
CPU time 18.7 seconds
Started Jul 03 06:16:10 PM PDT 24
Finished Jul 03 06:16:29 PM PDT 24
Peak memory 248728 kb
Host smart-954619ae-3fb7-42db-8655-bd918f2ab336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
89049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1848089049
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1118974984
Short name T428
Test name
Test status
Simulation time 575615316 ps
CPU time 6.16 seconds
Started Jul 03 06:16:06 PM PDT 24
Finished Jul 03 06:16:13 PM PDT 24
Peak memory 252204 kb
Host smart-f00e32e8-8438-457c-91d3-c6c6cbc3be6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11189
74984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1118974984
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3115200478
Short name T664
Test name
Test status
Simulation time 387588553 ps
CPU time 32.08 seconds
Started Jul 03 06:16:05 PM PDT 24
Finished Jul 03 06:16:37 PM PDT 24
Peak memory 249752 kb
Host smart-c34e0a13-be53-459d-b83e-49f8dc2cb5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31152
00478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3115200478
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3802299554
Short name T450
Test name
Test status
Simulation time 9050471749 ps
CPU time 207.27 seconds
Started Jul 03 06:16:10 PM PDT 24
Finished Jul 03 06:19:38 PM PDT 24
Peak memory 257456 kb
Host smart-ac9b55d2-5678-49e4-82a5-4ac829474f58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802299554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3802299554
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2074092605
Short name T238
Test name
Test status
Simulation time 49903687254 ps
CPU time 1787.51 seconds
Started Jul 03 06:16:12 PM PDT 24
Finished Jul 03 06:46:00 PM PDT 24
Peak memory 290516 kb
Host smart-bda4e1d2-bbd4-4293-b1b5-69d23fa854e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074092605 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2074092605
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4227911226
Short name T2
Test name
Test status
Simulation time 72950392 ps
CPU time 3.27 seconds
Started Jul 03 06:16:21 PM PDT 24
Finished Jul 03 06:16:25 PM PDT 24
Peak memory 249596 kb
Host smart-b256b04a-bbe0-4654-a746-56b39a106dc0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4227911226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4227911226
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2229903238
Short name T615
Test name
Test status
Simulation time 41569453891 ps
CPU time 2488.24 seconds
Started Jul 03 06:16:17 PM PDT 24
Finished Jul 03 06:57:46 PM PDT 24
Peak memory 289252 kb
Host smart-0dfc55c8-b0f4-4043-8ea8-6357705ba770
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229903238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2229903238
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2873473473
Short name T642
Test name
Test status
Simulation time 637142888 ps
CPU time 28.71 seconds
Started Jul 03 06:16:17 PM PDT 24
Finished Jul 03 06:16:46 PM PDT 24
Peak memory 249240 kb
Host smart-ec31dd39-133c-471a-9c5f-c1823bcef9f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2873473473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2873473473
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2452997300
Short name T208
Test name
Test status
Simulation time 3013759329 ps
CPU time 73.84 seconds
Started Jul 03 06:16:22 PM PDT 24
Finished Jul 03 06:17:36 PM PDT 24
Peak memory 257064 kb
Host smart-d13332dd-04c0-44d4-b988-654570d0c386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
97300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2452997300
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1033841945
Short name T429
Test name
Test status
Simulation time 5957495019 ps
CPU time 82.41 seconds
Started Jul 03 06:16:19 PM PDT 24
Finished Jul 03 06:17:42 PM PDT 24
Peak memory 257144 kb
Host smart-976d2578-2522-4b11-b809-2f2ffd3bce1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
41945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1033841945
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2591316986
Short name T308
Test name
Test status
Simulation time 46740935116 ps
CPU time 2751.58 seconds
Started Jul 03 06:16:17 PM PDT 24
Finished Jul 03 07:02:09 PM PDT 24
Peak memory 289988 kb
Host smart-693b91b7-6403-4401-9851-c8229a370fd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591316986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2591316986
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1962830568
Short name T501
Test name
Test status
Simulation time 47628034492 ps
CPU time 1493.13 seconds
Started Jul 03 06:16:16 PM PDT 24
Finished Jul 03 06:41:10 PM PDT 24
Peak memory 273484 kb
Host smart-270d8588-e5f3-4926-aa2b-678870b03abb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962830568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1962830568
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3831694851
Short name T573
Test name
Test status
Simulation time 1511858760 ps
CPU time 64.83 seconds
Started Jul 03 06:16:18 PM PDT 24
Finished Jul 03 06:17:23 PM PDT 24
Peak memory 249276 kb
Host smart-41df9d84-f203-4baa-9358-305eb1c80f40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831694851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3831694851
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3297082342
Short name T650
Test name
Test status
Simulation time 490027782 ps
CPU time 4.62 seconds
Started Jul 03 06:16:13 PM PDT 24
Finished Jul 03 06:16:18 PM PDT 24
Peak memory 249236 kb
Host smart-0b1f4918-3167-4c7b-b5fe-335e0c570d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32970
82342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3297082342
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.425726757
Short name T445
Test name
Test status
Simulation time 621211505 ps
CPU time 30.11 seconds
Started Jul 03 06:16:14 PM PDT 24
Finished Jul 03 06:16:45 PM PDT 24
Peak memory 248664 kb
Host smart-d79b2e41-79ab-40c3-a653-581fcbcf36e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42572
6757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.425726757
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2512130778
Short name T358
Test name
Test status
Simulation time 8226749992 ps
CPU time 60.74 seconds
Started Jul 03 06:16:18 PM PDT 24
Finished Jul 03 06:17:19 PM PDT 24
Peak memory 257072 kb
Host smart-db299897-94c8-4ba0-9979-583e2eb1ed4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121
30778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2512130778
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1980913221
Short name T401
Test name
Test status
Simulation time 1986253572 ps
CPU time 34.08 seconds
Started Jul 03 06:16:14 PM PDT 24
Finished Jul 03 06:16:49 PM PDT 24
Peak memory 249204 kb
Host smart-f8e3a8ab-72bc-4536-8091-5e0b2a759a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19809
13221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1980913221
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.357389294
Short name T35
Test name
Test status
Simulation time 197417464309 ps
CPU time 2771.44 seconds
Started Jul 03 06:16:21 PM PDT 24
Finished Jul 03 07:02:33 PM PDT 24
Peak memory 290256 kb
Host smart-d9690569-44c3-4c44-99a4-500fd228c65f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357389294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.357389294
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1877349148
Short name T283
Test name
Test status
Simulation time 72587721794 ps
CPU time 4998.18 seconds
Started Jul 03 06:16:20 PM PDT 24
Finished Jul 03 07:39:39 PM PDT 24
Peak memory 306040 kb
Host smart-7250da3b-3c41-4e39-9564-0616e6568ccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877349148 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1877349148
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1071281482
Short name T185
Test name
Test status
Simulation time 202791316 ps
CPU time 2.82 seconds
Started Jul 03 06:16:27 PM PDT 24
Finished Jul 03 06:16:30 PM PDT 24
Peak memory 249532 kb
Host smart-ddc61b53-19f1-462d-b894-d5a9604cc155
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1071281482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1071281482
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.660917209
Short name T540
Test name
Test status
Simulation time 23759797239 ps
CPU time 1372.2 seconds
Started Jul 03 06:16:21 PM PDT 24
Finished Jul 03 06:39:14 PM PDT 24
Peak memory 273956 kb
Host smart-4e20c59b-a9e1-48b2-86dd-6ad22ea5783b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660917209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.660917209
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2440094916
Short name T533
Test name
Test status
Simulation time 1717823208 ps
CPU time 76.12 seconds
Started Jul 03 06:16:23 PM PDT 24
Finished Jul 03 06:17:39 PM PDT 24
Peak memory 249248 kb
Host smart-01f7321a-c61f-47a7-b5c8-ae3e13ba5139
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2440094916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2440094916
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2562753208
Short name T567
Test name
Test status
Simulation time 4619195856 ps
CPU time 71.6 seconds
Started Jul 03 06:16:21 PM PDT 24
Finished Jul 03 06:17:33 PM PDT 24
Peak memory 257112 kb
Host smart-59234221-aeca-45d5-b099-edd3c17f0641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
53208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2562753208
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3959479764
Short name T695
Test name
Test status
Simulation time 1736918337 ps
CPU time 19.9 seconds
Started Jul 03 06:16:20 PM PDT 24
Finished Jul 03 06:16:41 PM PDT 24
Peak memory 255420 kb
Host smart-40c39a52-dc89-4efa-a6a3-2f282831a060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39594
79764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3959479764
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2228011565
Short name T314
Test name
Test status
Simulation time 132680751009 ps
CPU time 1344.45 seconds
Started Jul 03 06:16:22 PM PDT 24
Finished Jul 03 06:38:47 PM PDT 24
Peak memory 273700 kb
Host smart-bf966313-2e8e-4340-8a4e-c5c4d3bd8ba9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228011565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2228011565
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1009547346
Short name T665
Test name
Test status
Simulation time 10503228033 ps
CPU time 758.39 seconds
Started Jul 03 06:16:28 PM PDT 24
Finished Jul 03 06:29:07 PM PDT 24
Peak memory 265608 kb
Host smart-4d5008dd-d694-4234-a7c3-20b4a52a85f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009547346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1009547346
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2848145738
Short name T453
Test name
Test status
Simulation time 11641866827 ps
CPU time 102.55 seconds
Started Jul 03 06:16:28 PM PDT 24
Finished Jul 03 06:18:11 PM PDT 24
Peak memory 249288 kb
Host smart-6f1bffe8-30ef-45c9-979f-c944449f0f1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848145738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2848145738
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1706013996
Short name T24
Test name
Test status
Simulation time 603980622 ps
CPU time 39.19 seconds
Started Jul 03 06:16:21 PM PDT 24
Finished Jul 03 06:17:01 PM PDT 24
Peak memory 249308 kb
Host smart-e40f729e-be8b-4821-826b-c48dfe040198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17060
13996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1706013996
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2742109198
Short name T636
Test name
Test status
Simulation time 326582661 ps
CPU time 26.4 seconds
Started Jul 03 06:16:20 PM PDT 24
Finished Jul 03 06:16:47 PM PDT 24
Peak memory 256948 kb
Host smart-7926d9f9-5a99-4eb3-b51a-b43d21746af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27421
09198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2742109198
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2047539170
Short name T656
Test name
Test status
Simulation time 1002479216 ps
CPU time 31.2 seconds
Started Jul 03 06:16:20 PM PDT 24
Finished Jul 03 06:16:52 PM PDT 24
Peak memory 256852 kb
Host smart-dc7284ce-f335-439a-8020-61bf7d2089e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
39170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2047539170
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3013507875
Short name T633
Test name
Test status
Simulation time 982230350 ps
CPU time 21.35 seconds
Started Jul 03 06:16:20 PM PDT 24
Finished Jul 03 06:16:41 PM PDT 24
Peak memory 256640 kb
Host smart-da7bb44a-cf57-4f27-aaf1-bfba905549a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30135
07875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3013507875
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3829466901
Short name T502
Test name
Test status
Simulation time 60540841098 ps
CPU time 1604.22 seconds
Started Jul 03 06:16:23 PM PDT 24
Finished Jul 03 06:43:08 PM PDT 24
Peak memory 289576 kb
Host smart-c20d64f7-bbaa-4df2-963d-29b278ee6494
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829466901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3829466901
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.373359910
Short name T41
Test name
Test status
Simulation time 50600247789 ps
CPU time 1554.06 seconds
Started Jul 03 06:16:26 PM PDT 24
Finished Jul 03 06:42:20 PM PDT 24
Peak memory 298644 kb
Host smart-b34a2654-e9ad-4712-bd39-2d8acfc53a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373359910 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.373359910
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1582727146
Short name T188
Test name
Test status
Simulation time 114588610 ps
CPU time 3.6 seconds
Started Jul 03 06:16:39 PM PDT 24
Finished Jul 03 06:16:43 PM PDT 24
Peak memory 249468 kb
Host smart-9499b967-69b8-465a-a969-86a68b25144a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1582727146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1582727146
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1346273959
Short name T368
Test name
Test status
Simulation time 111475130242 ps
CPU time 1958.25 seconds
Started Jul 03 06:16:38 PM PDT 24
Finished Jul 03 06:49:17 PM PDT 24
Peak memory 282760 kb
Host smart-d6cb7e43-1c3c-4e0a-a88c-c881cb687566
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346273959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1346273959
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2630241780
Short name T688
Test name
Test status
Simulation time 1148451151 ps
CPU time 15.7 seconds
Started Jul 03 06:16:34 PM PDT 24
Finished Jul 03 06:16:50 PM PDT 24
Peak memory 249252 kb
Host smart-d1df05a7-5cd1-4a58-8c56-d1df6f3f464c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2630241780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2630241780
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2351113770
Short name T413
Test name
Test status
Simulation time 12558145151 ps
CPU time 218.18 seconds
Started Jul 03 06:16:31 PM PDT 24
Finished Jul 03 06:20:09 PM PDT 24
Peak memory 257592 kb
Host smart-db7aebb6-79dc-4ed7-89d1-8e1b2896b23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23511
13770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2351113770
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2038120049
Short name T356
Test name
Test status
Simulation time 314375127 ps
CPU time 34.96 seconds
Started Jul 03 06:16:31 PM PDT 24
Finished Jul 03 06:17:06 PM PDT 24
Peak memory 249340 kb
Host smart-39d0a997-8cd6-444b-836b-961bc33532c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20381
20049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2038120049
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2582282614
Short name T469
Test name
Test status
Simulation time 18154752397 ps
CPU time 1012.68 seconds
Started Jul 03 06:16:34 PM PDT 24
Finished Jul 03 06:33:27 PM PDT 24
Peak memory 273036 kb
Host smart-43baf799-0d15-40b7-a4d9-68743d6c6464
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582282614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2582282614
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.343241053
Short name T532
Test name
Test status
Simulation time 8561889560 ps
CPU time 675.68 seconds
Started Jul 03 06:16:33 PM PDT 24
Finished Jul 03 06:27:49 PM PDT 24
Peak memory 273196 kb
Host smart-c2ce3b1b-9fb7-42c0-8375-f99a206f498c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343241053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.343241053
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.910426655
Short name T278
Test name
Test status
Simulation time 4903487387 ps
CPU time 210.72 seconds
Started Jul 03 06:16:36 PM PDT 24
Finished Jul 03 06:20:07 PM PDT 24
Peak memory 248220 kb
Host smart-f3079dbd-0be5-49de-bcee-ece825b1d579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910426655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.910426655
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.692364903
Short name T385
Test name
Test status
Simulation time 71116342 ps
CPU time 5.28 seconds
Started Jul 03 06:16:27 PM PDT 24
Finished Jul 03 06:16:33 PM PDT 24
Peak memory 249288 kb
Host smart-f6f1e4c4-6a37-4918-80aa-fa9a41fa44fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69236
4903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.692364903
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1042758186
Short name T692
Test name
Test status
Simulation time 176426611 ps
CPU time 20.36 seconds
Started Jul 03 06:16:27 PM PDT 24
Finished Jul 03 06:16:47 PM PDT 24
Peak memory 249236 kb
Host smart-d5dc6439-f2c5-4afe-9aa9-422c26de2b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10427
58186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1042758186
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3271789604
Short name T549
Test name
Test status
Simulation time 363333946 ps
CPU time 24.08 seconds
Started Jul 03 06:16:30 PM PDT 24
Finished Jul 03 06:16:54 PM PDT 24
Peak memory 249148 kb
Host smart-e0fe14d7-81cf-48a3-84d3-6c8781300343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32717
89604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3271789604
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.449558315
Short name T520
Test name
Test status
Simulation time 834594387 ps
CPU time 34 seconds
Started Jul 03 06:16:26 PM PDT 24
Finished Jul 03 06:17:00 PM PDT 24
Peak memory 257440 kb
Host smart-75895622-3f43-4bad-aac1-b19d25e060e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44955
8315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.449558315
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3871242786
Short name T427
Test name
Test status
Simulation time 2946242121 ps
CPU time 215.36 seconds
Started Jul 03 06:16:36 PM PDT 24
Finished Jul 03 06:20:11 PM PDT 24
Peak memory 257628 kb
Host smart-5f0c3f20-22a7-4975-b669-f06884d8ef25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871242786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3871242786
Directory /workspace/9.alert_handler_stress_all/latest
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