Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	65777	1			T4	2		T8	1		T21	607
class_i[0x1]	37824	1			T4	1		T6	2368		T19	529
class_i[0x2]	42099	1			T4	1		T5	258		T21	2
class_i[0x3]	61352	1			T4	3		T5	7		T15	92

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	51393	1			T4	1		T5	6		T6	693
alert[0x1]	52799	1			T4	3		T6	573		T19	151
alert[0x2]	52879	1			T4	2		T5	258		T6	557
alert[0x3]	49981	1			T4	1		T5	1		T6	545

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

206793

1

T4

1

T5

265

T6

2368

esc_ping_fail

259

1

T4

6

T8

1

T10

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	51315	1			T5	6		T6	693		T19	117
esc_integrity_fail	alert[0x1]	52735	1			T4	1		T6	573		T19	151
esc_integrity_fail	alert[0x2]	52816	1			T5	258		T6	557		T19	113
esc_integrity_fail	alert[0x3]	49927	1			T5	1		T6	545		T19	148
esc_ping_fail	alert[0x0]	78	1			T4	1		T10	1		T180	2
esc_ping_fail	alert[0x1]	64	1			T4	2		T8	1		T10	1
esc_ping_fail	alert[0x2]	63	1			T4	2		T10	1		T180	1
esc_ping_fail	alert[0x3]	54	1			T4	1		T180	1		T73	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	65706	1			T21	607		T15	799		T30	4
esc_integrity_fail	class_i[0x1]	37768	1			T4	1		T6	2368		T19	529
esc_integrity_fail	class_i[0x2]	42025	1			T5	258		T21	2		T15	675
esc_integrity_fail	class_i[0x3]	61294	1			T5	7		T15	92		T83	11
esc_ping_fail	class_i[0x0]	71	1			T4	2		T8	1		T180	5
esc_ping_fail	class_i[0x1]	56	1			T50	3		T71	1		T308	2
esc_ping_fail	class_i[0x2]	74	1			T4	1		T50	1		T71	1
esc_ping_fail	class_i[0x3]	58	1			T4	3		T10	3		T180	1