Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	682088530	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	682088530	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	682088530	681905001	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	682088530	681905001	0	0
tb.dut.EdnKnownO_A	0	0	682088530	681905001	0	0
tb.dut.EscPKnownO_A	0	0	682088530	681905001	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	682088530	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	682088530	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	682088530	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	682088530	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	682088530	90	0	0
tb.dut.IrqAKnownO_A	0	0	682088530	681905001	0	0
tb.dut.IrqBKnownO_A	0	0	682088530	681905001	0	0
tb.dut.IrqCKnownO_A	0	0	682088530	681905001	0	0
tb.dut.IrqDKnownO_A	0	0	682088530	681905001	0	0
tb.dut.TlAReadyKnownO_A	0	0	682088530	681905001	0	0
tb.dut.TlDValidKnownO_A	0	0	682088530	681905001	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	706943432	2417371	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	706943432	15171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	706943432	15538	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	706943432	15335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	706943432	15227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	706943432	15154	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	706943432	16681	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	706943432	16371	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	706943432	15433	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	706943432	15078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	706943432	15234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	706943432	15797	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	706943432	15177	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	706943432	15179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	706943432	16060	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	706943432	15323	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	706943432	15248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	706943432	15160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	706943432	14727	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	706943432	16422	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	706943432	15089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	706943432	15330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	706943432	14990	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	706943432	16578	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	706943432	16482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	706943432	15305	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	706943432	15411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	706943432	15380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	706943432	15139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	706943432	15153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	706943432	15294	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	706943432	16064	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	706943432	15188	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	706943432	15110	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	706943432	14980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	706943432	15014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	706943432	15271	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	706943432	16397	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	706943432	16404	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	706943432	15141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	706943432	14827	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	706943432	16254	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	706943432	14949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	706943432	15285	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	706943432	15030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	706943432	16473	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	706943432	15317	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	706943432	15074	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	706943432	16850	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	706943432	15279	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	706943432	15443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	706943432	15223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	706943432	15630	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	706943432	15452	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	706943432	16649	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	706943432	15395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	706943432	15258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	706943432	16370	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	706943432	15210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	706943432	15170	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	706943432	14655	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	706943432	15141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	706943432	15380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	706943432	15345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	706943432	16482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	706943432	16267	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	706943432	15485	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	706943432	14758	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	706943432	14835	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	706943432	15261	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	706943432	29549	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	706943432	15302	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	706943432	16202	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	706943432	16140	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	706943432	15146	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	706943432	16463	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	706943432	16278	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	706943432	14965	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	706943432	15153	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	682088530	5882	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	682088530	217853	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	682088530	329831670	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	682088530	299	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	682088530	814	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	682088530	44	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	682088530	391	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	681876412	249242609	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	682088530	908	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	682088530	891	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	682088530	874	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	682088530	855	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	682088530	1140	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	682088530	124176	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	682088530	1022	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	682088530	72	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682088530	1559	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	682088530	1289	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	681875695	681807296	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	682088530	681905001	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	682088530	392	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	682088530	157428	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	682088530	413085594	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	682088530	316	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	682088530	442	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	682088530	19	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	682088530	190	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	681876412	347732220	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	682088530	523	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	682088530	518	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	682088530	506	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	682088530	503	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	682088530	952	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	682088530	91258	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	682088530	862	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	682088530	70	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682088530	1558	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	682088530	1288	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	681875695	681807296	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	682088530	681905001	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	682088530	3751	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	682088530	179134	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	682088530	385576159	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	682088530	299	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	682088530	510	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	682088530	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	682088530	243	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	681876412	296371678	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	682088530	578	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	682088530	571	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	682088530	563	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	682088530	556	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	682088530	821	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	682088530	107437	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	682088530	734	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	682088530	64	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682088530	1608	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	682088530	1338	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	681875695	681807296	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	682088530	681905001	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	682088530	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	682088530	3903	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	682088530	203290	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	682088530	422967271	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	682088530	321	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	682088530	481	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	682088530	12	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	682088530	200	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	681876412	343738143	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	682088530	535	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	682088530	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	682088530	517	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	682088530	510	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	682088530	779	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	682088530	95484	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	682088530	716	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	682088530	49	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682088530	1635	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	682088530	1365	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	681875695	681807296	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	682088530	681905001	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	706943432	118428147	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	706943432	706282383	0	0
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