Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	72	1			T1	1		T5	1		T30	1
class_index[0x1]	70	1			T1	2		T19	5		T22	1
class_index[0x2]	64	1			T19	1		T32	1		T53	1
class_index[0x3]	49	1			T32	1		T54	1		T87	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T1	3		T5	1		T81	1
intr_timeout_cnt[1]	61	1			T19	6		T32	2		T87	2
intr_timeout_cnt[2]	25	1			T54	1		T86	2		T118	1
intr_timeout_cnt[3]	21	1			T254	1		T55	4		T91	1
intr_timeout_cnt[4]	13	1			T22	1		T61	1		T93	1
intr_timeout_cnt[5]	6	1			T52	1		T38	1		T40	1
intr_timeout_cnt[6]	6	1			T22	1		T91	1		T93	1
intr_timeout_cnt[7]	11	1			T30	1		T53	1		T55	1
intr_timeout_cnt[8]	4	1			T91	1		T40	1		T136	1
intr_timeout_cnt[9]	8	1			T54	1		T135	1		T284	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	26	1			T1	1		T5	1		T51	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T90	1		T138	1		T283	2
class_index[0x0]	intr_timeout_cnt[2]	8	1			T54	1		T285	1		T286	2
class_index[0x0]	intr_timeout_cnt[3]	5	1			T254	1		T38	1		T275	3
class_index[0x0]	intr_timeout_cnt[4]	7	1			T22	1		T40	1		T259	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T38	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T91	1		T124	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T30	1		T287	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T91	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	28	1			T1	2		T81	1		T53	1
class_index[0x1]	intr_timeout_cnt[1]	21	1			T19	5		T87	1		T88	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T86	2		T91	1		T38	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T55	1		T203	1		T288	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T289	1		T275	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T52	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T22	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T38	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T290	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T54	1		T135	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	24	1			T92	1		T97	5		T40	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T19	1		T32	1		T87	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T93	1		T138	1		T247	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T55	3		T202	1		T275	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T93	1		T291	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T105	1		T292	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T93	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	6	1			T53	1		T203	1		T285	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T40	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	6	1			T284	1		T203	2		T62	1
class_index[0x3]	intr_timeout_cnt[0]	22	1			T54	1		T87	1		T117	5
class_index[0x3]	intr_timeout_cnt[1]	8	1			T32	1		T38	1		T293	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T118	1		T120	1		T275	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T91	1		T119	1		T138	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T61	1		T294	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T40	1		T294	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T285	1		T292	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T55	1		T288	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T136	1		-	-		-	-