Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	327838	1			T1	13		T2	17		T3	1681
all_values[1]	327838	1			T1	13		T2	17		T3	1681
all_values[2]	327838	1			T1	13		T2	17		T3	1681
all_values[3]	327838	1			T1	13		T2	17		T3	1681

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652049

1

T1

29

T2

41

T3

3395

auto[1]

659303

1

T1

23

T2

27

T3

3329

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

772737

1

T1

28

T2

36

T3

3408

auto[1]

538615

1

T1

24

T2

32

T3

3316

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92351	1			T1	6		T2	3		T3	430
all_values[0]	auto[0]	auto[1]	70930	1			T1	5		T2	3		T3	429
all_values[0]	auto[1]	auto[0]	93339	1			T1	1		T2	6		T3	411
all_values[0]	auto[1]	auto[1]	71218	1			T1	1		T2	5		T3	411
all_values[1]	auto[0]	auto[0]	96696	1			T1	4		T2	7		T3	397
all_values[1]	auto[0]	auto[1]	65624	1			T1	3		T2	6		T3	397
all_values[1]	auto[1]	auto[0]	99255	1			T1	3		T2	2		T3	445
all_values[1]	auto[1]	auto[1]	66263	1			T1	3		T2	2		T3	442
all_values[2]	auto[0]	auto[0]	98060	1			T1	5		T2	6		T3	466
all_values[2]	auto[0]	auto[1]	64605	1			T1	4		T2	5		T3	434
all_values[2]	auto[1]	auto[0]	100175	1			T1	2		T2	3		T3	413
all_values[2]	auto[1]	auto[1]	64998	1			T1	2		T2	3		T3	368
all_values[3]	auto[0]	auto[0]	96190	1			T1	1		T2	6		T3	423
all_values[3]	auto[0]	auto[1]	67593	1			T1	1		T2	5		T3	419
all_values[3]	auto[1]	auto[0]	96671	1			T1	6		T2	3		T3	423
all_values[3]	auto[1]	auto[1]	67384	1			T1	5		T2	3		T3	416