Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	327838	1			T1	13		T2	17		T3	1681
all_pins[1]	327838	1			T1	13		T2	17		T3	1681
all_pins[2]	327838	1			T1	13		T2	17		T3	1681
all_pins[3]	327838	1			T1	13		T2	17		T3	1681

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1041489	1			T1	41		T2	55		T3	5087
values[0x1]	269863	1			T1	11		T2	13		T3	1637
transitions[0x0=>0x1]	180119	1			T1	8		T2	9		T3	1021
transitions[0x1=>0x0]	180371	1			T1	8		T2	9		T3	1021

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	256620	1			T1	12		T2	12		T3	1270
all_pins[0]	values[0x1]	71218	1			T1	1		T2	5		T3	411
all_pins[0]	transitions[0x0=>0x1]	70591	1			T1	1		T2	5		T3	411
all_pins[0]	transitions[0x1=>0x0]	67009	1			T1	5		T2	3		T3	416
all_pins[1]	values[0x0]	261575	1			T1	10		T2	15		T3	1239
all_pins[1]	values[0x1]	66263	1			T1	3		T2	2		T3	442
all_pins[1]	transitions[0x0=>0x1]	35881	1			T1	2		T2	1		T3	217
all_pins[1]	transitions[0x1=>0x0]	40836	1			T2	4		T3	186		T4	2
all_pins[2]	values[0x0]	262840	1			T1	11		T2	14		T3	1313
all_pins[2]	values[0x1]	64998	1			T1	2		T2	3		T3	368
all_pins[2]	transitions[0x0=>0x1]	35811	1			T1	1		T2	1		T3	164
all_pins[2]	transitions[0x1=>0x0]	37076	1			T1	2		T3	238		T4	2
all_pins[3]	values[0x0]	260454	1			T1	8		T2	14		T3	1265
all_pins[3]	values[0x1]	67384	1			T1	5		T2	3		T3	416
all_pins[3]	transitions[0x0=>0x1]	37836	1			T1	4		T2	2		T3	229
all_pins[3]	transitions[0x1=>0x0]	35450	1			T1	1		T2	2		T3	181