Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	299	1			T181	7		T182	7		T183	7
all_values[1]	299	1			T181	7		T182	7		T183	7
all_values[2]	299	1			T181	7		T182	7		T183	7
all_values[3]	299	1			T181	7		T182	7		T183	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T181

17

T182

13

T183

15

auto[1]

555

1

T181

11

T182

15

T183

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

498

1

T181

11

T182

10

T183

13

auto[1]

698

1

T181

17

T182

18

T183

15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723

1

T181

20

T182

15

T183

17

auto[1]

473

1

T181

8

T182

13

T183

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

81

1

T181

1

T336

3

T337

3

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T181

2

T183

1

T336

1

all_values[0]

auto[0]

auto[1]

auto[0]

45

1

T183

1

T336

1

T338

1

all_values[0]

auto[0]

auto[1]

auto[1]

33

1

T181

2

T182

3

T336

1

all_values[0]

auto[1]

auto[0]

auto[1]

67

1

T181

1

T182

2

T183

4

all_values[0]

auto[1]

auto[1]

auto[1]

48

1

T181

1

T182

2

T183

1

all_values[1]

auto[0]

auto[0]

auto[0]

75

1

T181

1

T182

2

T183

4

all_values[1]

auto[0]

auto[0]

auto[1]

25

1

T339

1

T340

1

T341

1

all_values[1]

auto[0]

auto[1]

auto[0]

67

1

T181

4

T182

3

T183

2

all_values[1]

auto[0]

auto[1]

auto[1]

22

1

T336

1

T342

1

T343

1

all_values[1]

auto[1]

auto[0]

auto[1]

59

1

T181

2

T182

1

T344

1

all_values[1]

auto[1]

auto[1]

auto[1]

51

1

T182

1

T183

1

T336

1

all_values[2]

auto[0]

auto[0]

auto[0]

43

1

T181

2

T182

2

T337

1

all_values[2]

auto[0]

auto[0]

auto[1]

33

1

T181

2

T183

1

T336

1

all_values[2]

auto[0]

auto[1]

auto[0]

58

1

T182

2

T183

2

T336

3

all_values[2]

auto[0]

auto[1]

auto[1]

32

1

T181

1

T183

1

T338

2

all_values[2]

auto[1]

auto[0]

auto[1]

72

1

T181

1

T182

3

T183

1

all_values[2]

auto[1]

auto[1]

auto[1]

61

1

T181

1

T183

2

T336

1

all_values[3]

auto[0]

auto[0]

auto[0]

74

1

T181

2

T183

4

T336

2

all_values[3]

auto[0]

auto[0]

auto[1]

24

1

T181

1

T182

1

T342

1

all_values[3]

auto[0]

auto[1]

auto[0]

55

1

T181

1

T182

1

T336

1

all_values[3]

auto[0]

auto[1]

auto[1]

31

1

T181

1

T182

1

T183

1

all_values[3]

auto[1]

auto[0]

auto[1]

63

1

T181

2

T182

2

T336

2

all_values[3]

auto[1]

auto[1]

auto[1]

52

1

T182

2

T183

2

T336

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal