Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	85523	1			T3	2257		T14	67		T15	512
accum_cnt_1000	208166	1			T3	2174		T5	1		T6	634
accum_cnt_100	23970	1			T3	125		T5	1		T6	33
accum_cnt_50	61592	1			T1	2		T2	14		T3	93
accum_cnt_10	160837	1			T1	31		T2	26		T3	40
accum_cnt_0	387867	1			T1	15		T2	12		T3	9

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	242643	1			T1	12		T2	13		T3	1305
class_index[0x1]	242643	1			T1	12		T2	13		T3	1305
class_index[0x2]	242643	1			T1	12		T2	13		T3	1305
class_index[0x3]	242643	1			T1	12		T2	13		T3	1305

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22944	1			T3	620		T14	67		T65	163
class_index[0x0]	accum_cnt_1000	55467	1			T3	562		T19	151		T14	585
class_index[0x0]	accum_cnt_100	6790	1			T3	29		T19	52		T45	11
class_index[0x0]	accum_cnt_50	18234	1			T2	6		T3	23		T5	18
class_index[0x0]	accum_cnt_10	39961	1			T1	11		T2	4		T3	12
class_index[0x0]	accum_cnt_0	86075	1			T1	1		T2	3		T3	2
class_index[0x1]	accum_cnt_2000	20367	1			T3	440		T47	30		T31	167
class_index[0x1]	accum_cnt_1000	49306	1			T3	402		T19	32		T15	64
class_index[0x1]	accum_cnt_100	6581	1			T3	25		T19	53		T15	18
class_index[0x1]	accum_cnt_50	11027	1			T2	4		T3	16		T19	40
class_index[0x1]	accum_cnt_10	36838	1			T1	11		T2	8		T3	4
class_index[0x1]	accum_cnt_0	110968	1			T1	1		T2	1		T3	2
class_index[0x2]	accum_cnt_2000	21816	1			T3	571		T15	235		T65	212
class_index[0x2]	accum_cnt_1000	53057	1			T3	653		T5	1		T6	634
class_index[0x2]	accum_cnt_100	5358	1			T3	38		T5	1		T6	33
class_index[0x2]	accum_cnt_50	19704	1			T1	2		T3	29		T5	18
class_index[0x2]	accum_cnt_10	42633	1			T1	9		T2	10		T3	12
class_index[0x2]	accum_cnt_0	90372	1			T1	1		T2	3		T3	2
class_index[0x3]	accum_cnt_2000	20396	1			T3	626		T15	277		T65	234
class_index[0x3]	accum_cnt_1000	50336	1			T3	557		T19	89		T9	1090
class_index[0x3]	accum_cnt_100	5241	1			T3	33		T19	15		T9	164
class_index[0x3]	accum_cnt_50	12627	1			T2	4		T3	25		T19	12
class_index[0x3]	accum_cnt_10	41405	1			T2	4		T3	12		T4	29
class_index[0x3]	accum_cnt_0	100452	1			T1	12		T2	5		T3	3