Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3587	1			T19	8		T21	11		T10	1
alert[0x1]	5692	1			T19	7		T21	1		T10	1
alert[0x2]	6559	1			T5	5		T22	192		T69	41
alert[0x3]	4907	1			T5	1		T19	7		T15	48
alert[0x4]	5499	1			T6	1		T8	1		T15	4
alert[0x5]	2517	1			T4	1		T19	5		T15	509
alert[0x6]	5308	1			T4	1		T19	7		T15	31
alert[0x7]	4067	1			T9	1		T32	26		T84	527
alert[0x8]	14585	1			T6	283		T15	81		T32	38
alert[0x9]	3588	1			T6	35		T19	98		T21	3
alert[0xa]	13012	1			T6	30		T8	1		T15	8
alert[0xb]	6464	1			T15	7		T68	4		T32	47
alert[0xc]	3432	1			T4	1		T6	241		T19	3
alert[0xd]	4104	1			T10	1		T73	1		T53	16
alert[0xe]	7828	1			T5	1		T21	33		T15	94
alert[0xf]	4914	1			T6	196		T21	5		T15	187
alert[0x10]	5660	1			T6	73		T15	89		T68	1788
alert[0x11]	4946	1			T15	24		T22	444		T32	99
alert[0x12]	8071	1			T6	2304		T21	6		T10	1
alert[0x13]	7230	1			T4	2		T6	23		T10	1
alert[0x14]	3636	1			T4	1		T15	73		T67	1
alert[0x15]	6364	1			T180	1		T83	2		T52	2
alert[0x16]	10050	1			T6	436		T19	4		T10	1
alert[0x17]	11219	1			T180	1		T32	18		T74	1778
alert[0x18]	5680	1			T4	1		T5	47		T6	11
alert[0x19]	2677	1			T19	164		T15	6		T22	5
alert[0x1a]	11134	1			T15	198		T68	39		T50	1
alert[0x1b]	5842	1			T4	1		T180	1		T83	3
alert[0x1c]	4800	1			T4	1		T6	166		T19	15
alert[0x1d]	7995	1			T4	1		T19	1		T15	16
alert[0x1e]	4178	1			T15	33		T50	1		T73	1
alert[0x1f]	5631	1			T4	1		T15	296		T67	1
alert[0x20]	4229	1			T4	1		T19	74		T8	1
alert[0x21]	4096	1			T6	127		T15	577		T32	15
alert[0x22]	8861	1			T19	16		T67	1		T22	3302
alert[0x23]	12969	1			T6	18		T81	557		T32	3069
alert[0x24]	5957	1			T4	1		T6	3		T21	2
alert[0x25]	4013	1			T180	1		T32	26		T69	22
alert[0x26]	6437	1			T6	2		T68	14		T70	1
alert[0x27]	7915	1			T5	1		T15	94		T68	134
alert[0x28]	5381	1			T15	19		T244	1		T70	1
alert[0x29]	3589	1			T15	40		T32	430		T70	1
alert[0x2a]	15166	1			T8	1		T84	16		T53	605
alert[0x2b]	7564	1			T4	1		T19	45		T21	1
alert[0x2c]	14235	1			T6	187		T21	1		T15	2
alert[0x2d]	14313	1			T6	200		T30	9		T244	1
alert[0x2e]	3723	1			T6	15		T8	1		T21	1
alert[0x2f]	6674	1			T19	6		T15	16		T10	1
alert[0x30]	4815	1			T6	23		T15	17		T48	1
alert[0x31]	2116	1			T22	4		T69	8		T84	38
alert[0x32]	5960	1			T19	6		T68	4		T244	1
alert[0x33]	7439	1			T4	1		T8	1		T68	23
alert[0x34]	5544	1			T19	42		T180	2		T81	7
alert[0x35]	1732	1			T4	1		T6	110		T19	36
alert[0x36]	5491	1			T19	10		T15	226		T68	23
alert[0x37]	7037	1			T4	1		T6	41		T19	1
alert[0x38]	4386	1			T15	64		T68	33		T22	138
alert[0x39]	10005	1			T4	1		T19	77		T10	1
alert[0x3a]	4947	1			T6	65		T8	1		T22	119
alert[0x3b]	6264	1			T22	23		T32	133		T69	237
alert[0x3c]	5510	1			T4	1		T19	13		T81	164
alert[0x3d]	12826	1			T19	2		T15	70		T244	3
alert[0x3e]	8090	1			T15	1		T68	32		T74	221
alert[0x3f]	8059	1			T6	295		T15	17		T10	1
alert[0x40]	6943	1			T19	5		T22	47		T81	206

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	112790	1			T4	1		T5	1		T6	4877
class_i[0x1]	85864	1			T4	1		T5	6		T8	2
class_i[0x2]	111255	1			T4	1		T5	48		T8	4
class_i[0x3]	123553	1			T4	16		T6	8		T19	327

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

432725

1

T5

55

T6

4885

T19

652

alert_ping_fail

737

1

T4

19

T8

7

T9

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3580	1			T19	8		T21	11		T68	2
alert_integrity_fail	alert[0x1]	5685	1			T19	7		T21	1		T68	42
alert_integrity_fail	alert[0x2]	6548	1			T5	5		T22	192		T69	41
alert_integrity_fail	alert[0x3]	4901	1			T5	1		T19	7		T15	48
alert_integrity_fail	alert[0x4]	5487	1			T6	1		T15	4		T32	44
alert_integrity_fail	alert[0x5]	2504	1			T19	5		T15	509		T244	1
alert_integrity_fail	alert[0x6]	5290	1			T19	7		T15	31		T69	68
alert_integrity_fail	alert[0x7]	4055	1			T32	26		T84	527		T54	5
alert_integrity_fail	alert[0x8]	14579	1			T6	283		T15	81		T32	38
alert_integrity_fail	alert[0x9]	3577	1			T6	35		T19	98		T21	3
alert_integrity_fail	alert[0xa]	12997	1			T6	30		T15	8		T244	7
alert_integrity_fail	alert[0xb]	6450	1			T15	7		T68	4		T32	47
alert_integrity_fail	alert[0xc]	3423	1			T6	241		T19	3		T81	54
alert_integrity_fail	alert[0xd]	4094	1			T53	16		T298	73		T263	1
alert_integrity_fail	alert[0xe]	7821	1			T5	1		T21	33		T15	94
alert_integrity_fail	alert[0xf]	4903	1			T6	196		T21	5		T15	187
alert_integrity_fail	alert[0x10]	5653	1			T6	73		T15	89		T68	1788
alert_integrity_fail	alert[0x11]	4937	1			T15	24		T22	444		T32	99
alert_integrity_fail	alert[0x12]	8058	1			T6	2304		T21	6		T22	5
alert_integrity_fail	alert[0x13]	7213	1			T6	23		T68	136		T81	4
alert_integrity_fail	alert[0x14]	3615	1			T15	73		T68	24		T81	12
alert_integrity_fail	alert[0x15]	6352	1			T83	2		T52	2		T28	159
alert_integrity_fail	alert[0x16]	10024	1			T6	436		T19	4		T68	35
alert_integrity_fail	alert[0x17]	11208	1			T32	18		T74	1778		T28	78
alert_integrity_fail	alert[0x18]	5670	1			T5	47		T6	11		T15	1
alert_integrity_fail	alert[0x19]	2663	1			T19	164		T15	6		T22	5
alert_integrity_fail	alert[0x1a]	11123	1			T15	198		T68	39		T81	869
alert_integrity_fail	alert[0x1b]	5830	1			T83	3		T69	4		T53	98
alert_integrity_fail	alert[0x1c]	4783	1			T6	166		T19	15		T68	60
alert_integrity_fail	alert[0x1d]	7984	1			T19	1		T15	16		T32	117
alert_integrity_fail	alert[0x1e]	4168	1			T15	33		T74	61		T52	2
alert_integrity_fail	alert[0x1f]	5608	1			T15	296		T52	3		T54	1
alert_integrity_fail	alert[0x20]	4220	1			T19	74		T21	1		T68	142
alert_integrity_fail	alert[0x21]	4079	1			T6	127		T15	577		T32	15
alert_integrity_fail	alert[0x22]	8849	1			T19	16		T22	3302		T244	12
alert_integrity_fail	alert[0x23]	12958	1			T6	18		T81	557		T32	3069
alert_integrity_fail	alert[0x24]	5946	1			T6	3		T21	2		T15	20
alert_integrity_fail	alert[0x25]	4005	1			T32	26		T69	22		T88	27
alert_integrity_fail	alert[0x26]	6430	1			T6	2		T68	14		T74	269
alert_integrity_fail	alert[0x27]	7905	1			T5	1		T15	94		T68	134
alert_integrity_fail	alert[0x28]	5374	1			T15	19		T244	1		T74	21
alert_integrity_fail	alert[0x29]	3579	1			T15	40		T32	430		T74	224
alert_integrity_fail	alert[0x2a]	15159	1			T84	16		T53	605		T54	3
alert_integrity_fail	alert[0x2b]	7549	1			T19	45		T21	1		T15	64
alert_integrity_fail	alert[0x2c]	14219	1			T6	187		T21	1		T15	2
alert_integrity_fail	alert[0x2d]	14300	1			T6	200		T30	9		T244	1
alert_integrity_fail	alert[0x2e]	3711	1			T6	15		T21	1		T15	4
alert_integrity_fail	alert[0x2f]	6662	1			T19	6		T15	16		T68	9
alert_integrity_fail	alert[0x30]	4806	1			T6	23		T15	17		T244	2
alert_integrity_fail	alert[0x31]	2110	1			T22	4		T69	8		T84	38
alert_integrity_fail	alert[0x32]	5945	1			T19	6		T68	4		T244	1
alert_integrity_fail	alert[0x33]	7428	1			T68	23		T81	45		T74	240
alert_integrity_fail	alert[0x34]	5528	1			T19	42		T81	7		T32	132
alert_integrity_fail	alert[0x35]	1724	1			T6	110		T19	36		T15	94
alert_integrity_fail	alert[0x36]	5485	1			T19	10		T15	226		T68	23
alert_integrity_fail	alert[0x37]	7025	1			T6	41		T19	1		T15	13
alert_integrity_fail	alert[0x38]	4372	1			T15	64		T68	33		T22	138
alert_integrity_fail	alert[0x39]	9995	1			T19	77		T68	27		T32	16
alert_integrity_fail	alert[0x3a]	4941	1			T6	65		T22	119		T81	56
alert_integrity_fail	alert[0x3b]	6256	1			T22	23		T32	133		T69	237
alert_integrity_fail	alert[0x3c]	5497	1			T19	13		T81	164		T32	218
alert_integrity_fail	alert[0x3d]	12819	1			T19	2		T15	70		T244	3
alert_integrity_fail	alert[0x3e]	8077	1			T15	1		T68	32		T74	221
alert_integrity_fail	alert[0x3f]	8051	1			T6	295		T15	17		T22	307
alert_integrity_fail	alert[0x40]	6938	1			T19	5		T22	47		T81	206
alert_ping_fail	alert[0x0]	7	1			T10	1		T264	2		T299	1
alert_ping_fail	alert[0x1]	7	1			T10	1		T123	1		T300	1
alert_ping_fail	alert[0x2]	11	1			T71	1		T300	1		T299	1
alert_ping_fail	alert[0x3]	6	1			T10	1		T50	1		T43	1
alert_ping_fail	alert[0x4]	12	1			T8	1		T70	1		T43	1
alert_ping_fail	alert[0x5]	13	1			T4	1		T48	1		T71	1
alert_ping_fail	alert[0x6]	18	1			T4	1		T180	1		T299	1
alert_ping_fail	alert[0x7]	12	1			T9	1		T123	1		T299	1
alert_ping_fail	alert[0x8]	6	1			T264	1		T301	1		T297	1
alert_ping_fail	alert[0x9]	11	1			T70	1		T73	1		T299	1
alert_ping_fail	alert[0xa]	15	1			T8	1		T302	1		T301	1
alert_ping_fail	alert[0xb]	14	1			T70	2		T73	1		T300	1
alert_ping_fail	alert[0xc]	9	1			T4	1		T264	1		T302	1
alert_ping_fail	alert[0xd]	10	1			T10	1		T73	1		T302	1
alert_ping_fail	alert[0xe]	7	1			T301	1		T303	1		T304	1
alert_ping_fail	alert[0xf]	11	1			T50	1		T301	2		T303	1
alert_ping_fail	alert[0x10]	7	1			T70	1		T123	1		T299	2
alert_ping_fail	alert[0x11]	9	1			T300	1		T301	2		T305	1
alert_ping_fail	alert[0x12]	13	1			T10	1		T180	1		T50	1
alert_ping_fail	alert[0x13]	17	1			T4	2		T10	1		T302	1
alert_ping_fail	alert[0x14]	21	1			T4	1		T67	1		T50	1
alert_ping_fail	alert[0x15]	12	1			T180	1		T300	1		T301	1
alert_ping_fail	alert[0x16]	26	1			T10	1		T71	1		T73	1
alert_ping_fail	alert[0x17]	11	1			T180	1		T302	1		T299	1
alert_ping_fail	alert[0x18]	10	1			T4	1		T73	1		T123	1
alert_ping_fail	alert[0x19]	14	1			T50	1		T306	1		T307	1
alert_ping_fail	alert[0x1a]	11	1			T50	1		T303	1		T39	1
alert_ping_fail	alert[0x1b]	12	1			T4	1		T180	1		T300	1
alert_ping_fail	alert[0x1c]	17	1			T4	1		T73	1		T123	1
alert_ping_fail	alert[0x1d]	11	1			T4	1		T10	1		T308	2
alert_ping_fail	alert[0x1e]	10	1			T50	1		T73	1		T300	1
alert_ping_fail	alert[0x1f]	23	1			T4	1		T67	1		T180	1
alert_ping_fail	alert[0x20]	9	1			T4	1		T8	1		T10	1
alert_ping_fail	alert[0x21]	17	1			T123	1		T264	1		T299	1
alert_ping_fail	alert[0x22]	12	1			T67	1		T71	1		T123	1
alert_ping_fail	alert[0x23]	11	1			T70	1		T73	1		T123	1
alert_ping_fail	alert[0x24]	11	1			T4	1		T73	1		T300	1
alert_ping_fail	alert[0x25]	8	1			T180	1		T306	1		T309	1
alert_ping_fail	alert[0x26]	7	1			T70	1		T43	1		T309	2
alert_ping_fail	alert[0x27]	10	1			T123	2		T301	1		T39	1
alert_ping_fail	alert[0x28]	7	1			T70	1		T299	1		T297	1
alert_ping_fail	alert[0x29]	10	1			T70	1		T71	1		T123	1
alert_ping_fail	alert[0x2a]	7	1			T8	1		T123	1		T306	1
alert_ping_fail	alert[0x2b]	15	1			T4	1		T10	1		T123	2
alert_ping_fail	alert[0x2c]	16	1			T50	1		T236	1		T123	1
alert_ping_fail	alert[0x2d]	13	1			T70	1		T73	1		T264	1
alert_ping_fail	alert[0x2e]	12	1			T8	1		T50	1		T70	1
alert_ping_fail	alert[0x2f]	12	1			T10	1		T48	1		T73	1
alert_ping_fail	alert[0x30]	9	1			T48	1		T236	1		T310	1
alert_ping_fail	alert[0x31]	6	1			T205	1		T306	1		T309	1
alert_ping_fail	alert[0x32]	15	1			T70	2		T264	1		T308	1
alert_ping_fail	alert[0x33]	11	1			T4	1		T8	1		T50	1
alert_ping_fail	alert[0x34]	16	1			T180	2		T301	1		T303	1
alert_ping_fail	alert[0x35]	8	1			T4	1		T180	3		T73	1
alert_ping_fail	alert[0x36]	6	1			T180	1		T310	1		T43	1
alert_ping_fail	alert[0x37]	12	1			T4	1		T180	1		T50	1
alert_ping_fail	alert[0x38]	14	1			T73	1		T264	1		T301	1
alert_ping_fail	alert[0x39]	10	1			T4	1		T10	1		T70	1
alert_ping_fail	alert[0x3a]	6	1			T8	1		T71	1		T304	1
alert_ping_fail	alert[0x3b]	8	1			T302	1		T306	1		T272	2
alert_ping_fail	alert[0x3c]	13	1			T4	1		T205	2		T43	3
alert_ping_fail	alert[0x3d]	7	1			T73	1		T300	1		T299	1
alert_ping_fail	alert[0x3e]	13	1			T306	1		T307	1		T311	1
alert_ping_fail	alert[0x3f]	8	1			T10	1		T70	1		T308	1
alert_ping_fail	alert[0x40]	5	1			T123	1		T312	1		T304	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	112605	1			T5	1		T6	4877		T19	325
alert_integrity_fail	class_i[0x1]	85682	1			T5	6		T21	28		T15	43
alert_integrity_fail	class_i[0x2]	111053	1			T5	48		T15	4008		T244	44
alert_integrity_fail	class_i[0x3]	123385	1			T6	8		T19	327		T21	27
alert_ping_fail	class_i[0x0]	185	1			T4	1		T8	1		T10	8
alert_ping_fail	class_i[0x1]	182	1			T4	1		T8	2		T10	1
alert_ping_fail	class_i[0x2]	202	1			T4	1		T8	4		T9	1
alert_ping_fail	class_i[0x3]	168	1			T4	16		T10	2		T180	9