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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.75 100.00 100.00 100.00 99.38 99.60


Total test records in report: 827
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T163 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4096252834 Jul 04 04:49:04 PM PDT 24 Jul 04 04:53:42 PM PDT 24 3769934142 ps
T768 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1505962055 Jul 04 04:48:38 PM PDT 24 Jul 04 04:49:17 PM PDT 24 515945259 ps
T769 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3213659461 Jul 04 04:48:25 PM PDT 24 Jul 04 04:48:47 PM PDT 24 570532723 ps
T770 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.324436721 Jul 04 04:48:51 PM PDT 24 Jul 04 04:48:53 PM PDT 24 43932268 ps
T169 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3756629521 Jul 04 04:48:44 PM PDT 24 Jul 04 04:54:19 PM PDT 24 2220833338 ps
T200 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3518076242 Jul 04 04:48:32 PM PDT 24 Jul 04 04:48:34 PM PDT 24 22305106 ps
T771 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1905132478 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:18 PM PDT 24 9893715 ps
T772 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2738280072 Jul 04 04:48:15 PM PDT 24 Jul 04 04:48:21 PM PDT 24 192102864 ps
T773 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1291886205 Jul 04 04:48:47 PM PDT 24 Jul 04 04:48:52 PM PDT 24 184651259 ps
T774 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3856927095 Jul 04 04:48:44 PM PDT 24 Jul 04 04:48:51 PM PDT 24 35738319 ps
T775 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3072094631 Jul 04 04:48:25 PM PDT 24 Jul 04 04:48:27 PM PDT 24 10425126 ps
T776 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1139151326 Jul 04 04:48:55 PM PDT 24 Jul 04 04:49:10 PM PDT 24 1250703608 ps
T184 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2147934340 Jul 04 04:48:53 PM PDT 24 Jul 04 04:48:57 PM PDT 24 63550260 ps
T777 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1351407700 Jul 04 04:48:47 PM PDT 24 Jul 04 04:49:12 PM PDT 24 1087428827 ps
T778 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.479546913 Jul 04 04:48:38 PM PDT 24 Jul 04 04:49:18 PM PDT 24 3507138073 ps
T779 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3951514936 Jul 04 04:48:47 PM PDT 24 Jul 04 04:48:57 PM PDT 24 1344293568 ps
T188 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.571885720 Jul 04 04:48:52 PM PDT 24 Jul 04 04:48:57 PM PDT 24 36634006 ps
T185 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.675071109 Jul 04 04:48:38 PM PDT 24 Jul 04 04:50:02 PM PDT 24 9033245236 ps
T170 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3950321683 Jul 04 04:48:24 PM PDT 24 Jul 04 04:52:04 PM PDT 24 3414773703 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2476468243 Jul 04 04:48:32 PM PDT 24 Jul 04 04:48:58 PM PDT 24 718875613 ps
T781 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2887049354 Jul 04 04:48:44 PM PDT 24 Jul 04 04:49:06 PM PDT 24 223384510 ps
T782 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.446667170 Jul 04 04:48:58 PM PDT 24 Jul 04 04:49:04 PM PDT 24 64782143 ps
T173 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.290728275 Jul 04 04:48:55 PM PDT 24 Jul 04 04:51:25 PM PDT 24 1989490330 ps
T783 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3815089522 Jul 04 04:49:10 PM PDT 24 Jul 04 04:49:12 PM PDT 24 10380819 ps
T784 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3832462200 Jul 04 04:49:01 PM PDT 24 Jul 04 04:49:03 PM PDT 24 7957477 ps
T149 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3802845303 Jul 04 04:48:17 PM PDT 24 Jul 04 05:07:10 PM PDT 24 63849772328 ps
T785 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3226831906 Jul 04 04:48:23 PM PDT 24 Jul 04 04:48:27 PM PDT 24 24688585 ps
T786 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1816709665 Jul 04 04:48:58 PM PDT 24 Jul 04 04:49:05 PM PDT 24 35926558 ps
T787 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2342788357 Jul 04 04:48:58 PM PDT 24 Jul 04 04:49:01 PM PDT 24 11786129 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.850278223 Jul 04 04:48:21 PM PDT 24 Jul 04 04:49:06 PM PDT 24 575333680 ps
T789 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1596154119 Jul 04 04:48:46 PM PDT 24 Jul 04 04:48:48 PM PDT 24 10972213 ps
T345 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3678366295 Jul 04 04:48:22 PM PDT 24 Jul 04 04:57:02 PM PDT 24 43711876410 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2187101945 Jul 04 04:48:23 PM PDT 24 Jul 04 04:48:25 PM PDT 24 27123116 ps
T791 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3508260604 Jul 04 04:48:41 PM PDT 24 Jul 04 04:48:47 PM PDT 24 31850692 ps
T174 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3360925881 Jul 04 04:48:41 PM PDT 24 Jul 04 04:58:45 PM PDT 24 4938744089 ps
T792 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2702020079 Jul 04 04:48:56 PM PDT 24 Jul 04 04:49:02 PM PDT 24 303023329 ps
T153 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3632428142 Jul 04 04:48:52 PM PDT 24 Jul 04 04:54:37 PM PDT 24 9128980517 ps
T793 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.136846559 Jul 04 04:48:18 PM PDT 24 Jul 04 04:48:30 PM PDT 24 182250862 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2779699657 Jul 04 04:48:15 PM PDT 24 Jul 04 04:57:40 PM PDT 24 16399543521 ps
T795 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.56556813 Jul 04 04:48:49 PM PDT 24 Jul 04 04:48:59 PM PDT 24 316232790 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2627428882 Jul 04 04:48:35 PM PDT 24 Jul 04 04:49:03 PM PDT 24 776905715 ps
T797 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1268325398 Jul 04 04:48:17 PM PDT 24 Jul 04 04:48:23 PM PDT 24 138613374 ps
T798 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3094914629 Jul 04 04:48:53 PM PDT 24 Jul 04 04:49:07 PM PDT 24 74357332 ps
T799 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.112613839 Jul 04 04:48:58 PM PDT 24 Jul 04 04:49:01 PM PDT 24 6491770 ps
T800 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3522257454 Jul 04 04:49:04 PM PDT 24 Jul 04 04:49:06 PM PDT 24 9210980 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3433690505 Jul 04 04:48:31 PM PDT 24 Jul 04 04:55:43 PM PDT 24 47473265547 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.841878822 Jul 04 04:48:45 PM PDT 24 Jul 04 04:57:07 PM PDT 24 7667430260 ps
T803 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3621801822 Jul 04 04:48:17 PM PDT 24 Jul 04 04:48:58 PM PDT 24 506109070 ps
T166 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.744982811 Jul 04 04:48:15 PM PDT 24 Jul 04 04:51:27 PM PDT 24 12893011969 ps
T175 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3972979312 Jul 04 04:48:12 PM PDT 24 Jul 04 04:49:50 PM PDT 24 3167028394 ps
T804 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1514842613 Jul 04 04:48:49 PM PDT 24 Jul 04 04:48:55 PM PDT 24 38313660 ps
T805 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1897773222 Jul 04 04:48:45 PM PDT 24 Jul 04 04:49:10 PM PDT 24 269573436 ps
T806 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2279356889 Jul 04 04:48:51 PM PDT 24 Jul 04 04:49:30 PM PDT 24 488335236 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.847743752 Jul 04 04:49:04 PM PDT 24 Jul 04 04:49:06 PM PDT 24 10673995 ps
T168 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.900037142 Jul 04 04:48:46 PM PDT 24 Jul 04 04:52:08 PM PDT 24 2285195332 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1781254880 Jul 04 04:48:50 PM PDT 24 Jul 04 04:48:55 PM PDT 24 196301699 ps
T809 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.211281695 Jul 04 04:48:27 PM PDT 24 Jul 04 04:48:30 PM PDT 24 25985393 ps
T810 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.372252050 Jul 04 04:49:00 PM PDT 24 Jul 04 04:49:03 PM PDT 24 9788748 ps
T176 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.234727388 Jul 04 04:48:53 PM PDT 24 Jul 04 05:04:39 PM PDT 24 57948430707 ps
T811 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2711459075 Jul 04 04:48:17 PM PDT 24 Jul 04 04:48:23 PM PDT 24 100817036 ps
T812 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2093077086 Jul 04 04:48:37 PM PDT 24 Jul 04 04:48:42 PM PDT 24 21387615 ps
T813 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3831681696 Jul 04 04:48:17 PM PDT 24 Jul 04 04:48:41 PM PDT 24 335994399 ps
T814 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3458906353 Jul 04 04:48:22 PM PDT 24 Jul 04 04:48:27 PM PDT 24 43855101 ps
T815 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1808985211 Jul 04 04:48:47 PM PDT 24 Jul 04 04:48:53 PM PDT 24 33786047 ps
T816 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2459513525 Jul 04 04:48:54 PM PDT 24 Jul 04 04:59:28 PM PDT 24 30454975916 ps
T817 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2165570285 Jul 04 04:48:52 PM PDT 24 Jul 04 04:49:44 PM PDT 24 659244816 ps
T818 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.966676936 Jul 04 04:48:49 PM PDT 24 Jul 04 04:48:51 PM PDT 24 14617073 ps
T819 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2753900326 Jul 04 04:48:59 PM PDT 24 Jul 04 04:49:01 PM PDT 24 13866394 ps
T820 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4020699645 Jul 04 04:48:49 PM PDT 24 Jul 04 04:49:00 PM PDT 24 173753507 ps
T821 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.522961409 Jul 04 04:48:52 PM PDT 24 Jul 04 04:48:53 PM PDT 24 28200052 ps
T822 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4229384221 Jul 04 04:48:27 PM PDT 24 Jul 04 04:48:40 PM PDT 24 528760089 ps
T823 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2061547170 Jul 04 04:48:53 PM PDT 24 Jul 04 04:49:19 PM PDT 24 607511659 ps
T824 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.419469615 Jul 04 04:48:16 PM PDT 24 Jul 04 04:48:21 PM PDT 24 29172024 ps
T825 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1927741251 Jul 04 04:48:58 PM PDT 24 Jul 04 04:49:00 PM PDT 24 14196646 ps
T171 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3031437034 Jul 04 04:48:59 PM PDT 24 Jul 04 04:52:23 PM PDT 24 6151717433 ps
T826 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.30060888 Jul 04 04:49:03 PM PDT 24 Jul 04 04:49:05 PM PDT 24 10252108 ps
T827 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1361540840 Jul 04 04:48:33 PM PDT 24 Jul 04 04:48:42 PM PDT 24 378565609 ps

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3338177326
Short name T19
Test name
Test status
Simulation time 88990041720 ps
CPU time 1532.39 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 05:15:22 PM PDT 24
Peak memory 282220 kb
Host smart-2e7291df-79a4-4ac4-a557-bcd07abc5a95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338177326 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3338177326
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3079470286
Short name T15
Test name
Test status
Simulation time 30602728465 ps
CPU time 2119.22 seconds
Started Jul 04 04:50:34 PM PDT 24
Finished Jul 04 05:25:54 PM PDT 24
Peak memory 290120 kb
Host smart-e6dbcd6f-9898-4005-8518-ddcade73f77b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079470286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3079470286
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.198691129
Short name T13
Test name
Test status
Simulation time 1411605096 ps
CPU time 22.39 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:49:33 PM PDT 24
Peak memory 270512 kb
Host smart-c7a931d9-c339-4519-8714-7d504a4f57d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=198691129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.198691129
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1481057911
Short name T144
Test name
Test status
Simulation time 15046976399 ps
CPU time 1143.14 seconds
Started Jul 04 04:48:33 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 265216 kb
Host smart-899a49d8-9b3b-4641-88a0-9287daca3325
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481057911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1481057911
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.455891552
Short name T7
Test name
Test status
Simulation time 258292777 ps
CPU time 13.11 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:20 PM PDT 24
Peak memory 249080 kb
Host smart-ac8caa43-8ebf-4e69-85bd-1232eb99f1ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=455891552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.455891552
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2431654628
Short name T53
Test name
Test status
Simulation time 155985246931 ps
CPU time 2036.67 seconds
Started Jul 04 04:49:22 PM PDT 24
Finished Jul 04 05:23:19 PM PDT 24
Peak memory 285984 kb
Host smart-7293c001-0e38-4559-811c-68cd4db2cf97
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431654628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2431654628
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2968659006
Short name T177
Test name
Test status
Simulation time 187958906 ps
CPU time 22.93 seconds
Started Jul 04 04:48:35 PM PDT 24
Finished Jul 04 04:48:58 PM PDT 24
Peak memory 240380 kb
Host smart-b3957e0f-7532-4b16-859f-1f1b22a3d4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2968659006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2968659006
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3701523061
Short name T32
Test name
Test status
Simulation time 30240281649 ps
CPU time 2027.86 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 05:23:34 PM PDT 24
Peak memory 289592 kb
Host smart-9778827b-00ce-4278-8e96-3b8e753b8737
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701523061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3701523061
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2817736672
Short name T102
Test name
Test status
Simulation time 31357462516 ps
CPU time 1822.42 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 05:20:12 PM PDT 24
Peak memory 305528 kb
Host smart-c927ac66-f835-45ad-be46-7263bd5ce8b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817736672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2817736672
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3492845178
Short name T67
Test name
Test status
Simulation time 42674656236 ps
CPU time 2633.1 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 05:33:50 PM PDT 24
Peak memory 283080 kb
Host smart-957bb0ac-f428-49b3-ab9e-09c5fd285c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492845178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3492845178
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4016789302
Short name T162
Test name
Test status
Simulation time 23512220007 ps
CPU time 398.9 seconds
Started Jul 04 04:48:42 PM PDT 24
Finished Jul 04 04:55:21 PM PDT 24
Peak memory 265304 kb
Host smart-8bba3bef-24ac-457e-890b-800bb29c5f24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4016789302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4016789302
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1120225838
Short name T38
Test name
Test status
Simulation time 14047724765 ps
CPU time 883.91 seconds
Started Jul 04 04:49:15 PM PDT 24
Finished Jul 04 05:03:59 PM PDT 24
Peak memory 272648 kb
Host smart-b6141637-2239-4b37-b622-03c829799b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120225838 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1120225838
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3471295263
Short name T665
Test name
Test status
Simulation time 76492806866 ps
CPU time 2256.34 seconds
Started Jul 04 04:49:47 PM PDT 24
Finished Jul 04 05:27:24 PM PDT 24
Peak memory 290036 kb
Host smart-a938c792-aaa8-4006-9838-359697d57f8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471295263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3471295263
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1575712984
Short name T157
Test name
Test status
Simulation time 8480836473 ps
CPU time 317.32 seconds
Started Jul 04 04:48:47 PM PDT 24
Finished Jul 04 04:54:05 PM PDT 24
Peak memory 265308 kb
Host smart-c65cb9c4-b27e-42fd-aebe-73c8c137e1ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1575712984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1575712984
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.278214136
Short name T128
Test name
Test status
Simulation time 3434467035 ps
CPU time 129.84 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 04:52:04 PM PDT 24
Peak memory 248180 kb
Host smart-f546f37e-4602-4b84-9d5b-ec0a1c174bf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278214136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.278214136
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3335252292
Short name T126
Test name
Test status
Simulation time 17154191944 ps
CPU time 1570.17 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 289940 kb
Host smart-335003ef-2d04-47ba-862f-84c1612be578
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335252292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3335252292
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3443533793
Short name T145
Test name
Test status
Simulation time 54751567197 ps
CPU time 992.38 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 05:04:46 PM PDT 24
Peak memory 265228 kb
Host smart-c6dc4ebb-2325-47bb-b2ea-4a34aa637312
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443533793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3443533793
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3497316733
Short name T73
Test name
Test status
Simulation time 42130617249 ps
CPU time 549.95 seconds
Started Jul 04 04:49:50 PM PDT 24
Finished Jul 04 04:59:00 PM PDT 24
Peak memory 249100 kb
Host smart-d41742fe-4255-4a1f-867c-ee5c461ece1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497316733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3497316733
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.4010373514
Short name T296
Test name
Test status
Simulation time 153210844316 ps
CPU time 2309.84 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 05:27:38 PM PDT 24
Peak memory 281816 kb
Host smart-6cdec8df-70aa-4b0c-aa6a-4da89f9d53bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010373514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.4010373514
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1894598174
Short name T181
Test name
Test status
Simulation time 12574398 ps
CPU time 1.49 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 237440 kb
Host smart-ce436ccd-a30c-49ee-90c8-0b23f9c13b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1894598174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1894598174
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.250237908
Short name T146
Test name
Test status
Simulation time 15528242074 ps
CPU time 972.6 seconds
Started Jul 04 04:48:43 PM PDT 24
Finished Jul 04 05:04:55 PM PDT 24
Peak memory 265432 kb
Host smart-9c686c42-cdd0-4308-ae09-1c7db8d4d944
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250237908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.250237908
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2996011962
Short name T54
Test name
Test status
Simulation time 132697438149 ps
CPU time 1881.12 seconds
Started Jul 04 04:50:16 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 286300 kb
Host smart-3d97b461-42db-488b-a45a-627e44ac3dde
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996011962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2996011962
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1470529229
Short name T143
Test name
Test status
Simulation time 7039702278 ps
CPU time 271.52 seconds
Started Jul 04 04:48:36 PM PDT 24
Finished Jul 04 04:53:08 PM PDT 24
Peak memory 265300 kb
Host smart-3186c399-e41e-4c22-b954-15794151721d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1470529229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1470529229
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2343437889
Short name T297
Test name
Test status
Simulation time 37970156108 ps
CPU time 2017.33 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 05:22:42 PM PDT 24
Peak memory 290556 kb
Host smart-b27022c4-afbf-4dd5-98f4-9f9d2b9a5bed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343437889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2343437889
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3674662393
Short name T323
Test name
Test status
Simulation time 171635533888 ps
CPU time 2279.57 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 05:27:04 PM PDT 24
Peak memory 286416 kb
Host smart-050c6895-552e-4f6c-bfd0-a35a4eb54162
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674662393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3674662393
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3109435616
Short name T91
Test name
Test status
Simulation time 205425885071 ps
CPU time 3435.01 seconds
Started Jul 04 04:50:17 PM PDT 24
Finished Jul 04 05:47:32 PM PDT 24
Peak memory 306416 kb
Host smart-631d47ca-7c75-473d-bd52-0f92af55c0e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109435616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3109435616
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.998328355
Short name T155
Test name
Test status
Simulation time 1558184725 ps
CPU time 219.96 seconds
Started Jul 04 04:48:34 PM PDT 24
Finished Jul 04 04:52:14 PM PDT 24
Peak memory 265200 kb
Host smart-f4db3724-1e3d-47cf-9e9a-bf9e996fab0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=998328355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.998328355
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2322633090
Short name T306
Test name
Test status
Simulation time 61483482499 ps
CPU time 614.84 seconds
Started Jul 04 04:49:21 PM PDT 24
Finished Jul 04 04:59:36 PM PDT 24
Peak memory 249120 kb
Host smart-e03289ba-4aca-4c70-9e76-7b676d70df6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322633090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2322633090
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3999634146
Short name T141
Test name
Test status
Simulation time 4612609380 ps
CPU time 335.14 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:54:36 PM PDT 24
Peak memory 268492 kb
Host smart-c18b2234-01f8-4201-9c6a-57f2305335b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999634146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3999634146
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2348488390
Short name T70
Test name
Test status
Simulation time 10290091920 ps
CPU time 411.93 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 04:56:37 PM PDT 24
Peak memory 248972 kb
Host smart-e861ece1-619c-4bd1-8a00-dc2ddbd7d449
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348488390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2348488390
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.661681636
Short name T328
Test name
Test status
Simulation time 56112905267 ps
CPU time 3033.96 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 05:40:47 PM PDT 24
Peak memory 289780 kb
Host smart-39caf734-19b2-42f6-91e5-73c1e4b49022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661681636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.661681636
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.332089014
Short name T4
Test name
Test status
Simulation time 56412242194 ps
CPU time 544.74 seconds
Started Jul 04 04:50:24 PM PDT 24
Finished Jul 04 04:59:29 PM PDT 24
Peak memory 248912 kb
Host smart-d6188df1-1001-4e6f-9e45-baa027889b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332089014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.332089014
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4096252834
Short name T163
Test name
Test status
Simulation time 3769934142 ps
CPU time 277.9 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:53:42 PM PDT 24
Peak memory 265300 kb
Host smart-0e9568b6-51b7-4bc2-8fb1-90f8eece1ce6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4096252834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4096252834
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1376201904
Short name T50
Test name
Test status
Simulation time 12195687661 ps
CPU time 267.19 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:53:29 PM PDT 24
Peak memory 249300 kb
Host smart-7830cb14-155e-4c0c-9a5a-207a0ccb83ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376201904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1376201904
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3497980631
Short name T336
Test name
Test status
Simulation time 15875659 ps
CPU time 1.42 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 04:49:05 PM PDT 24
Peak memory 236480 kb
Host smart-59033e51-06e8-42ba-9140-0530e885a6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3497980631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3497980631
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3391274139
Short name T151
Test name
Test status
Simulation time 6514644986 ps
CPU time 554.39 seconds
Started Jul 04 04:48:43 PM PDT 24
Finished Jul 04 04:57:58 PM PDT 24
Peak memory 265400 kb
Host smart-a82cf751-1111-4ac1-941e-ab429ce92710
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391274139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3391274139
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3036115405
Short name T275
Test name
Test status
Simulation time 89648036465 ps
CPU time 1425.82 seconds
Started Jul 04 04:49:37 PM PDT 24
Finished Jul 04 05:13:23 PM PDT 24
Peak memory 289868 kb
Host smart-721125a2-27be-4436-b69b-15f612448167
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036115405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3036115405
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1423084360
Short name T28
Test name
Test status
Simulation time 23738398597 ps
CPU time 1510.51 seconds
Started Jul 04 04:49:25 PM PDT 24
Finished Jul 04 05:14:36 PM PDT 24
Peak memory 273324 kb
Host smart-9ced9d9b-e792-43c4-bc7c-94d03af30d89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423084360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1423084360
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.556858754
Short name T305
Test name
Test status
Simulation time 9747698942 ps
CPU time 380.61 seconds
Started Jul 04 04:49:41 PM PDT 24
Finished Jul 04 04:56:01 PM PDT 24
Peak memory 249112 kb
Host smart-e6eca8be-3a29-4ab2-983b-6b47806b463e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556858754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.556858754
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.269592178
Short name T40
Test name
Test status
Simulation time 118260989871 ps
CPU time 1704.96 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 05:17:31 PM PDT 24
Peak memory 273892 kb
Host smart-326f6026-e70c-4719-b22d-378309a3cabe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269592178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.269592178
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2747748894
Short name T203
Test name
Test status
Simulation time 83408376205 ps
CPU time 4967.69 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 06:13:29 PM PDT 24
Peak memory 306196 kb
Host smart-e45d8074-fd90-4e27-905c-53d605cc04e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747748894 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2747748894
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.17113604
Short name T194
Test name
Test status
Simulation time 87202641 ps
CPU time 5.3 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:48:26 PM PDT 24
Peak memory 237664 kb
Host smart-b3601e45-0491-428e-a8d4-bca7b5215b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=17113604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.17113604
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2427185305
Short name T111
Test name
Test status
Simulation time 18664231422 ps
CPU time 1072.17 seconds
Started Jul 04 04:49:38 PM PDT 24
Finished Jul 04 05:07:30 PM PDT 24
Peak memory 272968 kb
Host smart-0d5be910-301c-4674-9be4-6add1a9580b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427185305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2427185305
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3439849693
Short name T304
Test name
Test status
Simulation time 12077835364 ps
CPU time 474.39 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 04:57:52 PM PDT 24
Peak memory 249340 kb
Host smart-e0a85918-150c-48e2-b36b-ca331f09f300
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439849693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3439849693
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2671470526
Short name T93
Test name
Test status
Simulation time 234926076653 ps
CPU time 2547.33 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 05:31:29 PM PDT 24
Peak memory 290292 kb
Host smart-0cd51567-b9ac-41f2-a9dc-881887cf49aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671470526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2671470526
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.413780997
Short name T69
Test name
Test status
Simulation time 37407146546 ps
CPU time 2273.7 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 05:27:05 PM PDT 24
Peak memory 281924 kb
Host smart-32eef971-617b-4eda-be30-75147afeabea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413780997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.413780997
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2239058195
Short name T147
Test name
Test status
Simulation time 7944294698 ps
CPU time 315.08 seconds
Started Jul 04 04:48:20 PM PDT 24
Finished Jul 04 04:53:36 PM PDT 24
Peak memory 266404 kb
Host smart-38f9775b-bcbc-4d65-8afd-3265493e5560
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2239058195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2239058195
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.776306013
Short name T221
Test name
Test status
Simulation time 13497231 ps
CPU time 2.88 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:01 PM PDT 24
Peak memory 249392 kb
Host smart-8347db88-0a2c-4886-8fd2-807d694e2702
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=776306013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.776306013
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3287797162
Short name T219
Test name
Test status
Simulation time 34202831 ps
CPU time 3.1 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:04 PM PDT 24
Peak memory 249444 kb
Host smart-8fe98511-0e56-4d3c-90b8-b38ac4118262
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3287797162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3287797162
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3882263762
Short name T233
Test name
Test status
Simulation time 48983869 ps
CPU time 2.5 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 249356 kb
Host smart-b0933c7d-d144-4baa-aa63-e434790ca225
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3882263762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3882263762
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1413709501
Short name T218
Test name
Test status
Simulation time 101760474 ps
CPU time 3.83 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 04:49:11 PM PDT 24
Peak memory 249476 kb
Host smart-24445a57-be2f-4ab3-b9f5-d192508bb244
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1413709501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1413709501
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1008700717
Short name T158
Test name
Test status
Simulation time 4202512190 ps
CPU time 303.13 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:54:01 PM PDT 24
Peak memory 265300 kb
Host smart-e9f0fd25-7e57-45d5-8a57-a39a8e1150b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1008700717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1008700717
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.838841604
Short name T179
Test name
Test status
Simulation time 758010828 ps
CPU time 23.72 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:39 PM PDT 24
Peak memory 248576 kb
Host smart-43f337c2-27f5-46d3-84bc-b00581f84119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=838841604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.838841604
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3768431435
Short name T292
Test name
Test status
Simulation time 44567081060 ps
CPU time 1013.52 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 05:05:55 PM PDT 24
Peak memory 282068 kb
Host smart-cd93e69b-4ddd-4797-b10a-73fc7b9070d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768431435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3768431435
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1634266528
Short name T316
Test name
Test status
Simulation time 79755783347 ps
CPU time 2601.49 seconds
Started Jul 04 04:49:20 PM PDT 24
Finished Jul 04 05:32:42 PM PDT 24
Peak memory 290180 kb
Host smart-75b5a6c0-9001-4db6-9564-5095e4654df9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634266528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1634266528
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.826679393
Short name T283
Test name
Test status
Simulation time 42372834137 ps
CPU time 2413.84 seconds
Started Jul 04 04:49:37 PM PDT 24
Finished Jul 04 05:29:51 PM PDT 24
Peak memory 289604 kb
Host smart-f408af25-1f32-4dc4-a648-a2e42c920f73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826679393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.826679393
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2098562653
Short name T131
Test name
Test status
Simulation time 61279239827 ps
CPU time 1524.41 seconds
Started Jul 04 04:50:25 PM PDT 24
Finished Jul 04 05:15:50 PM PDT 24
Peak memory 290264 kb
Host smart-871767f4-32af-4e34-86cf-f9da58be7c68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098562653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2098562653
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3972979312
Short name T175
Test name
Test status
Simulation time 3167028394 ps
CPU time 97.52 seconds
Started Jul 04 04:48:12 PM PDT 24
Finished Jul 04 04:49:50 PM PDT 24
Peak memory 267512 kb
Host smart-4027b7fd-4f6b-46b6-9620-cae33b60393d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3972979312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3972979312
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.769969952
Short name T156
Test name
Test status
Simulation time 28641081162 ps
CPU time 1077.96 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 05:06:22 PM PDT 24
Peak memory 273460 kb
Host smart-be2e6176-288b-43df-9fa6-3f92634cfa29
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769969952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.769969952
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.417304637
Short name T758
Test name
Test status
Simulation time 10952667 ps
CPU time 1.66 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:48:52 PM PDT 24
Peak memory 237444 kb
Host smart-b772ea3b-a99c-41a2-839d-58f1a6e3cd0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=417304637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.417304637
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2463348099
Short name T61
Test name
Test status
Simulation time 105303954940 ps
CPU time 4547.72 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 06:04:48 PM PDT 24
Peak memory 349720 kb
Host smart-27efd1a1-46f3-42ad-a312-a775e357fbea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463348099 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2463348099
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2722247654
Short name T318
Test name
Test status
Simulation time 35102417026 ps
CPU time 697.39 seconds
Started Jul 04 04:49:14 PM PDT 24
Finished Jul 04 05:00:52 PM PDT 24
Peak memory 273736 kb
Host smart-b3866dfc-f9fd-4b26-b7eb-f457c0ecc3d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722247654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2722247654
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4212532465
Short name T17
Test name
Test status
Simulation time 2346359448 ps
CPU time 40.55 seconds
Started Jul 04 04:49:16 PM PDT 24
Finished Jul 04 04:49:57 PM PDT 24
Peak memory 256764 kb
Host smart-ce4d6a05-a316-422f-b301-ee3e35082e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42125
32465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4212532465
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2729654641
Short name T257
Test name
Test status
Simulation time 447537687 ps
CPU time 28.23 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:37 PM PDT 24
Peak memory 256632 kb
Host smart-3e03fc72-a2c3-4255-99b9-369b1ba6fc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
54641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2729654641
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2070337223
Short name T565
Test name
Test status
Simulation time 13913309736 ps
CPU time 453.61 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:56:45 PM PDT 24
Peak memory 249216 kb
Host smart-6c3bedd8-a7b3-4e7d-8dbd-684fbf37c451
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070337223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2070337223
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1841542582
Short name T288
Test name
Test status
Simulation time 114727564193 ps
CPU time 1044.31 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 05:06:34 PM PDT 24
Peak memory 265692 kb
Host smart-68e490dd-21b2-419b-9e68-f91c24872192
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841542582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1841542582
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3131578889
Short name T287
Test name
Test status
Simulation time 70902458130 ps
CPU time 1251.24 seconds
Started Jul 04 04:49:18 PM PDT 24
Finished Jul 04 05:10:10 PM PDT 24
Peak memory 287660 kb
Host smart-5aade75c-94cb-47d3-bec6-b6ca35bb4cb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131578889 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3131578889
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2585604011
Short name T48
Test name
Test status
Simulation time 10759573503 ps
CPU time 954.78 seconds
Started Jul 04 04:49:16 PM PDT 24
Finished Jul 04 05:05:11 PM PDT 24
Peak memory 273228 kb
Host smart-62c374f8-15d4-4414-9240-dcb52f9b5b31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585604011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2585604011
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2939311401
Short name T82
Test name
Test status
Simulation time 74745140 ps
CPU time 7.5 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:14 PM PDT 24
Peak memory 248504 kb
Host smart-8b78457a-7d85-4eda-9b47-1464c64469ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29393
11401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2939311401
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.425381781
Short name T52
Test name
Test status
Simulation time 130893428648 ps
CPU time 2647.05 seconds
Started Jul 04 04:49:44 PM PDT 24
Finished Jul 04 05:33:51 PM PDT 24
Peak memory 289712 kb
Host smart-9ebd18ad-f3cb-4b0a-b6a8-166f0c945cbe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425381781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.425381781
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1237930737
Short name T276
Test name
Test status
Simulation time 1443386528 ps
CPU time 28.33 seconds
Started Jul 04 04:49:47 PM PDT 24
Finished Jul 04 04:50:15 PM PDT 24
Peak memory 256400 kb
Host smart-cb12f3c8-fc5a-4750-8fa6-2e5514c94cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12379
30737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1237930737
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3552317746
Short name T104
Test name
Test status
Simulation time 117096541866 ps
CPU time 4325.53 seconds
Started Jul 04 04:49:47 PM PDT 24
Finished Jul 04 06:01:53 PM PDT 24
Peak memory 322900 kb
Host smart-7c77e5e1-4f1f-4b21-9b77-bf289aab95b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552317746 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3552317746
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3961280024
Short name T136
Test name
Test status
Simulation time 1378046725 ps
CPU time 19.1 seconds
Started Jul 04 04:49:51 PM PDT 24
Finished Jul 04 04:50:10 PM PDT 24
Peak memory 249176 kb
Host smart-afdf7ae1-bad7-4232-b951-0da973233834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39612
80024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3961280024
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2032231361
Short name T290
Test name
Test status
Simulation time 58535249191 ps
CPU time 3203.26 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 05:43:25 PM PDT 24
Peak memory 290184 kb
Host smart-234c44ee-88b2-49ce-8a55-7250ac133158
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032231361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2032231361
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3469575696
Short name T22
Test name
Test status
Simulation time 258312915226 ps
CPU time 2228.14 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 05:26:17 PM PDT 24
Peak memory 289948 kb
Host smart-f6132eec-27ee-40db-ac9e-7dbf11852cfb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469575696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3469575696
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4279032160
Short name T190
Test name
Test status
Simulation time 212189675 ps
CPU time 4.03 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:48:52 PM PDT 24
Peak memory 237400 kb
Host smart-b8215cab-7ab9-42ad-abd4-5ecd671aac81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4279032160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4279032160
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.23821390
Short name T101
Test name
Test status
Simulation time 306836527020 ps
CPU time 2654.85 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 05:33:19 PM PDT 24
Peak memory 282012 kb
Host smart-654ce85f-1f23-44a2-b9b5-39468549249c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23821390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.23821390
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.675071109
Short name T185
Test name
Test status
Simulation time 9033245236 ps
CPU time 84.24 seconds
Started Jul 04 04:48:38 PM PDT 24
Finished Jul 04 04:50:02 PM PDT 24
Peak memory 240416 kb
Host smart-a5016e53-2901-4c61-8a50-e3d982d35856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=675071109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.675071109
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.153105324
Short name T186
Test name
Test status
Simulation time 193918609 ps
CPU time 4.57 seconds
Started Jul 04 04:48:49 PM PDT 24
Finished Jul 04 04:48:54 PM PDT 24
Peak memory 237668 kb
Host smart-6deb84dd-4840-4329-b24c-ac00ac0e45d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=153105324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.153105324
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1236234043
Short name T178
Test name
Test status
Simulation time 50962481 ps
CPU time 4.28 seconds
Started Jul 04 04:48:12 PM PDT 24
Finished Jul 04 04:48:16 PM PDT 24
Peak memory 237680 kb
Host smart-0fb5d54e-879e-4467-bdf2-12567767b88b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1236234043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1236234043
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2147934340
Short name T184
Test name
Test status
Simulation time 63550260 ps
CPU time 3.04 seconds
Started Jul 04 04:48:53 PM PDT 24
Finished Jul 04 04:48:57 PM PDT 24
Peak memory 237468 kb
Host smart-77e13c06-1b19-4af1-acc1-15880733ba8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2147934340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2147934340
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4123141858
Short name T189
Test name
Test status
Simulation time 66087498 ps
CPU time 4.92 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:22 PM PDT 24
Peak memory 237008 kb
Host smart-78658318-69fd-4984-aba0-3be0f8847d47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4123141858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4123141858
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3518076242
Short name T200
Test name
Test status
Simulation time 22305106 ps
CPU time 2.36 seconds
Started Jul 04 04:48:32 PM PDT 24
Finished Jul 04 04:48:34 PM PDT 24
Peak memory 237384 kb
Host smart-62648062-cb5a-4162-831c-e3498452891c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3518076242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3518076242
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1630140683
Short name T159
Test name
Test status
Simulation time 4198795836 ps
CPU time 226.56 seconds
Started Jul 04 04:48:56 PM PDT 24
Finished Jul 04 04:52:43 PM PDT 24
Peak memory 265260 kb
Host smart-35dd087a-ba27-4715-b01b-905751215dcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1630140683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1630140683
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1328520031
Short name T193
Test name
Test status
Simulation time 97628533 ps
CPU time 5.42 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:07 PM PDT 24
Peak memory 236496 kb
Host smart-bb740da7-6400-4cba-ba4a-59abfa739c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1328520031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1328520031
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.872207416
Short name T192
Test name
Test status
Simulation time 2419589735 ps
CPU time 83.43 seconds
Started Jul 04 04:48:26 PM PDT 24
Finished Jul 04 04:49:50 PM PDT 24
Peak memory 240408 kb
Host smart-de08510f-46f6-4b28-9be5-bda53deb64b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=872207416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.872207416
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.903455556
Short name T201
Test name
Test status
Simulation time 65052298 ps
CPU time 4.7 seconds
Started Jul 04 04:48:54 PM PDT 24
Finished Jul 04 04:48:59 PM PDT 24
Peak memory 237648 kb
Host smart-d8e72901-45ca-44d7-8c48-e2986aeb6b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=903455556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.903455556
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.571885720
Short name T188
Test name
Test status
Simulation time 36634006 ps
CPU time 3.75 seconds
Started Jul 04 04:48:52 PM PDT 24
Finished Jul 04 04:48:57 PM PDT 24
Peak memory 237440 kb
Host smart-ace87aed-c188-4a86-9fef-435fb87f1bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=571885720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.571885720
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1308566266
Short name T195
Test name
Test status
Simulation time 58128485 ps
CPU time 4.16 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:21 PM PDT 24
Peak memory 237904 kb
Host smart-9626d001-521d-4cb8-b773-f3d3a93d417f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1308566266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1308566266
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2742534872
Short name T196
Test name
Test status
Simulation time 85029014 ps
CPU time 3.25 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 04:48:27 PM PDT 24
Peak memory 238468 kb
Host smart-f0274d3e-7cff-4fbf-b8d0-2a7161e80b42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2742534872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2742534872
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2438812126
Short name T187
Test name
Test status
Simulation time 52822678 ps
CPU time 4.11 seconds
Started Jul 04 04:48:39 PM PDT 24
Finished Jul 04 04:48:44 PM PDT 24
Peak memory 237812 kb
Host smart-c8dfb8d8-d6fc-44ae-aca1-da4c0e4f0ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2438812126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2438812126
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2159450018
Short name T124
Test name
Test status
Simulation time 4745826636 ps
CPU time 273.48 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:53:46 PM PDT 24
Peak memory 257440 kb
Host smart-286bd35e-0254-4ead-8c41-cb13c1503d6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159450018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2159450018
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2647116313
Short name T25
Test name
Test status
Simulation time 600342147 ps
CPU time 33.73 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:50:26 PM PDT 24
Peak memory 256360 kb
Host smart-74e50120-3bea-40fe-927c-287d5331cbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26471
16313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2647116313
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1301440410
Short name T23
Test name
Test status
Simulation time 156413204010 ps
CPU time 2450.05 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 05:29:51 PM PDT 24
Peak memory 282096 kb
Host smart-ddb986a8-f88f-4b3e-80cf-114bd59e9a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301440410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1301440410
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.309175973
Short name T215
Test name
Test status
Simulation time 13141055373 ps
CPU time 280.98 seconds
Started Jul 04 04:48:22 PM PDT 24
Finished Jul 04 04:53:04 PM PDT 24
Peak memory 241352 kb
Host smart-95d570f4-b4ba-48b7-b839-883a94ea4bc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=309175973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.309175973
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3181000647
Short name T216
Test name
Test status
Simulation time 11410532623 ps
CPU time 419.77 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:55:15 PM PDT 24
Peak memory 237496 kb
Host smart-12b7715f-f2b5-4caf-83bd-2a553e9de61e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3181000647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3181000647
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1145719334
Short name T755
Test name
Test status
Simulation time 270770047 ps
CPU time 4.68 seconds
Started Jul 04 04:48:36 PM PDT 24
Finished Jul 04 04:48:41 PM PDT 24
Peak memory 240344 kb
Host smart-b23b94cf-58cd-46eb-9d09-68feac201b1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1145719334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1145719334
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1256009526
Short name T759
Test name
Test status
Simulation time 124929913 ps
CPU time 9.55 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:49:14 PM PDT 24
Peak memory 256320 kb
Host smart-e259e065-15c6-4090-9e29-4e2369388831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256009526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1256009526
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1687652863
Short name T711
Test name
Test status
Simulation time 97993582 ps
CPU time 5.1 seconds
Started Jul 04 04:48:26 PM PDT 24
Finished Jul 04 04:48:31 PM PDT 24
Peak memory 240284 kb
Host smart-d3712c74-2cc1-4043-824b-a8c03cb1dbc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1687652863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1687652863
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2767832063
Short name T710
Test name
Test status
Simulation time 7853551 ps
CPU time 1.3 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 04:48:25 PM PDT 24
Peak memory 236492 kb
Host smart-01f4ec01-a5ec-4a4e-99ef-27bee65130bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2767832063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2767832063
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3621801822
Short name T803
Test name
Test status
Simulation time 506109070 ps
CPU time 40.15 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:58 PM PDT 24
Peak memory 248540 kb
Host smart-0a07f13b-c327-4b13-8b40-9a45938899ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3621801822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3621801822
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4255303433
Short name T150
Test name
Test status
Simulation time 6806213627 ps
CPU time 97.87 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:49:54 PM PDT 24
Peak memory 257084 kb
Host smart-9230e5e1-5739-4ebe-994e-78cac44d00a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4255303433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.4255303433
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3802845303
Short name T149
Test name
Test status
Simulation time 63849772328 ps
CPU time 1132.84 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 05:07:10 PM PDT 24
Peak memory 264940 kb
Host smart-aa8aa908-7ad8-4469-8180-a6ca7e88a6ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802845303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3802845303
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4242731802
Short name T750
Test name
Test status
Simulation time 113912138 ps
CPU time 5.27 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 248668 kb
Host smart-f085d76c-4b5f-4526-aea2-05321c7682ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4242731802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4242731802
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1062329058
Short name T757
Test name
Test status
Simulation time 1130066840 ps
CPU time 78.69 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:49:40 PM PDT 24
Peak memory 237432 kb
Host smart-81e4078b-9914-4798-a96a-671db1151f54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1062329058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1062329058
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3433690505
Short name T801
Test name
Test status
Simulation time 47473265547 ps
CPU time 431.06 seconds
Started Jul 04 04:48:31 PM PDT 24
Finished Jul 04 04:55:43 PM PDT 24
Peak memory 237488 kb
Host smart-141b8c28-05fa-4d31-8406-bc74499ccd9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3433690505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3433690505
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2738280072
Short name T772
Test name
Test status
Simulation time 192102864 ps
CPU time 5.75 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:21 PM PDT 24
Peak memory 248576 kb
Host smart-36a0c643-cd10-4c18-a821-dc7c7cff31c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2738280072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2738280072
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.419469615
Short name T824
Test name
Test status
Simulation time 29172024 ps
CPU time 4.43 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:21 PM PDT 24
Peak memory 240008 kb
Host smart-678bd1c0-fb72-4c2b-ba31-cd6a50abf00a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419469615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.419469615
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1085076105
Short name T712
Test name
Test status
Simulation time 53858743 ps
CPU time 3.29 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:17 PM PDT 24
Peak memory 236440 kb
Host smart-c39e2625-d9b0-48ce-a378-4c51c37f9e28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1085076105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1085076105
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3831681696
Short name T813
Test name
Test status
Simulation time 335994399 ps
CPU time 23.59 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:41 PM PDT 24
Peak memory 245612 kb
Host smart-952de279-d1fe-4f58-8c4a-260fd1953652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3831681696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3831681696
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1794746190
Short name T165
Test name
Test status
Simulation time 3829339725 ps
CPU time 246.63 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:52:24 PM PDT 24
Peak memory 265268 kb
Host smart-ee5ec5e7-0b0f-4a11-9d7a-7729c9e4902c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1794746190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1794746190
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.297063971
Short name T706
Test name
Test status
Simulation time 230779865 ps
CPU time 15.91 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:29 PM PDT 24
Peak memory 247980 kb
Host smart-16d54723-ef5e-4727-882c-b7be877e568b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=297063971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.297063971
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3508260604
Short name T791
Test name
Test status
Simulation time 31850692 ps
CPU time 5.55 seconds
Started Jul 04 04:48:41 PM PDT 24
Finished Jul 04 04:48:47 PM PDT 24
Peak memory 240860 kb
Host smart-2a9020c3-4063-4ac0-899b-34a03661e1ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508260604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3508260604
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1291886205
Short name T773
Test name
Test status
Simulation time 184651259 ps
CPU time 4.51 seconds
Started Jul 04 04:48:47 PM PDT 24
Finished Jul 04 04:48:52 PM PDT 24
Peak memory 236476 kb
Host smart-2946a142-65b8-45ed-8192-98b66c67ebfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1291886205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1291886205
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4206995020
Short name T344
Test name
Test status
Simulation time 12324701 ps
CPU time 1.58 seconds
Started Jul 04 04:48:32 PM PDT 24
Finished Jul 04 04:48:39 PM PDT 24
Peak memory 237440 kb
Host smart-50fe6c24-6b71-4d6c-adf2-04ee893914ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4206995020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4206995020
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2627428882
Short name T796
Test name
Test status
Simulation time 776905715 ps
CPU time 27.79 seconds
Started Jul 04 04:48:35 PM PDT 24
Finished Jul 04 04:49:03 PM PDT 24
Peak memory 248516 kb
Host smart-5f057b61-5df5-46fd-94c2-a262597007f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2627428882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2627428882
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3756629521
Short name T169
Test name
Test status
Simulation time 2220833338 ps
CPU time 335.07 seconds
Started Jul 04 04:48:44 PM PDT 24
Finished Jul 04 04:54:19 PM PDT 24
Peak memory 265264 kb
Host smart-58a79be3-ff46-4408-b088-fca21b53883b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756629521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3756629521
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1158626309
Short name T716
Test name
Test status
Simulation time 84307872 ps
CPU time 11.77 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:49:00 PM PDT 24
Peak memory 248396 kb
Host smart-325501a5-8243-428d-9be6-41d4fb5c50c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1158626309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1158626309
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3242837411
Short name T732
Test name
Test status
Simulation time 295278583 ps
CPU time 7.32 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:05 PM PDT 24
Peak memory 240200 kb
Host smart-bdf5bb46-eb76-47fe-8971-d08dc1ff31c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242837411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3242837411
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3404505615
Short name T728
Test name
Test status
Simulation time 870355601 ps
CPU time 4.88 seconds
Started Jul 04 04:48:55 PM PDT 24
Finished Jul 04 04:49:00 PM PDT 24
Peak memory 237296 kb
Host smart-bdd2711c-11f8-4ad1-83dd-b529fc2eceaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3404505615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3404505615
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3419957013
Short name T760
Test name
Test status
Simulation time 11447092 ps
CPU time 1.69 seconds
Started Jul 04 04:48:55 PM PDT 24
Finished Jul 04 04:48:57 PM PDT 24
Peak memory 236476 kb
Host smart-f7ab7785-8bb0-4577-af3d-2c2d3d941cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3419957013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3419957013
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.993775332
Short name T752
Test name
Test status
Simulation time 173388531 ps
CPU time 12.55 seconds
Started Jul 04 04:48:41 PM PDT 24
Finished Jul 04 04:48:53 PM PDT 24
Peak memory 240380 kb
Host smart-bcde1750-67c6-4b21-b29d-8f63a9dc104e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=993775332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.993775332
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1304513504
Short name T148
Test name
Test status
Simulation time 3016642349 ps
CPU time 365.74 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:54:54 PM PDT 24
Peak memory 270268 kb
Host smart-bbadbd8d-e212-4061-af32-eb3aa9e91949
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304513504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1304513504
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.253425242
Short name T714
Test name
Test status
Simulation time 298646542 ps
CPU time 12.13 seconds
Started Jul 04 04:48:45 PM PDT 24
Finished Jul 04 04:48:58 PM PDT 24
Peak memory 248648 kb
Host smart-142a4539-00c6-40ef-9afb-4bd3b4a2eab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=253425242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.253425242
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.119142816
Short name T753
Test name
Test status
Simulation time 901914011 ps
CPU time 36.22 seconds
Started Jul 04 04:48:43 PM PDT 24
Finished Jul 04 04:49:20 PM PDT 24
Peak memory 248580 kb
Host smart-08a7fc68-d61c-4b78-a38f-f5649b163e61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=119142816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.119142816
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1540237794
Short name T754
Test name
Test status
Simulation time 286242255 ps
CPU time 10.86 seconds
Started Jul 04 04:48:43 PM PDT 24
Finished Jul 04 04:48:54 PM PDT 24
Peak memory 252368 kb
Host smart-d3f11c1b-7c1e-4b59-9152-57bc37b19882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540237794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1540237794
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3596078097
Short name T767
Test name
Test status
Simulation time 153191272 ps
CPU time 7.95 seconds
Started Jul 04 04:48:55 PM PDT 24
Finished Jul 04 04:49:03 PM PDT 24
Peak memory 240484 kb
Host smart-ec987e0a-8349-40b0-b09a-9e841437942e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3596078097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3596078097
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1927741251
Short name T825
Test name
Test status
Simulation time 14196646 ps
CPU time 1.52 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:00 PM PDT 24
Peak memory 236496 kb
Host smart-e566ffd9-6b29-40f5-9c14-508c114a1ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1927741251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1927741251
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1897773222
Short name T805
Test name
Test status
Simulation time 269573436 ps
CPU time 19.48 seconds
Started Jul 04 04:48:45 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 240348 kb
Host smart-d63b44ff-38ec-4cd8-adec-fe2dda1d8ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1897773222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1897773222
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2361771956
Short name T140
Test name
Test status
Simulation time 3241919601 ps
CPU time 114.38 seconds
Started Jul 04 04:48:45 PM PDT 24
Finished Jul 04 04:50:40 PM PDT 24
Peak memory 266312 kb
Host smart-c3ad4cb3-8f24-483e-9ade-628aabdf59d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2361771956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2361771956
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.295946388
Short name T154
Test name
Test status
Simulation time 2313396351 ps
CPU time 435.81 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:56:11 PM PDT 24
Peak memory 265368 kb
Host smart-f709f59a-32b8-4640-b542-fe79c737a2fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295946388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.295946388
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4003428645
Short name T764
Test name
Test status
Simulation time 1004324592 ps
CPU time 12.12 seconds
Started Jul 04 04:48:33 PM PDT 24
Finished Jul 04 04:48:45 PM PDT 24
Peak memory 248624 kb
Host smart-5f862423-35b4-42bd-b404-3269d321d72c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4003428645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4003428645
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.450744735
Short name T191
Test name
Test status
Simulation time 62418946 ps
CPU time 3.43 seconds
Started Jul 04 04:48:33 PM PDT 24
Finished Jul 04 04:48:37 PM PDT 24
Peak memory 237400 kb
Host smart-ff35107b-97de-48b2-90f7-213d07530db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=450744735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.450744735
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1473795403
Short name T756
Test name
Test status
Simulation time 857917869 ps
CPU time 9.56 seconds
Started Jul 04 04:48:43 PM PDT 24
Finished Jul 04 04:48:53 PM PDT 24
Peak memory 251840 kb
Host smart-b1a28761-c1a7-429e-81d4-566803ee43e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473795403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1473795403
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2337687792
Short name T748
Test name
Test status
Simulation time 470784391 ps
CPU time 9.49 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:49:00 PM PDT 24
Peak memory 237428 kb
Host smart-adf7d2b8-0993-457c-bf80-3e5e84845829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2337687792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2337687792
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.30060888
Short name T826
Test name
Test status
Simulation time 10252108 ps
CPU time 1.68 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 04:49:05 PM PDT 24
Peak memory 236524 kb
Host smart-8e5a993c-0454-4354-8360-6aedc371565f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=30060888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.30060888
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1283197246
Short name T718
Test name
Test status
Simulation time 701722922 ps
CPU time 47.62 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:49:46 PM PDT 24
Peak memory 248572 kb
Host smart-ada1a571-9eb6-4c50-a348-036457c21857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1283197246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1283197246
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.841878822
Short name T802
Test name
Test status
Simulation time 7667430260 ps
CPU time 500.92 seconds
Started Jul 04 04:48:45 PM PDT 24
Finished Jul 04 04:57:07 PM PDT 24
Peak memory 269388 kb
Host smart-076f9a17-9fe3-4067-a168-d56732b95333
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841878822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.841878822
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.403766514
Short name T722
Test name
Test status
Simulation time 87415160 ps
CPU time 12.26 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 253564 kb
Host smart-46d18b8f-bcc5-4abc-9477-739b937d7997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=403766514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.403766514
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.600082863
Short name T705
Test name
Test status
Simulation time 305862713 ps
CPU time 11.86 seconds
Started Jul 04 04:48:45 PM PDT 24
Finished Jul 04 04:48:57 PM PDT 24
Peak memory 251684 kb
Host smart-d300f22d-bbd3-4b0f-9fa9-2dd20647ba2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600082863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.600082863
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.446667170
Short name T782
Test name
Test status
Simulation time 64782143 ps
CPU time 5.88 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:04 PM PDT 24
Peak memory 236464 kb
Host smart-5393c749-10e3-4fc2-9877-ab790f9ea2d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=446667170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.446667170
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.522961409
Short name T821
Test name
Test status
Simulation time 28200052 ps
CPU time 1.46 seconds
Started Jul 04 04:48:52 PM PDT 24
Finished Jul 04 04:48:53 PM PDT 24
Peak memory 236500 kb
Host smart-27633fda-36c7-4e0f-90e7-2e33b53cfeff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=522961409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.522961409
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4020699645
Short name T820
Test name
Test status
Simulation time 173753507 ps
CPU time 11.21 seconds
Started Jul 04 04:48:49 PM PDT 24
Finished Jul 04 04:49:00 PM PDT 24
Peak memory 244660 kb
Host smart-3e9e36a3-bc8f-4f4a-a53c-748bb66295d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4020699645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.4020699645
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3883031365
Short name T161
Test name
Test status
Simulation time 20544811807 ps
CPU time 145.6 seconds
Started Jul 04 04:48:52 PM PDT 24
Finished Jul 04 04:51:19 PM PDT 24
Peak memory 266080 kb
Host smart-bcddfb06-1474-4c91-a9b4-9c7da03ac201
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3883031365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3883031365
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3632428142
Short name T153
Test name
Test status
Simulation time 9128980517 ps
CPU time 344.07 seconds
Started Jul 04 04:48:52 PM PDT 24
Finished Jul 04 04:54:37 PM PDT 24
Peak memory 265284 kb
Host smart-6cfbf18a-5d2a-4327-a6e9-dd50c0fc062a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632428142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3632428142
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1351407700
Short name T777
Test name
Test status
Simulation time 1087428827 ps
CPU time 24.53 seconds
Started Jul 04 04:48:47 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 250780 kb
Host smart-56249aed-df7a-473e-8fb0-009afa9cb1de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1351407700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1351407700
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2702020079
Short name T792
Test name
Test status
Simulation time 303023329 ps
CPU time 6.16 seconds
Started Jul 04 04:48:56 PM PDT 24
Finished Jul 04 04:49:02 PM PDT 24
Peak memory 256768 kb
Host smart-a54b2275-5ec7-4101-b71a-5f2821b1f7fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702020079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2702020079
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2542035706
Short name T729
Test name
Test status
Simulation time 150312707 ps
CPU time 3.92 seconds
Started Jul 04 04:48:55 PM PDT 24
Finished Jul 04 04:48:59 PM PDT 24
Peak memory 237444 kb
Host smart-9563a72e-7782-4095-8f2e-1f0e3c2a2828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2542035706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2542035706
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2771983990
Short name T735
Test name
Test status
Simulation time 967331586 ps
CPU time 18.8 seconds
Started Jul 04 04:48:53 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 240392 kb
Host smart-c2a9e1ce-1420-4bec-80c0-1fa13877a012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2771983990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2771983990
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.900037142
Short name T168
Test name
Test status
Simulation time 2285195332 ps
CPU time 201.48 seconds
Started Jul 04 04:48:46 PM PDT 24
Finished Jul 04 04:52:08 PM PDT 24
Peak memory 265252 kb
Host smart-b179cbb0-73cd-42b7-8671-909630bbd8c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=900037142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.900037142
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.234727388
Short name T176
Test name
Test status
Simulation time 57948430707 ps
CPU time 944.92 seconds
Started Jul 04 04:48:53 PM PDT 24
Finished Jul 04 05:04:39 PM PDT 24
Peak memory 265336 kb
Host smart-a7838189-d72c-4d02-b8f4-372804fed05d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234727388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.234727388
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2579294169
Short name T702
Test name
Test status
Simulation time 103606824 ps
CPU time 6.94 seconds
Started Jul 04 04:48:39 PM PDT 24
Finished Jul 04 04:48:46 PM PDT 24
Peak memory 253776 kb
Host smart-fc2a22ba-b387-4c3c-a2d8-ab308aef3bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2579294169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2579294169
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3951514936
Short name T779
Test name
Test status
Simulation time 1344293568 ps
CPU time 9.87 seconds
Started Jul 04 04:48:47 PM PDT 24
Finished Jul 04 04:48:57 PM PDT 24
Peak memory 240800 kb
Host smart-aef3b831-bf86-4a9d-b914-6de6ecd37e44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951514936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3951514936
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1781254880
Short name T808
Test name
Test status
Simulation time 196301699 ps
CPU time 4.99 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:48:55 PM PDT 24
Peak memory 237440 kb
Host smart-588324ea-f586-40f3-8002-793a439ba44e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1781254880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1781254880
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.324436721
Short name T770
Test name
Test status
Simulation time 43932268 ps
CPU time 1.42 seconds
Started Jul 04 04:48:51 PM PDT 24
Finished Jul 04 04:48:53 PM PDT 24
Peak memory 237404 kb
Host smart-aeea1843-6acb-4b25-8f0e-f27efe9bac49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=324436721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.324436721
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2165570285
Short name T817
Test name
Test status
Simulation time 659244816 ps
CPU time 52.48 seconds
Started Jul 04 04:48:52 PM PDT 24
Finished Jul 04 04:49:44 PM PDT 24
Peak memory 245628 kb
Host smart-a945a249-998e-4bfd-949f-11902e18ed31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2165570285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2165570285
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3031437034
Short name T171
Test name
Test status
Simulation time 6151717433 ps
CPU time 203.49 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:52:23 PM PDT 24
Peak memory 265268 kb
Host smart-f0adc34f-ab10-4214-8420-a9ba16b16cf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3031437034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3031437034
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2459513525
Short name T816
Test name
Test status
Simulation time 30454975916 ps
CPU time 634.22 seconds
Started Jul 04 04:48:54 PM PDT 24
Finished Jul 04 04:59:28 PM PDT 24
Peak memory 265600 kb
Host smart-0e5ed912-3f51-47c0-8b0f-6a8f8bf69fab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459513525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2459513525
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3094914629
Short name T798
Test name
Test status
Simulation time 74357332 ps
CPU time 13.3 seconds
Started Jul 04 04:48:53 PM PDT 24
Finished Jul 04 04:49:07 PM PDT 24
Peak memory 248812 kb
Host smart-58bc7262-f126-4376-9c7a-3e2cf5ffc703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3094914629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3094914629
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1370945186
Short name T704
Test name
Test status
Simulation time 99693660 ps
CPU time 8.13 seconds
Started Jul 04 04:48:47 PM PDT 24
Finished Jul 04 04:48:56 PM PDT 24
Peak memory 240192 kb
Host smart-d7c097b0-7947-480e-99c5-ba16ea6aa786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370945186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1370945186
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1816709665
Short name T786
Test name
Test status
Simulation time 35926558 ps
CPU time 5.75 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:05 PM PDT 24
Peak memory 237400 kb
Host smart-0d781c11-a3d2-4cc1-aced-872594c3a46f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1816709665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1816709665
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2066425439
Short name T762
Test name
Test status
Simulation time 27228973 ps
CPU time 1.53 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 04:49:09 PM PDT 24
Peak memory 237416 kb
Host smart-8dfa6767-6363-4850-a369-f4f58ba7ea09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2066425439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2066425439
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2279356889
Short name T806
Test name
Test status
Simulation time 488335236 ps
CPU time 39.47 seconds
Started Jul 04 04:48:51 PM PDT 24
Finished Jul 04 04:49:30 PM PDT 24
Peak memory 245632 kb
Host smart-35da0ce5-7724-4676-bf32-084f21c5b734
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2279356889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2279356889
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.56556813
Short name T795
Test name
Test status
Simulation time 316232790 ps
CPU time 9.57 seconds
Started Jul 04 04:48:49 PM PDT 24
Finished Jul 04 04:48:59 PM PDT 24
Peak memory 248348 kb
Host smart-dfbd196d-ac03-48a4-93af-454bc2cd39fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=56556813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.56556813
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1139151326
Short name T776
Test name
Test status
Simulation time 1250703608 ps
CPU time 14.99 seconds
Started Jul 04 04:48:55 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 254708 kb
Host smart-07be37ea-f3ee-48e0-b91f-48afad231cbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139151326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1139151326
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1514842613
Short name T804
Test name
Test status
Simulation time 38313660 ps
CPU time 5.59 seconds
Started Jul 04 04:48:49 PM PDT 24
Finished Jul 04 04:48:55 PM PDT 24
Peak memory 240388 kb
Host smart-b452382b-b2e9-449e-9de6-27a91b875d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1514842613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1514842613
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.966676936
Short name T818
Test name
Test status
Simulation time 14617073 ps
CPU time 1.44 seconds
Started Jul 04 04:48:49 PM PDT 24
Finished Jul 04 04:48:51 PM PDT 24
Peak memory 236592 kb
Host smart-4678f33d-2398-4804-975f-5edc9610fda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=966676936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.966676936
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2523820085
Short name T707
Test name
Test status
Simulation time 719604535 ps
CPU time 22.05 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 244652 kb
Host smart-a4621779-03c9-4f46-9e3c-5043a4fed2a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2523820085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2523820085
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1178041692
Short name T142
Test name
Test status
Simulation time 6842304025 ps
CPU time 469.44 seconds
Started Jul 04 04:48:54 PM PDT 24
Finished Jul 04 04:56:44 PM PDT 24
Peak memory 265324 kb
Host smart-7b029f10-2ce5-46ad-ad02-4b58d1122c5f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178041692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1178041692
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1639792699
Short name T738
Test name
Test status
Simulation time 117462522 ps
CPU time 3.78 seconds
Started Jul 04 04:48:45 PM PDT 24
Finished Jul 04 04:48:49 PM PDT 24
Peak memory 249680 kb
Host smart-53fa6554-5f8d-4a30-bf30-2f99b675d5f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1639792699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1639792699
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.998007099
Short name T742
Test name
Test status
Simulation time 122844123 ps
CPU time 8.72 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 256672 kb
Host smart-34430ffb-c06e-4983-917a-6c8175664859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998007099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.998007099
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.362841423
Short name T214
Test name
Test status
Simulation time 108721274 ps
CPU time 8.19 seconds
Started Jul 04 04:48:49 PM PDT 24
Finished Jul 04 04:48:58 PM PDT 24
Peak memory 236568 kb
Host smart-4b5555bc-9f45-42e0-a222-cb65352ae8b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=362841423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.362841423
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.847743752
Short name T807
Test name
Test status
Simulation time 10673995 ps
CPU time 1.43 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:49:06 PM PDT 24
Peak memory 236484 kb
Host smart-a2f4ad37-8883-429c-b849-8de9ab820a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=847743752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.847743752
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3895205837
Short name T213
Test name
Test status
Simulation time 1211026713 ps
CPU time 23.74 seconds
Started Jul 04 04:48:45 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 245588 kb
Host smart-1323dd27-8073-4bb7-9037-5dd0511e9a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3895205837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3895205837
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1714382054
Short name T172
Test name
Test status
Simulation time 4349629222 ps
CPU time 369.16 seconds
Started Jul 04 04:48:51 PM PDT 24
Finished Jul 04 04:55:01 PM PDT 24
Peak memory 269456 kb
Host smart-b30f7fb9-3e06-4afb-ba7e-42519bfebabc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714382054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1714382054
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3615107673
Short name T703
Test name
Test status
Simulation time 38807848 ps
CPU time 5.16 seconds
Started Jul 04 04:48:55 PM PDT 24
Finished Jul 04 04:49:00 PM PDT 24
Peak memory 248452 kb
Host smart-c327beed-67ec-41a8-a9d9-b11b020fa0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3615107673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3615107673
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3798288608
Short name T198
Test name
Test status
Simulation time 13308617577 ps
CPU time 251.06 seconds
Started Jul 04 04:48:20 PM PDT 24
Finished Jul 04 04:52:31 PM PDT 24
Peak memory 240568 kb
Host smart-bf36c300-3f05-4656-ab36-eadceaf54d72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3798288608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3798288608
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2849543806
Short name T737
Test name
Test status
Simulation time 14840878150 ps
CPU time 234.13 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:52:12 PM PDT 24
Peak memory 237492 kb
Host smart-bc4821c9-dd02-484f-abec-f3483bb5da56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2849543806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2849543806
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1362015709
Short name T726
Test name
Test status
Simulation time 253899116 ps
CPU time 12.54 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:25 PM PDT 24
Peak memory 240368 kb
Host smart-51d81038-e017-4fe9-b5bf-01aea78310d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1362015709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1362015709
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1555382539
Short name T346
Test name
Test status
Simulation time 567733678 ps
CPU time 11.44 seconds
Started Jul 04 04:48:14 PM PDT 24
Finished Jul 04 04:48:26 PM PDT 24
Peak memory 251740 kb
Host smart-4c7e6c25-11e0-4ad5-a33a-753da5b785d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555382539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1555382539
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.403370076
Short name T211
Test name
Test status
Simulation time 97001202 ps
CPU time 7.25 seconds
Started Jul 04 04:48:13 PM PDT 24
Finished Jul 04 04:48:20 PM PDT 24
Peak memory 236464 kb
Host smart-db6f3bde-8bcb-4f06-bed5-0d6f2e4f272e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=403370076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.403370076
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2187101945
Short name T790
Test name
Test status
Simulation time 27123116 ps
CPU time 1.47 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 04:48:25 PM PDT 24
Peak memory 236484 kb
Host smart-1f44f7aa-616f-49ad-bdd3-a5bad974443c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2187101945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2187101945
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.517663020
Short name T717
Test name
Test status
Simulation time 1397887694 ps
CPU time 49.22 seconds
Started Jul 04 04:48:22 PM PDT 24
Finished Jul 04 04:49:11 PM PDT 24
Peak memory 245636 kb
Host smart-adfa2ade-6066-44c8-acd8-89667580bad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=517663020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.517663020
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.744982811
Short name T166
Test name
Test status
Simulation time 12893011969 ps
CPU time 191.4 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 264508 kb
Host smart-1729470b-9251-44a7-afff-b23dd5287fa1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=744982811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.744982811
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.136846559
Short name T793
Test name
Test status
Simulation time 182250862 ps
CPU time 11.82 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:30 PM PDT 24
Peak memory 254032 kb
Host smart-a51085d8-520e-4723-b19b-c9f958fea8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=136846559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.136846559
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2753900326
Short name T819
Test name
Test status
Simulation time 13866394 ps
CPU time 1.83 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:49:01 PM PDT 24
Peak memory 235464 kb
Host smart-7cd3a757-fac7-492a-821a-e5af7f5be3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2753900326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2753900326
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.197506621
Short name T731
Test name
Test status
Simulation time 7542657 ps
CPU time 1.39 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:08 PM PDT 24
Peak memory 237436 kb
Host smart-5c547fd5-ca6c-4bd0-bcd2-ca4633484db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=197506621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.197506621
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.433751817
Short name T343
Test name
Test status
Simulation time 10200329 ps
CPU time 1.23 seconds
Started Jul 04 04:48:46 PM PDT 24
Finished Jul 04 04:48:47 PM PDT 24
Peak memory 235472 kb
Host smart-862dad2a-a917-437f-b0de-25f46215ec3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=433751817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.433751817
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.326224433
Short name T733
Test name
Test status
Simulation time 19804734 ps
CPU time 1.42 seconds
Started Jul 04 04:48:51 PM PDT 24
Finished Jul 04 04:48:58 PM PDT 24
Peak memory 236512 kb
Host smart-cf94cfcf-3a4e-4d8a-a288-54a633d0f518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=326224433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.326224433
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.177711125
Short name T342
Test name
Test status
Simulation time 11600911 ps
CPU time 1.32 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:48:52 PM PDT 24
Peak memory 237400 kb
Host smart-5f02e206-1f11-4b26-8b11-9e03ef515ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=177711125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.177711125
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.112613839
Short name T799
Test name
Test status
Simulation time 6491770 ps
CPU time 1.57 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:01 PM PDT 24
Peak memory 237452 kb
Host smart-d8a2428f-aa89-4efc-b0fa-a32149c8c507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=112613839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.112613839
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3145209747
Short name T337
Test name
Test status
Simulation time 18871214 ps
CPU time 1.4 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:48:51 PM PDT 24
Peak memory 237416 kb
Host smart-8c135a1b-4c99-4060-955d-ba3acc7d3634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3145209747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3145209747
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1596154119
Short name T789
Test name
Test status
Simulation time 10972213 ps
CPU time 1.41 seconds
Started Jul 04 04:48:46 PM PDT 24
Finished Jul 04 04:48:48 PM PDT 24
Peak memory 236496 kb
Host smart-c079959b-b60a-4125-a293-7b8229db4c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1596154119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1596154119
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3586470338
Short name T745
Test name
Test status
Simulation time 48698007 ps
CPU time 1.41 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:09 PM PDT 24
Peak memory 237280 kb
Host smart-b9f7d32f-dd69-4fb9-b94d-9ccd0d80eeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3586470338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3586470338
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2994970943
Short name T743
Test name
Test status
Simulation time 8295195 ps
CPU time 1.59 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:48:59 PM PDT 24
Peak memory 237428 kb
Host smart-9cceddd0-042e-4b14-b290-159c7581f6d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2994970943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2994970943
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2092172153
Short name T725
Test name
Test status
Simulation time 9572074937 ps
CPU time 185.83 seconds
Started Jul 04 04:48:24 PM PDT 24
Finished Jul 04 04:51:30 PM PDT 24
Peak memory 237500 kb
Host smart-d9527d58-2e4d-4b2b-8ecc-787603b0554e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2092172153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2092172153
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2646720903
Short name T212
Test name
Test status
Simulation time 7424119202 ps
CPU time 211.65 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:51:48 PM PDT 24
Peak memory 240528 kb
Host smart-323693f0-11dd-42ba-bb6a-69a207b58f51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2646720903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2646720903
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2939782012
Short name T713
Test name
Test status
Simulation time 571991485 ps
CPU time 7.57 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:24 PM PDT 24
Peak memory 240544 kb
Host smart-0d212ead-cf7d-4b47-b372-119b19685510
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2939782012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2939782012
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.662871357
Short name T749
Test name
Test status
Simulation time 92120177 ps
CPU time 7.38 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:24 PM PDT 24
Peak memory 248676 kb
Host smart-f9add9b4-e27e-4b7c-9f63-21a0d1b4b966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662871357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.662871357
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3253186061
Short name T744
Test name
Test status
Simulation time 70518976 ps
CPU time 6.73 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 240324 kb
Host smart-19bb5236-fa73-4fea-b16e-717406baf424
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3253186061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3253186061
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1905132478
Short name T771
Test name
Test status
Simulation time 9893715 ps
CPU time 1.52 seconds
Started Jul 04 04:48:16 PM PDT 24
Finished Jul 04 04:48:18 PM PDT 24
Peak memory 236576 kb
Host smart-bdc346e2-13c9-4216-b427-778903520480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1905132478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1905132478
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3213659461
Short name T769
Test name
Test status
Simulation time 570532723 ps
CPU time 21.55 seconds
Started Jul 04 04:48:25 PM PDT 24
Finished Jul 04 04:48:47 PM PDT 24
Peak memory 245600 kb
Host smart-67b3ff6e-923f-4831-9500-da254c1782f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3213659461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3213659461
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2905581420
Short name T164
Test name
Test status
Simulation time 25112434483 ps
CPU time 292.43 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:53:08 PM PDT 24
Peak memory 265204 kb
Host smart-33b9d24b-d25b-454a-a9b7-155cb883b26c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905581420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2905581420
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2728408341
Short name T751
Test name
Test status
Simulation time 297501224 ps
CPU time 11.41 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:30 PM PDT 24
Peak memory 253616 kb
Host smart-95cd538a-a804-4c3c-9900-ae322ae8cc51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2728408341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2728408341
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2290690142
Short name T183
Test name
Test status
Simulation time 6857379 ps
CPU time 1.51 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:48:50 PM PDT 24
Peak memory 237400 kb
Host smart-78ea168e-1480-448f-9642-eb00e565676a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2290690142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2290690142
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.372252050
Short name T810
Test name
Test status
Simulation time 9788748 ps
CPU time 1.61 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:03 PM PDT 24
Peak memory 236480 kb
Host smart-f6a4ff05-0618-400b-bf96-125d5b5a8114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=372252050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.372252050
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2690141433
Short name T721
Test name
Test status
Simulation time 24711994 ps
CPU time 1.49 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:01 PM PDT 24
Peak memory 237416 kb
Host smart-0d944d3b-0951-43a5-bc5d-83c1b8a62926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2690141433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2690141433
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3509370333
Short name T341
Test name
Test status
Simulation time 11163432 ps
CPU time 1.48 seconds
Started Jul 04 04:48:51 PM PDT 24
Finished Jul 04 04:48:53 PM PDT 24
Peak memory 237408 kb
Host smart-e02f3197-fc21-4bba-a9bc-343c9e238123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3509370333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3509370333
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3726423744
Short name T719
Test name
Test status
Simulation time 14782718 ps
CPU time 1.51 seconds
Started Jul 04 04:48:56 PM PDT 24
Finished Jul 04 04:48:59 PM PDT 24
Peak memory 237428 kb
Host smart-604ad852-7852-4276-a691-ec66870dbd01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3726423744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3726423744
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3832462200
Short name T784
Test name
Test status
Simulation time 7957477 ps
CPU time 1.5 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:03 PM PDT 24
Peak memory 237436 kb
Host smart-33cf4886-5c65-4a3a-8ad7-2913592015a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3832462200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3832462200
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3815089522
Short name T783
Test name
Test status
Simulation time 10380819 ps
CPU time 1.67 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 236436 kb
Host smart-26d68748-8c63-4969-b976-462365adb46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3815089522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3815089522
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.4008948972
Short name T740
Test name
Test status
Simulation time 13508487 ps
CPU time 1.82 seconds
Started Jul 04 04:48:46 PM PDT 24
Finished Jul 04 04:48:48 PM PDT 24
Peak memory 237428 kb
Host smart-a51ab356-f7bb-4c3b-9937-8aa10e8b7cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008948972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.4008948972
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.72505373
Short name T715
Test name
Test status
Simulation time 12896879 ps
CPU time 1.5 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:48:51 PM PDT 24
Peak memory 236496 kb
Host smart-2b83357b-0e4c-46f1-ab1f-c6c224211d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=72505373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.72505373
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2572385951
Short name T766
Test name
Test status
Simulation time 1761299050 ps
CPU time 125.13 seconds
Started Jul 04 04:48:20 PM PDT 24
Finished Jul 04 04:50:25 PM PDT 24
Peak memory 237512 kb
Host smart-fa9df4b7-36e9-464a-8b03-1ce99bc8bcdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2572385951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2572385951
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2779699657
Short name T794
Test name
Test status
Simulation time 16399543521 ps
CPU time 564.28 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:57:40 PM PDT 24
Peak memory 237508 kb
Host smart-b130eb5c-2d9a-41fb-9116-2966e3064544
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2779699657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2779699657
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3158934020
Short name T741
Test name
Test status
Simulation time 159853066 ps
CPU time 5.75 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:48:27 PM PDT 24
Peak memory 240384 kb
Host smart-5e65f6f2-992b-4092-add5-32bc9c1a612e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3158934020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3158934020
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3081796243
Short name T763
Test name
Test status
Simulation time 211211435 ps
CPU time 13.81 seconds
Started Jul 04 04:48:15 PM PDT 24
Finished Jul 04 04:48:29 PM PDT 24
Peak memory 242884 kb
Host smart-4e3bb3f1-0fa7-4901-8690-91b98ec27845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081796243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3081796243
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1268325398
Short name T797
Test name
Test status
Simulation time 138613374 ps
CPU time 5.9 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 237444 kb
Host smart-b5c95c1d-8a45-4537-99d0-fcfc359190b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1268325398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1268325398
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2890909161
Short name T736
Test name
Test status
Simulation time 8380875 ps
CPU time 1.34 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:19 PM PDT 24
Peak memory 235500 kb
Host smart-8ecee69d-8842-4252-a173-88261488e590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2890909161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2890909161
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.850278223
Short name T788
Test name
Test status
Simulation time 575333680 ps
CPU time 44.89 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:49:06 PM PDT 24
Peak memory 245564 kb
Host smart-15ceba2e-aaad-4219-b572-3fd2197b9c93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=850278223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.850278223
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3678366295
Short name T345
Test name
Test status
Simulation time 43711876410 ps
CPU time 519.43 seconds
Started Jul 04 04:48:22 PM PDT 24
Finished Jul 04 04:57:02 PM PDT 24
Peak memory 265420 kb
Host smart-a0b1d372-869d-40fa-a48f-e055436c2856
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678366295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3678366295
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4229384221
Short name T822
Test name
Test status
Simulation time 528760089 ps
CPU time 12.71 seconds
Started Jul 04 04:48:27 PM PDT 24
Finished Jul 04 04:48:40 PM PDT 24
Peak memory 248636 kb
Host smart-6928bfa4-d5c5-44dc-a61d-bed5b777a6ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4229384221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4229384221
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2922047183
Short name T761
Test name
Test status
Simulation time 6432908 ps
CPU time 1.55 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:03 PM PDT 24
Peak memory 237440 kb
Host smart-3c7f7f0b-f787-414e-b490-8faaac6463ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2922047183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2922047183
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3106887805
Short name T724
Test name
Test status
Simulation time 11149551 ps
CPU time 1.66 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:48:50 PM PDT 24
Peak memory 236508 kb
Host smart-ba8ec28d-e896-4047-bbb4-0a32fb1659fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3106887805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3106887805
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3522257454
Short name T800
Test name
Test status
Simulation time 9210980 ps
CPU time 1.56 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:49:06 PM PDT 24
Peak memory 237404 kb
Host smart-faee434a-48c1-455c-be6e-8bdc8acd098d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3522257454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3522257454
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2220716721
Short name T746
Test name
Test status
Simulation time 6635398 ps
CPU time 1.45 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 04:49:07 PM PDT 24
Peak memory 237440 kb
Host smart-810226c9-a483-46dc-bcf0-251b91e919d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220716721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2220716721
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3492290697
Short name T182
Test name
Test status
Simulation time 17415335 ps
CPU time 1.9 seconds
Started Jul 04 04:48:54 PM PDT 24
Finished Jul 04 04:48:57 PM PDT 24
Peak memory 237416 kb
Host smart-a25d3858-068c-4a32-8273-a2357641c063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3492290697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3492290697
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2508675188
Short name T723
Test name
Test status
Simulation time 8356521 ps
CPU time 1.59 seconds
Started Jul 04 04:48:54 PM PDT 24
Finished Jul 04 04:48:56 PM PDT 24
Peak memory 237428 kb
Host smart-1ac9beae-bdc8-4685-ac87-009280b15a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2508675188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2508675188
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4212820214
Short name T340
Test name
Test status
Simulation time 15568429 ps
CPU time 1.35 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:02 PM PDT 24
Peak memory 235472 kb
Host smart-ad9c7eab-ac89-45ba-bc16-5dc47517311d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4212820214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4212820214
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2013560349
Short name T338
Test name
Test status
Simulation time 6518463 ps
CPU time 1.43 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 04:49:07 PM PDT 24
Peak memory 236496 kb
Host smart-61c7742f-e548-4b77-bda1-fff9615289de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2013560349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2013560349
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2342788357
Short name T787
Test name
Test status
Simulation time 11786129 ps
CPU time 1.39 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:01 PM PDT 24
Peak memory 236488 kb
Host smart-9deb25fe-c54a-4365-b8fc-38d57307eefb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2342788357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2342788357
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.353133245
Short name T734
Test name
Test status
Simulation time 23728728 ps
CPU time 1.64 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:00 PM PDT 24
Peak memory 236488 kb
Host smart-08465509-adf1-48be-9950-be6fc9224925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=353133245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.353133245
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3806125121
Short name T708
Test name
Test status
Simulation time 77501511 ps
CPU time 7.11 seconds
Started Jul 04 04:48:21 PM PDT 24
Finished Jul 04 04:48:28 PM PDT 24
Peak memory 239532 kb
Host smart-669bf70c-2c11-4ba3-8a0d-8d7d542d703c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806125121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3806125121
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3458906353
Short name T814
Test name
Test status
Simulation time 43855101 ps
CPU time 5.11 seconds
Started Jul 04 04:48:22 PM PDT 24
Finished Jul 04 04:48:27 PM PDT 24
Peak memory 236484 kb
Host smart-b2715317-4d17-457f-afb0-8019a68b6e3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3458906353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3458906353
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.360558600
Short name T339
Test name
Test status
Simulation time 11752258 ps
CPU time 1.52 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:48:20 PM PDT 24
Peak memory 237396 kb
Host smart-d7692c8d-fd44-4890-a37a-f5614e66363e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=360558600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.360558600
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.946040651
Short name T739
Test name
Test status
Simulation time 92651391 ps
CPU time 12.2 seconds
Started Jul 04 04:48:18 PM PDT 24
Finished Jul 04 04:48:31 PM PDT 24
Peak memory 248540 kb
Host smart-6ddd0673-2ca8-4af2-8115-76b03b2634ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=946040651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.946040651
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1712327749
Short name T160
Test name
Test status
Simulation time 19408129089 ps
CPU time 367.16 seconds
Started Jul 04 04:48:30 PM PDT 24
Finished Jul 04 04:54:37 PM PDT 24
Peak memory 272852 kb
Host smart-fe0fcb71-7b75-436c-a705-2bbde50614fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1712327749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1712327749
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1203910432
Short name T167
Test name
Test status
Simulation time 28392635025 ps
CPU time 579.69 seconds
Started Jul 04 04:48:19 PM PDT 24
Finished Jul 04 04:57:59 PM PDT 24
Peak memory 265272 kb
Host smart-0793c1f6-562d-4693-b8ff-5809012f1b1e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203910432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1203910432
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2711459075
Short name T811
Test name
Test status
Simulation time 100817036 ps
CPU time 5.3 seconds
Started Jul 04 04:48:17 PM PDT 24
Finished Jul 04 04:48:23 PM PDT 24
Peak memory 248596 kb
Host smart-e3d4bdcb-487b-447b-8788-52ccb7f38c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2711459075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2711459075
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3856927095
Short name T774
Test name
Test status
Simulation time 35738319 ps
CPU time 6.39 seconds
Started Jul 04 04:48:44 PM PDT 24
Finished Jul 04 04:48:51 PM PDT 24
Peak memory 256760 kb
Host smart-21376419-3a55-4644-b626-b0f75e7eb950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856927095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3856927095
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2093077086
Short name T812
Test name
Test status
Simulation time 21387615 ps
CPU time 4.55 seconds
Started Jul 04 04:48:37 PM PDT 24
Finished Jul 04 04:48:42 PM PDT 24
Peak memory 237444 kb
Host smart-fc82bc75-3e88-4763-8514-59ac5272e819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2093077086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2093077086
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3072094631
Short name T775
Test name
Test status
Simulation time 10425126 ps
CPU time 1.65 seconds
Started Jul 04 04:48:25 PM PDT 24
Finished Jul 04 04:48:27 PM PDT 24
Peak memory 237452 kb
Host smart-4fd4f30d-7455-49a2-a069-e6cac67ba5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3072094631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3072094631
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.244514759
Short name T199
Test name
Test status
Simulation time 1056157009 ps
CPU time 37.72 seconds
Started Jul 04 04:48:28 PM PDT 24
Finished Jul 04 04:49:06 PM PDT 24
Peak memory 244708 kb
Host smart-0f7613e1-ff6b-4ba8-8730-5bdb9265184d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=244514759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.244514759
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1129645099
Short name T152
Test name
Test status
Simulation time 788790688 ps
CPU time 94.31 seconds
Started Jul 04 04:48:24 PM PDT 24
Finished Jul 04 04:49:58 PM PDT 24
Peak memory 265360 kb
Host smart-a842da92-b3ba-424b-9711-17e772642fe8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1129645099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1129645099
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3360925881
Short name T174
Test name
Test status
Simulation time 4938744089 ps
CPU time 603.75 seconds
Started Jul 04 04:48:41 PM PDT 24
Finished Jul 04 04:58:45 PM PDT 24
Peak memory 265364 kb
Host smart-b58e1396-98d2-432c-af79-3c5d247619d8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360925881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3360925881
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3325041918
Short name T765
Test name
Test status
Simulation time 49642152 ps
CPU time 7.59 seconds
Started Jul 04 04:48:26 PM PDT 24
Finished Jul 04 04:48:34 PM PDT 24
Peak memory 248612 kb
Host smart-8253739c-7062-4079-a26e-936c892a98c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3325041918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3325041918
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.146097326
Short name T197
Test name
Test status
Simulation time 58940260 ps
CPU time 4.75 seconds
Started Jul 04 04:48:33 PM PDT 24
Finished Jul 04 04:48:38 PM PDT 24
Peak memory 240364 kb
Host smart-0788c893-a26c-42d1-b51a-9733830267be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146097326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.146097326
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3226831906
Short name T785
Test name
Test status
Simulation time 24688585 ps
CPU time 3.91 seconds
Started Jul 04 04:48:23 PM PDT 24
Finished Jul 04 04:48:27 PM PDT 24
Peak memory 237400 kb
Host smart-d5a94413-1fa7-4b03-b6d0-2f0e75a79ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3226831906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3226831906
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1379185970
Short name T720
Test name
Test status
Simulation time 18245978 ps
CPU time 1.44 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:48:50 PM PDT 24
Peak memory 236564 kb
Host smart-a1dde663-dc84-469e-a1ff-2f2cd0f7958f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1379185970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1379185970
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2476468243
Short name T780
Test name
Test status
Simulation time 718875613 ps
CPU time 25.63 seconds
Started Jul 04 04:48:32 PM PDT 24
Finished Jul 04 04:48:58 PM PDT 24
Peak memory 245612 kb
Host smart-16d82835-2cd9-4f84-925e-669395a41957
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2476468243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2476468243
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.290728275
Short name T173
Test name
Test status
Simulation time 1989490330 ps
CPU time 150.44 seconds
Started Jul 04 04:48:55 PM PDT 24
Finished Jul 04 04:51:25 PM PDT 24
Peak memory 257124 kb
Host smart-f87d7694-a206-4411-8f41-114a4027d912
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=290728275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.290728275
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3571701374
Short name T727
Test name
Test status
Simulation time 278542868 ps
CPU time 6.82 seconds
Started Jul 04 04:48:39 PM PDT 24
Finished Jul 04 04:48:46 PM PDT 24
Peak memory 248532 kb
Host smart-8fd7a19c-f20d-49af-b834-d01bc7e74416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3571701374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3571701374
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1361540840
Short name T827
Test name
Test status
Simulation time 378565609 ps
CPU time 8.76 seconds
Started Jul 04 04:48:33 PM PDT 24
Finished Jul 04 04:48:42 PM PDT 24
Peak memory 239952 kb
Host smart-2a03052e-f3dc-4b57-9da9-f00d6135a019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361540840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1361540840
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1808985211
Short name T815
Test name
Test status
Simulation time 33786047 ps
CPU time 5.83 seconds
Started Jul 04 04:48:47 PM PDT 24
Finished Jul 04 04:48:53 PM PDT 24
Peak memory 237396 kb
Host smart-7a15ba79-1a06-4f22-b818-fdc6a4af4516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1808985211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1808985211
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3737777928
Short name T709
Test name
Test status
Simulation time 9611898 ps
CPU time 1.65 seconds
Started Jul 04 04:48:46 PM PDT 24
Finished Jul 04 04:48:48 PM PDT 24
Peak memory 237392 kb
Host smart-0a56135a-25bf-470a-a12b-c73ff8a49fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3737777928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3737777928
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.479546913
Short name T778
Test name
Test status
Simulation time 3507138073 ps
CPU time 39.49 seconds
Started Jul 04 04:48:38 PM PDT 24
Finished Jul 04 04:49:18 PM PDT 24
Peak memory 245668 kb
Host smart-b70edcac-3515-4519-912c-6e3035ba745a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=479546913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.479546913
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3950321683
Short name T170
Test name
Test status
Simulation time 3414773703 ps
CPU time 220.16 seconds
Started Jul 04 04:48:24 PM PDT 24
Finished Jul 04 04:52:04 PM PDT 24
Peak memory 265512 kb
Host smart-22ffe3ae-10cb-4fd5-bb47-b67278466873
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3950321683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3950321683
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.321600054
Short name T701
Test name
Test status
Simulation time 394717667 ps
CPU time 13.65 seconds
Started Jul 04 04:48:43 PM PDT 24
Finished Jul 04 04:48:57 PM PDT 24
Peak memory 248740 kb
Host smart-7287137d-13d5-4a74-ad8a-6f1aff007b37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=321600054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.321600054
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.758807798
Short name T747
Test name
Test status
Simulation time 136393466 ps
CPU time 5.73 seconds
Started Jul 04 04:48:27 PM PDT 24
Finished Jul 04 04:48:33 PM PDT 24
Peak memory 248700 kb
Host smart-89ba9f1b-4f19-4c94-a5ea-0073d62f5562
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758807798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.758807798
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1635516302
Short name T730
Test name
Test status
Simulation time 363938953 ps
CPU time 9.38 seconds
Started Jul 04 04:48:28 PM PDT 24
Finished Jul 04 04:48:37 PM PDT 24
Peak memory 237440 kb
Host smart-890a5252-6b7d-4480-907f-585ce9ee67fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1635516302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1635516302
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.211281695
Short name T809
Test name
Test status
Simulation time 25985393 ps
CPU time 2.16 seconds
Started Jul 04 04:48:27 PM PDT 24
Finished Jul 04 04:48:30 PM PDT 24
Peak memory 237440 kb
Host smart-75a63661-7d31-4444-bf8a-4a6929c35c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=211281695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.211281695
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1505962055
Short name T768
Test name
Test status
Simulation time 515945259 ps
CPU time 38.44 seconds
Started Jul 04 04:48:38 PM PDT 24
Finished Jul 04 04:49:17 PM PDT 24
Peak memory 244708 kb
Host smart-b8c8fbfa-f7d9-4ac5-85fd-1342a36f2976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1505962055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1505962055
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2887049354
Short name T781
Test name
Test status
Simulation time 223384510 ps
CPU time 22.14 seconds
Started Jul 04 04:48:44 PM PDT 24
Finished Jul 04 04:49:06 PM PDT 24
Peak memory 254144 kb
Host smart-1c941292-ab99-4d92-af18-3c4972c0743f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2887049354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2887049354
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2061547170
Short name T823
Test name
Test status
Simulation time 607511659 ps
CPU time 25.48 seconds
Started Jul 04 04:48:53 PM PDT 24
Finished Jul 04 04:49:19 PM PDT 24
Peak memory 240396 kb
Host smart-f656e72d-908e-426c-b372-2ca3c855acfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2061547170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2061547170
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1504247882
Short name T210
Test name
Test status
Simulation time 35403494651 ps
CPU time 1133.51 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 05:07:59 PM PDT 24
Peak memory 273840 kb
Host smart-95353d69-6a6c-4e3f-93df-7bc5428b890f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504247882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1504247882
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.888409665
Short name T363
Test name
Test status
Simulation time 159967105 ps
CPU time 10.28 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 04:49:17 PM PDT 24
Peak memory 249132 kb
Host smart-628920ab-1722-47bd-8c08-8808cea82a0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=888409665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.888409665
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.54717447
Short name T604
Test name
Test status
Simulation time 1793523639 ps
CPU time 52.36 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 04:50:00 PM PDT 24
Peak memory 256660 kb
Host smart-db998369-325b-4c09-b614-fd5c5e1a4d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54717
447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.54717447
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4088490348
Short name T515
Test name
Test status
Simulation time 1298813295 ps
CPU time 72.95 seconds
Started Jul 04 04:48:50 PM PDT 24
Finished Jul 04 04:50:03 PM PDT 24
Peak memory 249176 kb
Host smart-423f99e1-b669-4295-a66d-2d7f649a5a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40884
90348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4088490348
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.4120179846
Short name T585
Test name
Test status
Simulation time 45931166525 ps
CPU time 1295.12 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 05:10:35 PM PDT 24
Peak memory 265620 kb
Host smart-73745fa7-2eb5-4354-812f-243543a6012a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120179846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.4120179846
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1416703933
Short name T562
Test name
Test status
Simulation time 44114107630 ps
CPU time 425.09 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:56:03 PM PDT 24
Peak memory 249128 kb
Host smart-2946c4a1-6a6c-464b-bc33-d53ba6298a7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416703933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1416703933
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2625387157
Short name T554
Test name
Test status
Simulation time 265488251 ps
CPU time 21.57 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:24 PM PDT 24
Peak memory 256724 kb
Host smart-ac6cc3be-e733-4932-a28f-f65df858e60a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253
87157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2625387157
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2144329739
Short name T548
Test name
Test status
Simulation time 4029840533 ps
CPU time 43.93 seconds
Started Jul 04 04:48:56 PM PDT 24
Finished Jul 04 04:49:40 PM PDT 24
Peak memory 248424 kb
Host smart-8d592a7d-9e5b-4ae2-8714-5275d34a05a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21443
29739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2144329739
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2254041282
Short name T12
Test name
Test status
Simulation time 2836820090 ps
CPU time 16.73 seconds
Started Jul 04 04:48:51 PM PDT 24
Finished Jul 04 04:49:08 PM PDT 24
Peak memory 271336 kb
Host smart-8d6aebfb-f837-4d95-a668-fabd4ef7639f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2254041282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2254041282
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.499676338
Short name T675
Test name
Test status
Simulation time 1982997616 ps
CPU time 28.04 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:37 PM PDT 24
Peak memory 256820 kb
Host smart-2f0ba846-d300-45c4-aee3-8275ff718b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49967
6338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.499676338
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2770225969
Short name T375
Test name
Test status
Simulation time 665568932 ps
CPU time 35.73 seconds
Started Jul 04 04:48:48 PM PDT 24
Finished Jul 04 04:49:24 PM PDT 24
Peak memory 249100 kb
Host smart-3700a467-5dff-456a-b23e-a1d79551736a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
25969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2770225969
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3147084610
Short name T490
Test name
Test status
Simulation time 55676195471 ps
CPU time 3408.17 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 05:45:52 PM PDT 24
Peak memory 289572 kb
Host smart-09e6e6b1-ba8b-44c2-83a8-bf92932e4a5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147084610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3147084610
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1550198022
Short name T132
Test name
Test status
Simulation time 329883233748 ps
CPU time 7415.75 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 06:52:34 PM PDT 24
Peak memory 355352 kb
Host smart-1a4c8a5c-748d-4052-9c01-2c42a0d6f933
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550198022 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1550198022
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1629381281
Short name T384
Test name
Test status
Simulation time 22405674769 ps
CPU time 1331.62 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 05:11:19 PM PDT 24
Peak memory 273752 kb
Host smart-5c4784d4-791d-4ff5-a83e-fea896788cc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629381281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1629381281
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1489462205
Short name T648
Test name
Test status
Simulation time 1407116624 ps
CPU time 56.69 seconds
Started Jul 04 04:48:56 PM PDT 24
Finished Jul 04 04:49:54 PM PDT 24
Peak memory 249100 kb
Host smart-b1ecdce4-1340-431c-bffe-42a6e564bad9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1489462205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1489462205
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3497143956
Short name T441
Test name
Test status
Simulation time 15128710930 ps
CPU time 188.4 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:52:17 PM PDT 24
Peak memory 257032 kb
Host smart-95c18851-8cbd-48ba-a27b-1c1fc41ef5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34971
43956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3497143956
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.656141819
Short name T366
Test name
Test status
Simulation time 309683050 ps
CPU time 28.09 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:49:28 PM PDT 24
Peak memory 249152 kb
Host smart-3716d4ea-777e-4509-9345-330ed50ff453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65614
1819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.656141819
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3651717098
Short name T613
Test name
Test status
Simulation time 20823133559 ps
CPU time 1201.22 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 05:09:03 PM PDT 24
Peak memory 273728 kb
Host smart-54734dbd-0117-42b9-8055-36813594314a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651717098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3651717098
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.180082008
Short name T625
Test name
Test status
Simulation time 22292050201 ps
CPU time 201.85 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:52:30 PM PDT 24
Peak memory 249316 kb
Host smart-5e3dc433-da4c-41e4-a1ce-9bafff68c62f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180082008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.180082008
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1027044345
Short name T634
Test name
Test status
Simulation time 208570550 ps
CPU time 14.1 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:49:14 PM PDT 24
Peak memory 249076 kb
Host smart-cd39c33b-9555-4ae9-a7fe-b9a7dc48860e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
44345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1027044345
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.101973510
Short name T561
Test name
Test status
Simulation time 850727490 ps
CPU time 55.07 seconds
Started Jul 04 04:48:53 PM PDT 24
Finished Jul 04 04:49:48 PM PDT 24
Peak memory 256932 kb
Host smart-94e309ae-48d8-424e-9c23-51d054012bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10197
3510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.101973510
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1598673521
Short name T35
Test name
Test status
Simulation time 1503158432 ps
CPU time 22.8 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:49:27 PM PDT 24
Peak memory 271852 kb
Host smart-bc12e82d-538d-486b-869f-f3730306f40e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1598673521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1598673521
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.839368086
Short name T135
Test name
Test status
Simulation time 1222363863 ps
CPU time 50.8 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:50:00 PM PDT 24
Peak memory 257216 kb
Host smart-2d293441-f8dc-4c10-977f-f46db83b8d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83936
8086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.839368086
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2958371210
Short name T656
Test name
Test status
Simulation time 838227814 ps
CPU time 10.61 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 255088 kb
Host smart-5271c7a3-beae-4fe1-a52c-493bfff16e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29583
71210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2958371210
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3736087473
Short name T627
Test name
Test status
Simulation time 31591637372 ps
CPU time 1770.32 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 05:18:33 PM PDT 24
Peak memory 290176 kb
Host smart-686af50c-6845-4eb5-97c8-801c7abd2ee5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736087473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3736087473
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2047835117
Short name T231
Test name
Test status
Simulation time 43116103 ps
CPU time 3.9 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:13 PM PDT 24
Peak memory 249420 kb
Host smart-35c55367-9ee4-4910-8913-eb7e93d899f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2047835117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2047835117
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2795386882
Short name T44
Test name
Test status
Simulation time 8072485585 ps
CPU time 866.45 seconds
Started Jul 04 04:49:15 PM PDT 24
Finished Jul 04 05:03:42 PM PDT 24
Peak memory 268744 kb
Host smart-573502e4-fb4f-4bd0-abee-780add1f626e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795386882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2795386882
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3832422137
Short name T615
Test name
Test status
Simulation time 396102156 ps
CPU time 8.15 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:49:21 PM PDT 24
Peak memory 249216 kb
Host smart-97a82739-0c27-48fa-b583-ce0705649992
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3832422137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3832422137
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2901413816
Short name T491
Test name
Test status
Simulation time 1900248568 ps
CPU time 58.46 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:50:08 PM PDT 24
Peak memory 256884 kb
Host smart-1972a577-f70f-461c-9695-fcd2820543b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29014
13816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2901413816
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.213902933
Short name T457
Test name
Test status
Simulation time 659459779 ps
CPU time 26.86 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:35 PM PDT 24
Peak memory 249104 kb
Host smart-a4c9a98a-0d05-4a80-a78c-35c0266e3106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21390
2933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.213902933
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2714082526
Short name T626
Test name
Test status
Simulation time 17925747850 ps
CPU time 857.49 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 05:03:29 PM PDT 24
Peak memory 273856 kb
Host smart-362d2050-9d7d-43e9-896e-059dfccc36c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714082526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2714082526
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3965496141
Short name T527
Test name
Test status
Simulation time 35316268457 ps
CPU time 1978.3 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 273820 kb
Host smart-fda0f7d2-d84a-4ae0-aacf-d61d1ae25c8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965496141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3965496141
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.168555456
Short name T397
Test name
Test status
Simulation time 4091330318 ps
CPU time 184.29 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:52:06 PM PDT 24
Peak memory 248908 kb
Host smart-9b8d1c9f-e7fe-475a-8ae7-6cccbdff0666
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168555456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.168555456
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2710233582
Short name T76
Test name
Test status
Simulation time 930823298 ps
CPU time 29 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:49:41 PM PDT 24
Peak memory 256672 kb
Host smart-86df463e-1868-43e9-ac76-50cf520b33ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27102
33582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2710233582
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.86191965
Short name T589
Test name
Test status
Simulation time 596784129 ps
CPU time 37.99 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:46 PM PDT 24
Peak memory 249200 kb
Host smart-006d1adf-2a0c-4777-8cfb-994ff5b4ee68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86191
965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.86191965
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3163962577
Short name T630
Test name
Test status
Simulation time 732637181 ps
CPU time 27.93 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 04:49:32 PM PDT 24
Peak memory 256748 kb
Host smart-b60d65b7-b063-4088-a069-5dc36d71bd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31639
62577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3163962577
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2472137584
Short name T671
Test name
Test status
Simulation time 225179688 ps
CPU time 22.88 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:49:35 PM PDT 24
Peak memory 257172 kb
Host smart-69b25123-9f34-4668-8448-271e0d22917e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24721
37584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2472137584
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2933500406
Short name T232
Test name
Test status
Simulation time 184892810 ps
CPU time 3.9 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:49:15 PM PDT 24
Peak memory 249420 kb
Host smart-b18a3db5-1cee-4f4b-b684-75f1bc9ba59c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2933500406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2933500406
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3745295085
Short name T622
Test name
Test status
Simulation time 10700900997 ps
CPU time 1481.45 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 289992 kb
Host smart-3fc6613c-a6c5-477c-9efb-c47c4ff9730e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745295085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3745295085
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1468812400
Short name T237
Test name
Test status
Simulation time 416553530 ps
CPU time 18.89 seconds
Started Jul 04 04:49:14 PM PDT 24
Finished Jul 04 04:49:33 PM PDT 24
Peak memory 249092 kb
Host smart-7c339af4-6040-4047-9969-ee38d5da4c20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1468812400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1468812400
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1647575530
Short name T422
Test name
Test status
Simulation time 1206991636 ps
CPU time 31.29 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:40 PM PDT 24
Peak memory 256656 kb
Host smart-303b3a9d-6f3e-42c1-95e7-1e88e8521b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16475
75530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1647575530
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2338406999
Short name T453
Test name
Test status
Simulation time 1554840221 ps
CPU time 40.79 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:49:54 PM PDT 24
Peak memory 249112 kb
Host smart-cd5ff0f2-d808-45c0-8a46-c3cba46a1cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23384
06999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2338406999
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1127321184
Short name T240
Test name
Test status
Simulation time 150278524812 ps
CPU time 2180.76 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 05:25:29 PM PDT 24
Peak memory 273788 kb
Host smart-4e519865-290c-4ece-a80d-0cf27fe837ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127321184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1127321184
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3158866949
Short name T299
Test name
Test status
Simulation time 30514593497 ps
CPU time 336.96 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 04:54:44 PM PDT 24
Peak memory 249268 kb
Host smart-e6bfad4f-c415-4a97-8dc1-41b4c297bbbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158866949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3158866949
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3697745972
Short name T533
Test name
Test status
Simulation time 4229739966 ps
CPU time 25.16 seconds
Started Jul 04 04:49:18 PM PDT 24
Finished Jul 04 04:49:43 PM PDT 24
Peak memory 256744 kb
Host smart-18005d43-2d9b-4d27-99b2-b3938061a20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36977
45972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3697745972
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.45195039
Short name T500
Test name
Test status
Simulation time 269018554 ps
CPU time 32.39 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:33 PM PDT 24
Peak memory 257320 kb
Host smart-bf0ea162-2b48-47f0-8ecd-eaef6baaf9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45195
039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.45195039
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1802505482
Short name T612
Test name
Test status
Simulation time 166265172 ps
CPU time 12.45 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:19 PM PDT 24
Peak memory 253928 kb
Host smart-55f38850-5a36-41de-a7e3-22e106d2f403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
05482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1802505482
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.324334964
Short name T621
Test name
Test status
Simulation time 805241060 ps
CPU time 52.66 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 04:49:56 PM PDT 24
Peak memory 256356 kb
Host smart-5a968370-81bf-44a1-bc7b-3d51432f98b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324334964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.324334964
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1104667283
Short name T220
Test name
Test status
Simulation time 77530823 ps
CPU time 3.33 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 249488 kb
Host smart-686e3630-56fa-41dd-8603-af47704e7603
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1104667283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1104667283
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.744558350
Short name T619
Test name
Test status
Simulation time 32465852224 ps
CPU time 1871.05 seconds
Started Jul 04 04:49:27 PM PDT 24
Finished Jul 04 05:20:38 PM PDT 24
Peak memory 273300 kb
Host smart-cdf7384c-7198-4a73-8210-cc67e284ca28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744558350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.744558350
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.270372461
Short name T245
Test name
Test status
Simulation time 465881503 ps
CPU time 21.21 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 04:49:26 PM PDT 24
Peak memory 249040 kb
Host smart-a2ccd612-b831-4939-ab7f-dfbd8b7c85dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=270372461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.270372461
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2490461002
Short name T649
Test name
Test status
Simulation time 2190554388 ps
CPU time 90.58 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:50:40 PM PDT 24
Peak memory 257000 kb
Host smart-541861e6-19d6-4b78-88a8-de2af7dd1a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24904
61002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2490461002
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3399651236
Short name T471
Test name
Test status
Simulation time 854768965 ps
CPU time 51.04 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:57 PM PDT 24
Peak memory 256136 kb
Host smart-02511e99-f6c6-4d09-b875-e3143813fb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33996
51236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3399651236
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.46137937
Short name T368
Test name
Test status
Simulation time 17330932332 ps
CPU time 1455.3 seconds
Started Jul 04 04:49:17 PM PDT 24
Finished Jul 04 05:13:33 PM PDT 24
Peak memory 290112 kb
Host smart-a1e0ca14-dfe3-4db5-a7a0-0b09db4e11a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46137937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.46137937
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.710805551
Short name T600
Test name
Test status
Simulation time 24105555874 ps
CPU time 302.08 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:54:14 PM PDT 24
Peak memory 249236 kb
Host smart-28e15b50-834e-4145-b55e-1c64e504d895
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710805551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.710805551
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.308150468
Short name T531
Test name
Test status
Simulation time 1697142939 ps
CPU time 17.89 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:26 PM PDT 24
Peak memory 248076 kb
Host smart-74187005-1142-4458-9fd1-f8e1178cc1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30815
0468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.308150468
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.4075362384
Short name T536
Test name
Test status
Simulation time 141861497 ps
CPU time 18.7 seconds
Started Jul 04 04:49:02 PM PDT 24
Finished Jul 04 04:49:21 PM PDT 24
Peak memory 249148 kb
Host smart-1711ad64-d496-40ef-bdca-2d4fbb8bede3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40753
62384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4075362384
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3339429628
Short name T430
Test name
Test status
Simulation time 1979256280 ps
CPU time 29.58 seconds
Started Jul 04 04:49:17 PM PDT 24
Finished Jul 04 04:49:46 PM PDT 24
Peak memory 257048 kb
Host smart-c594ff0d-cfcb-4e55-a977-8bb90873626e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33394
29628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3339429628
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3869580558
Short name T138
Test name
Test status
Simulation time 80380276951 ps
CPU time 2109.43 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 05:24:19 PM PDT 24
Peak memory 290068 kb
Host smart-d7436469-96a6-45d7-b877-e32efc4842f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869580558 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3869580558
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2916841714
Short name T690
Test name
Test status
Simulation time 65778757951 ps
CPU time 1083.2 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 05:07:14 PM PDT 24
Peak memory 274052 kb
Host smart-1a26cf25-8017-4d3e-afec-ee9c29d18915
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916841714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2916841714
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.349059136
Short name T508
Test name
Test status
Simulation time 1186995476 ps
CPU time 11.32 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:13 PM PDT 24
Peak memory 249572 kb
Host smart-650b6433-eb4a-42fd-bdfd-648df307acee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=349059136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.349059136
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3593619225
Short name T652
Test name
Test status
Simulation time 3407700904 ps
CPU time 233.52 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:53:06 PM PDT 24
Peak memory 251320 kb
Host smart-8c53bbd6-5738-42b7-a6e7-3755ffaf54fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35936
19225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3593619225
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.470286566
Short name T447
Test name
Test status
Simulation time 343959700 ps
CPU time 25.51 seconds
Started Jul 04 04:49:18 PM PDT 24
Finished Jul 04 04:49:44 PM PDT 24
Peak memory 248936 kb
Host smart-9ab3540c-925d-43c6-b4c7-3754cecbf418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47028
6566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.470286566
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2082642801
Short name T608
Test name
Test status
Simulation time 31427006233 ps
CPU time 785.46 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 05:02:19 PM PDT 24
Peak memory 265584 kb
Host smart-a39e70ab-3155-452b-b3ca-08855a205c75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082642801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2082642801
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2999775474
Short name T45
Test name
Test status
Simulation time 854477666 ps
CPU time 59.62 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 04:50:05 PM PDT 24
Peak memory 256912 kb
Host smart-739afb98-1425-453f-b6d6-0d7aecbf6edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29997
75474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2999775474
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3448875851
Short name T473
Test name
Test status
Simulation time 3818355840 ps
CPU time 55.43 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:50:07 PM PDT 24
Peak memory 250148 kb
Host smart-6a5d56f1-f14a-4d71-928b-269be261766b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
75851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3448875851
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2909473715
Short name T534
Test name
Test status
Simulation time 368212432 ps
CPU time 23.42 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:49:33 PM PDT 24
Peak memory 248616 kb
Host smart-abb4b5e3-df4e-4093-9099-7a829de79353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29094
73715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2909473715
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2831555255
Short name T425
Test name
Test status
Simulation time 1009602109 ps
CPU time 18.62 seconds
Started Jul 04 04:49:22 PM PDT 24
Finished Jul 04 04:49:41 PM PDT 24
Peak memory 256924 kb
Host smart-79bd4049-8b83-4666-9325-aa8738a7a3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315
55255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2831555255
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2859093481
Short name T139
Test name
Test status
Simulation time 63748004603 ps
CPU time 2519.74 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 05:31:08 PM PDT 24
Peak memory 322860 kb
Host smart-5217b2a2-e7c5-4f76-a36a-f17b548490f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859093481 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2859093481
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3547784066
Short name T227
Test name
Test status
Simulation time 213679307 ps
CPU time 3.71 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 249472 kb
Host smart-abf5556b-8a04-4a44-9102-14c2dd81b5fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3547784066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3547784066
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3957796570
Short name T16
Test name
Test status
Simulation time 1100241040 ps
CPU time 11.54 seconds
Started Jul 04 04:49:15 PM PDT 24
Finished Jul 04 04:49:27 PM PDT 24
Peak memory 249076 kb
Host smart-8f1aa027-069a-4e6a-84b9-de13a49ff3b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3957796570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3957796570
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3618204538
Short name T499
Test name
Test status
Simulation time 275329853 ps
CPU time 14.58 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:28 PM PDT 24
Peak memory 255016 kb
Host smart-b2ae1104-e54c-4b04-860f-084648d40a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36182
04538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3618204538
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.132240863
Short name T78
Test name
Test status
Simulation time 213308883 ps
CPU time 13.4 seconds
Started Jul 04 04:49:02 PM PDT 24
Finished Jul 04 04:49:16 PM PDT 24
Peak memory 249116 kb
Host smart-53c251ea-6906-4605-96f0-2669c683d9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13224
0863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.132240863
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1751316444
Short name T677
Test name
Test status
Simulation time 54550649545 ps
CPU time 1341.86 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 05:11:32 PM PDT 24
Peak memory 287740 kb
Host smart-c7ae4afb-5ba3-4653-9335-8004be389551
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751316444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1751316444
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2585611552
Short name T463
Test name
Test status
Simulation time 146882907641 ps
CPU time 2350.54 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 05:28:21 PM PDT 24
Peak memory 290068 kb
Host smart-92951cfb-f483-409a-bc2d-3de998288e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585611552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2585611552
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2217185802
Short name T538
Test name
Test status
Simulation time 29902381345 ps
CPU time 629.36 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:59:42 PM PDT 24
Peak memory 255572 kb
Host smart-d414799d-38fd-48d7-b0fe-1a4032611205
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217185802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2217185802
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.449634978
Short name T691
Test name
Test status
Simulation time 2155910411 ps
CPU time 41.37 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:49:53 PM PDT 24
Peak memory 257452 kb
Host smart-3cfe016e-6fb4-4eb4-9daa-6cae7e5de902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44963
4978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.449634978
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1538634331
Short name T468
Test name
Test status
Simulation time 1184154794 ps
CPU time 25.94 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:34 PM PDT 24
Peak memory 256628 kb
Host smart-9da27f71-ae38-42e3-9edc-cb55816fa9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15386
34331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1538634331
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1457379312
Short name T511
Test name
Test status
Simulation time 246782881 ps
CPU time 5.66 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:19 PM PDT 24
Peak memory 240200 kb
Host smart-e5c522b1-cb90-405c-89b8-ac72f9519829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14573
79312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1457379312
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1900842322
Short name T121
Test name
Test status
Simulation time 4017063051 ps
CPU time 56.37 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:50:03 PM PDT 24
Peak memory 249712 kb
Host smart-9b5b01a6-b7aa-47c4-ac3e-fbf3b69babe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19008
42322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1900842322
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1000069219
Short name T480
Test name
Test status
Simulation time 20301492826 ps
CPU time 1644.4 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 05:16:38 PM PDT 24
Peak memory 290132 kb
Host smart-c32fe8e6-3a54-4cf7-9f3a-3a5d35235429
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000069219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1000069219
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.24296054
Short name T228
Test name
Test status
Simulation time 28491452 ps
CPU time 2.56 seconds
Started Jul 04 04:49:15 PM PDT 24
Finished Jul 04 04:49:18 PM PDT 24
Peak memory 249436 kb
Host smart-acc01b13-5813-4c57-bcd7-1a78624782e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=24296054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.24296054
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3544634509
Short name T115
Test name
Test status
Simulation time 41309432680 ps
CPU time 2283.99 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 05:27:17 PM PDT 24
Peak memory 289740 kb
Host smart-004f8b58-0b82-4fe2-a3cc-ce1dbce4d3ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544634509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3544634509
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.436639372
Short name T479
Test name
Test status
Simulation time 142597798 ps
CPU time 8.58 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:49:19 PM PDT 24
Peak memory 249040 kb
Host smart-ba7a9792-247c-4cc2-aa1a-dadb46369a6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=436639372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.436639372
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.688469051
Short name T442
Test name
Test status
Simulation time 7265754221 ps
CPU time 173.44 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:52:03 PM PDT 24
Peak memory 257464 kb
Host smart-8dc3986a-dd1b-4902-870f-a2e5f55379fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68846
9051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.688469051
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.472965768
Short name T99
Test name
Test status
Simulation time 7444911453 ps
CPU time 60.42 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:50:14 PM PDT 24
Peak memory 257488 kb
Host smart-eb1d5220-37d4-424c-a89f-cdffcd5a7b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47296
5768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.472965768
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2409527979
Short name T486
Test name
Test status
Simulation time 60832003795 ps
CPU time 1376.7 seconds
Started Jul 04 04:49:14 PM PDT 24
Finished Jul 04 05:12:11 PM PDT 24
Peak memory 290168 kb
Host smart-a64667b0-d133-46cd-a23a-496f0dd8abe6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409527979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2409527979
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.530218001
Short name T47
Test name
Test status
Simulation time 7458439054 ps
CPU time 824.68 seconds
Started Jul 04 04:49:16 PM PDT 24
Finished Jul 04 05:03:01 PM PDT 24
Peak memory 273212 kb
Host smart-c96c9b62-81e8-45ef-9b67-bfc3cc8a857a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530218001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.530218001
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2127813539
Short name T507
Test name
Test status
Simulation time 4058505091 ps
CPU time 169.28 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:52:00 PM PDT 24
Peak memory 249100 kb
Host smart-c4419e72-4e28-49ad-ad09-65011d0f148a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127813539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2127813539
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3859030711
Short name T372
Test name
Test status
Simulation time 291117583 ps
CPU time 14.84 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:17 PM PDT 24
Peak memory 256676 kb
Host smart-1ffd4263-e119-4b33-8855-fef91ef89c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38590
30711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3859030711
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1969995913
Short name T555
Test name
Test status
Simulation time 1996971225 ps
CPU time 64.9 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:50:15 PM PDT 24
Peak memory 249060 kb
Host smart-84f3b922-b719-452e-aaca-80979d36f365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19699
95913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1969995913
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1108770555
Short name T584
Test name
Test status
Simulation time 1433699023 ps
CPU time 33.49 seconds
Started Jul 04 04:49:20 PM PDT 24
Finished Jul 04 04:49:53 PM PDT 24
Peak memory 248228 kb
Host smart-95bdc656-6650-4d6c-81d0-51f667b30225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11087
70555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1108770555
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2100603580
Short name T404
Test name
Test status
Simulation time 1525361839 ps
CPU time 24.61 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:49:35 PM PDT 24
Peak memory 257332 kb
Host smart-044a20c9-d233-4225-8078-9374c7445579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21006
03580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2100603580
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1331375952
Short name T654
Test name
Test status
Simulation time 11051490051 ps
CPU time 161.35 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:51:50 PM PDT 24
Peak memory 257432 kb
Host smart-be867f7c-7a85-4cac-a1d1-85696c7e5884
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331375952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1331375952
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3614146011
Short name T271
Test name
Test status
Simulation time 365568422184 ps
CPU time 10321.9 seconds
Started Jul 04 04:49:16 PM PDT 24
Finished Jul 04 07:41:19 PM PDT 24
Peak memory 394952 kb
Host smart-c397c608-a402-4022-9044-fa4501492f7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614146011 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3614146011
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3984421904
Short name T217
Test name
Test status
Simulation time 36385572 ps
CPU time 3.41 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:17 PM PDT 24
Peak memory 249440 kb
Host smart-6ed21186-7608-434f-bad3-30b2cf44cbec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3984421904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3984421904
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1772959365
Short name T116
Test name
Test status
Simulation time 104959995058 ps
CPU time 762.62 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 05:01:56 PM PDT 24
Peak memory 273880 kb
Host smart-f28457d8-b9a1-48bb-9b27-ef1315985c98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772959365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1772959365
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2920020186
Short name T550
Test name
Test status
Simulation time 419732814 ps
CPU time 19.62 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:29 PM PDT 24
Peak memory 249144 kb
Host smart-e625db08-be6b-483b-a952-c50b613d173c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2920020186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2920020186
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.301974405
Short name T253
Test name
Test status
Simulation time 9254801539 ps
CPU time 69.53 seconds
Started Jul 04 04:49:15 PM PDT 24
Finished Jul 04 04:50:25 PM PDT 24
Peak memory 256980 kb
Host smart-8df459d5-8271-4bb7-8189-c553f4e57fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197
4405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.301974405
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2561758050
Short name T576
Test name
Test status
Simulation time 2046487308 ps
CPU time 46.4 seconds
Started Jul 04 04:49:14 PM PDT 24
Finished Jul 04 04:50:01 PM PDT 24
Peak memory 249188 kb
Host smart-b4d07c35-25b9-4f09-8989-e3ebb0c22254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
58050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2561758050
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2689322085
Short name T512
Test name
Test status
Simulation time 16720614567 ps
CPU time 1056.84 seconds
Started Jul 04 04:49:21 PM PDT 24
Finished Jul 04 05:06:58 PM PDT 24
Peak memory 273792 kb
Host smart-e0d17b2b-2abd-4655-9f97-8c236e7913c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689322085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2689322085
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2592086417
Short name T582
Test name
Test status
Simulation time 239007718167 ps
CPU time 1721.97 seconds
Started Jul 04 04:49:17 PM PDT 24
Finished Jul 04 05:18:00 PM PDT 24
Peak memory 272232 kb
Host smart-c4c68086-ffa7-48b4-aad9-654d512e25dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592086417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2592086417
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1258269642
Short name T521
Test name
Test status
Simulation time 18226022184 ps
CPU time 404.99 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:55:55 PM PDT 24
Peak memory 255828 kb
Host smart-9c528be1-ca59-40b8-b0b7-9c75b9815195
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258269642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1258269642
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.745208346
Short name T518
Test name
Test status
Simulation time 19717786 ps
CPU time 2.87 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:49:15 PM PDT 24
Peak memory 240972 kb
Host smart-d898c661-25a2-4850-8381-da8a2711b43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74520
8346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.745208346
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3225013126
Short name T410
Test name
Test status
Simulation time 305916102 ps
CPU time 28.17 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:49:41 PM PDT 24
Peak memory 248992 kb
Host smart-3b9de0c2-8826-4a2b-ab9b-e9b9dee9a63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32250
13126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3225013126
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3828883110
Short name T467
Test name
Test status
Simulation time 276614735 ps
CPU time 19.66 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:49:29 PM PDT 24
Peak memory 256628 kb
Host smart-d3fce3a9-bd31-4f8e-92cd-b921feb28ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38288
83110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3828883110
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2877690458
Short name T411
Test name
Test status
Simulation time 6782734750 ps
CPU time 27.48 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:37 PM PDT 24
Peak memory 256392 kb
Host smart-15f43fa8-de47-4686-83db-491dedafcb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
90458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2877690458
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.960477164
Short name T247
Test name
Test status
Simulation time 44512311436 ps
CPU time 2987.23 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 05:39:01 PM PDT 24
Peak memory 289816 kb
Host smart-f7391dc3-c468-4b0b-80d9-75f45dfb8374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960477164 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.960477164
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2543384591
Short name T224
Test name
Test status
Simulation time 15117143 ps
CPU time 2.68 seconds
Started Jul 04 04:49:17 PM PDT 24
Finished Jul 04 04:49:20 PM PDT 24
Peak memory 249420 kb
Host smart-9aab0eca-5f43-40fa-a484-07939a31ef31
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2543384591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2543384591
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4052439776
Short name T6
Test name
Test status
Simulation time 146084167849 ps
CPU time 1696.61 seconds
Started Jul 04 04:49:14 PM PDT 24
Finished Jul 04 05:17:31 PM PDT 24
Peak memory 273592 kb
Host smart-81ed9d30-b1d3-4586-982e-f321925ab952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052439776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4052439776
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1205737847
Short name T446
Test name
Test status
Simulation time 279037304 ps
CPU time 9.08 seconds
Started Jul 04 04:49:24 PM PDT 24
Finished Jul 04 04:49:33 PM PDT 24
Peak memory 249048 kb
Host smart-3da27009-aafe-4486-bcd2-63a468d6ef4c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1205737847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1205737847
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2044813349
Short name T578
Test name
Test status
Simulation time 3191960911 ps
CPU time 92.3 seconds
Started Jul 04 04:49:27 PM PDT 24
Finished Jul 04 04:50:59 PM PDT 24
Peak memory 256996 kb
Host smart-40d9c644-2ea3-449e-acb7-1d2dbb4332f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
13349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2044813349
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4029021698
Short name T449
Test name
Test status
Simulation time 559760175 ps
CPU time 8.87 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:23 PM PDT 24
Peak memory 249040 kb
Host smart-cdbc8af9-376e-4540-b4ec-625c8a276548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40290
21698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4029021698
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.4195139642
Short name T575
Test name
Test status
Simulation time 28473396160 ps
CPU time 1103.75 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 05:07:37 PM PDT 24
Peak memory 286068 kb
Host smart-f7f620a2-80cb-4ace-a100-40ea13d1e660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195139642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.4195139642
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.191247317
Short name T697
Test name
Test status
Simulation time 143402579971 ps
CPU time 484.04 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:57:16 PM PDT 24
Peak memory 249272 kb
Host smart-ac5cb02d-84e4-4758-bcca-2feb8713f59a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191247317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.191247317
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.490597973
Short name T57
Test name
Test status
Simulation time 116692847 ps
CPU time 13.06 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:49:23 PM PDT 24
Peak memory 255632 kb
Host smart-48b48327-8a92-4d81-93d7-2ac16539b68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49059
7973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.490597973
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.924706631
Short name T107
Test name
Test status
Simulation time 708691206 ps
CPU time 43.02 seconds
Started Jul 04 04:49:27 PM PDT 24
Finished Jul 04 04:50:11 PM PDT 24
Peak memory 256892 kb
Host smart-84d2cb75-0691-4662-8a6a-2e5ff45e172e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92470
6631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.924706631
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.351369236
Short name T641
Test name
Test status
Simulation time 457427297 ps
CPU time 29.46 seconds
Started Jul 04 04:49:14 PM PDT 24
Finished Jul 04 04:49:44 PM PDT 24
Peak memory 249204 kb
Host smart-cc442011-1ff6-4c14-994e-f620fbe066a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35136
9236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.351369236
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2349387939
Short name T459
Test name
Test status
Simulation time 319210751 ps
CPU time 22.23 seconds
Started Jul 04 04:49:24 PM PDT 24
Finished Jul 04 04:49:46 PM PDT 24
Peak memory 257020 kb
Host smart-8ceddc8f-ac1c-4e2f-a50f-fc20f915c2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23493
87939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2349387939
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1315108717
Short name T51
Test name
Test status
Simulation time 3775858157 ps
CPU time 124.36 seconds
Started Jul 04 04:49:18 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 257436 kb
Host smart-1ec824ef-b934-429c-92f6-6cf51a050c83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315108717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1315108717
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.46083809
Short name T223
Test name
Test status
Simulation time 30049660 ps
CPU time 2.76 seconds
Started Jul 04 04:49:26 PM PDT 24
Finished Jul 04 04:49:29 PM PDT 24
Peak memory 249464 kb
Host smart-e39d3802-bfbc-416c-8e6c-de7f4d7aa5ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=46083809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.46083809
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3090615236
Short name T481
Test name
Test status
Simulation time 84462758131 ps
CPU time 2629.61 seconds
Started Jul 04 04:49:23 PM PDT 24
Finished Jul 04 05:33:13 PM PDT 24
Peak memory 289368 kb
Host smart-da451227-8378-41f2-9eb4-7ff403f19a73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090615236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3090615236
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.742822564
Short name T364
Test name
Test status
Simulation time 995340239 ps
CPU time 11.21 seconds
Started Jul 04 04:49:25 PM PDT 24
Finished Jul 04 04:49:37 PM PDT 24
Peak memory 249104 kb
Host smart-8668a68c-56e4-4993-8016-263482c05c07
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=742822564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.742822564
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.348466569
Short name T387
Test name
Test status
Simulation time 2873034586 ps
CPU time 149.75 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:51:42 PM PDT 24
Peak memory 257500 kb
Host smart-f376ccd7-8948-48ef-bdf6-5ead96b35e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34846
6569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.348466569
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1861174648
Short name T492
Test name
Test status
Simulation time 2615717119 ps
CPU time 79.9 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:50:33 PM PDT 24
Peak memory 257044 kb
Host smart-537f5c04-0b06-4d7c-a006-26a15c046a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18611
74648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1861174648
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4269668972
Short name T313
Test name
Test status
Simulation time 16864296416 ps
CPU time 1065.63 seconds
Started Jul 04 04:49:20 PM PDT 24
Finished Jul 04 05:07:06 PM PDT 24
Peak memory 273236 kb
Host smart-2f8fdd0a-cea2-4d94-acdb-f63a02aee9a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269668972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4269668972
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2778593670
Short name T3
Test name
Test status
Simulation time 126421297902 ps
CPU time 2192.93 seconds
Started Jul 04 04:49:32 PM PDT 24
Finished Jul 04 05:26:05 PM PDT 24
Peak memory 288008 kb
Host smart-ee436540-8197-424c-b693-daf11f86ec63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778593670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2778593670
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.793332638
Short name T43
Test name
Test status
Simulation time 24397619051 ps
CPU time 527.8 seconds
Started Jul 04 04:49:17 PM PDT 24
Finished Jul 04 04:58:05 PM PDT 24
Peak memory 249196 kb
Host smart-c735df3c-a44c-4893-b3cb-056e2e5fe6d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793332638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.793332638
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3189604151
Short name T113
Test name
Test status
Simulation time 291240919 ps
CPU time 17.75 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:49:33 PM PDT 24
Peak memory 249056 kb
Host smart-be4af0f2-e8e1-4d8f-a594-1145c848d1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
04151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3189604151
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.382020649
Short name T27
Test name
Test status
Simulation time 770173628 ps
CPU time 52.33 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:50:04 PM PDT 24
Peak memory 249184 kb
Host smart-c7132985-616e-4184-b347-10fb55865ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
0649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.382020649
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.300636975
Short name T485
Test name
Test status
Simulation time 229163436 ps
CPU time 12.2 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:49:23 PM PDT 24
Peak memory 256796 kb
Host smart-c5b9ac20-76ca-4aa1-8afa-370996f65b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30063
6975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.300636975
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1286863804
Short name T455
Test name
Test status
Simulation time 959661476 ps
CPU time 29.25 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:49:41 PM PDT 24
Peak memory 249084 kb
Host smart-0838ca8f-9643-4bfe-a427-4979a09c12bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12868
63804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1286863804
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2687345753
Short name T55
Test name
Test status
Simulation time 9892434035 ps
CPU time 231.74 seconds
Started Jul 04 04:49:22 PM PDT 24
Finished Jul 04 04:53:14 PM PDT 24
Peak memory 255028 kb
Host smart-ddbc7fe3-7564-433c-acfd-acef816be1fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687345753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2687345753
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3939535991
Short name T234
Test name
Test status
Simulation time 172249535 ps
CPU time 4.2 seconds
Started Jul 04 04:49:40 PM PDT 24
Finished Jul 04 04:49:44 PM PDT 24
Peak memory 249456 kb
Host smart-44727d49-cb25-40c3-af1e-975ebade96aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3939535991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3939535991
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3965325552
Short name T638
Test name
Test status
Simulation time 4013970743 ps
CPU time 46.45 seconds
Started Jul 04 04:49:23 PM PDT 24
Finished Jul 04 04:50:10 PM PDT 24
Peak memory 249272 kb
Host smart-dce6a923-e2c3-4cb3-bc84-e93065a4960b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3965325552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3965325552
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.507978808
Short name T470
Test name
Test status
Simulation time 1740474421 ps
CPU time 62.94 seconds
Started Jul 04 04:49:42 PM PDT 24
Finished Jul 04 04:50:45 PM PDT 24
Peak memory 257168 kb
Host smart-5d7a8f6a-950a-4a87-9bab-4fda79a934f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50797
8808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.507978808
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2635558497
Short name T564
Test name
Test status
Simulation time 164365545 ps
CPU time 3.95 seconds
Started Jul 04 04:49:26 PM PDT 24
Finished Jul 04 04:49:31 PM PDT 24
Peak memory 240920 kb
Host smart-1d461649-ee3a-49ea-b9de-9100e53d9fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26355
58497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2635558497
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2706379151
Short name T475
Test name
Test status
Simulation time 10215669276 ps
CPU time 883.85 seconds
Started Jul 04 04:49:21 PM PDT 24
Finished Jul 04 05:04:06 PM PDT 24
Peak memory 273176 kb
Host smart-19847ec4-8c3e-4258-adef-eb2d5cccfe46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706379151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2706379151
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.230437877
Short name T246
Test name
Test status
Simulation time 74355556312 ps
CPU time 2234.3 seconds
Started Jul 04 04:49:21 PM PDT 24
Finished Jul 04 05:26:36 PM PDT 24
Peak memory 273816 kb
Host smart-8105c1d1-834d-4319-a16c-14141dfa78e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230437877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.230437877
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.485210170
Short name T390
Test name
Test status
Simulation time 1033562413 ps
CPU time 49.09 seconds
Started Jul 04 04:49:29 PM PDT 24
Finished Jul 04 04:50:18 PM PDT 24
Peak memory 249176 kb
Host smart-2263addb-3555-4a22-aa88-836cfba15423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48521
0170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.485210170
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.276169416
Short name T476
Test name
Test status
Simulation time 250533585 ps
CPU time 24.86 seconds
Started Jul 04 04:49:25 PM PDT 24
Finished Jul 04 04:49:50 PM PDT 24
Peak memory 248704 kb
Host smart-0826b078-6f4c-49d5-bf40-33dfec7ea925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27616
9416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.276169416
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3880947576
Short name T21
Test name
Test status
Simulation time 3548175844 ps
CPU time 34.35 seconds
Started Jul 04 04:49:25 PM PDT 24
Finished Jul 04 04:49:59 PM PDT 24
Peak memory 248568 kb
Host smart-6412a730-d658-4213-9c69-c884a146f527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
47576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3880947576
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3872494010
Short name T684
Test name
Test status
Simulation time 1458448999 ps
CPU time 30.7 seconds
Started Jul 04 04:49:24 PM PDT 24
Finished Jul 04 04:49:54 PM PDT 24
Peak memory 249584 kb
Host smart-5f263c5d-b511-4f9e-b7c0-b4899538e6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
94010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3872494010
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.590129087
Short name T586
Test name
Test status
Simulation time 9068410805 ps
CPU time 508.59 seconds
Started Jul 04 04:49:28 PM PDT 24
Finished Jul 04 04:57:57 PM PDT 24
Peak memory 257400 kb
Host smart-f006c37c-658e-42c2-b9f4-99825d986a3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590129087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.590129087
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1211477134
Short name T596
Test name
Test status
Simulation time 69258489936 ps
CPU time 2129.95 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 05:24:31 PM PDT 24
Peak memory 289388 kb
Host smart-22e6353e-b9ae-40e8-b44f-cc066f9d28e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211477134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1211477134
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3557623611
Short name T412
Test name
Test status
Simulation time 3053131622 ps
CPU time 35.95 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:49:46 PM PDT 24
Peak memory 249292 kb
Host smart-3da59fe1-55b0-45b0-b69c-bafcb226c240
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3557623611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3557623611
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2687682302
Short name T623
Test name
Test status
Simulation time 5747165085 ps
CPU time 306.13 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:54:17 PM PDT 24
Peak memory 257004 kb
Host smart-04f9911e-0b96-47b2-83cc-1e5e0bd93931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26876
82302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2687682302
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2428986886
Short name T385
Test name
Test status
Simulation time 3629202127 ps
CPU time 48.79 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:50:02 PM PDT 24
Peak memory 256712 kb
Host smart-df867828-8a92-4cb6-beed-9ab08ea35f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24289
86886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2428986886
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2894857096
Short name T680
Test name
Test status
Simulation time 21128872863 ps
CPU time 1194.52 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 05:09:01 PM PDT 24
Peak memory 273252 kb
Host smart-bf52f3b2-76bf-40fb-9f75-c13a7b2c5974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894857096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2894857096
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1360587917
Short name T525
Test name
Test status
Simulation time 68581877249 ps
CPU time 1286.51 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 05:10:38 PM PDT 24
Peak memory 290032 kb
Host smart-4df35cd2-d81f-4f7b-9bb2-ee1a65482aab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360587917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1360587917
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2869036491
Short name T620
Test name
Test status
Simulation time 9242689426 ps
CPU time 342.52 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:54:56 PM PDT 24
Peak memory 249276 kb
Host smart-fee5410b-81c4-4897-8ce8-dacd3738256b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869036491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2869036491
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3920141303
Short name T406
Test name
Test status
Simulation time 31343088 ps
CPU time 6.05 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:49:04 PM PDT 24
Peak memory 249164 kb
Host smart-a35b1941-09b9-4ef2-bfa2-c19a61777f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39201
41303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3920141303
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2586082413
Short name T464
Test name
Test status
Simulation time 302565185 ps
CPU time 21.69 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 04:49:27 PM PDT 24
Peak memory 249176 kb
Host smart-8c5631a0-2b33-4471-af7a-b6026da2c779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25860
82413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2586082413
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1404783802
Short name T42
Test name
Test status
Simulation time 2216148870 ps
CPU time 62.56 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:50:17 PM PDT 24
Peak memory 257452 kb
Host smart-10cac8d2-7ab2-4352-bf1e-b61fb48ba71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14047
83802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1404783802
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1341420641
Short name T379
Test name
Test status
Simulation time 11694563316 ps
CPU time 105.9 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:50:43 PM PDT 24
Peak memory 257468 kb
Host smart-cf69b0a6-f083-4aca-a9f4-dca786ffd900
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341420641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1341420641
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3658979820
Short name T263
Test name
Test status
Simulation time 48987024082 ps
CPU time 2919.98 seconds
Started Jul 04 04:49:28 PM PDT 24
Finished Jul 04 05:38:08 PM PDT 24
Peak memory 289324 kb
Host smart-37aa8e13-bc83-4dbd-b103-b359118edd4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658979820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3658979820
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.621240631
Short name T369
Test name
Test status
Simulation time 1450038971 ps
CPU time 109.45 seconds
Started Jul 04 04:49:29 PM PDT 24
Finished Jul 04 04:51:19 PM PDT 24
Peak memory 256856 kb
Host smart-22bc361c-c105-4b22-bdf7-26872fe5acbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62124
0631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.621240631
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3347340488
Short name T644
Test name
Test status
Simulation time 437965556 ps
CPU time 25.89 seconds
Started Jul 04 04:49:37 PM PDT 24
Finished Jul 04 04:50:03 PM PDT 24
Peak memory 256668 kb
Host smart-c5c1da2f-c312-4c89-8b43-b776ed2615c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
40488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3347340488
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4251981487
Short name T321
Test name
Test status
Simulation time 81063169292 ps
CPU time 2147.34 seconds
Started Jul 04 04:49:32 PM PDT 24
Finished Jul 04 05:25:20 PM PDT 24
Peak memory 282020 kb
Host smart-d2f968a1-d4a3-4a05-bdc5-a54d75aea5a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251981487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4251981487
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2233368655
Short name T482
Test name
Test status
Simulation time 73700814456 ps
CPU time 1120.81 seconds
Started Jul 04 04:49:41 PM PDT 24
Finished Jul 04 05:08:22 PM PDT 24
Peak memory 265652 kb
Host smart-18fc576b-dfdc-41b6-9209-88e36f2c68d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233368655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2233368655
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.944136492
Short name T20
Test name
Test status
Simulation time 2741258254 ps
CPU time 38.76 seconds
Started Jul 04 04:49:30 PM PDT 24
Finished Jul 04 04:50:09 PM PDT 24
Peak memory 249236 kb
Host smart-edc5cf4d-9a66-4a42-8eee-b6fe23d2e1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94413
6492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.944136492
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1570091667
Short name T18
Test name
Test status
Simulation time 166079062 ps
CPU time 5.53 seconds
Started Jul 04 04:49:33 PM PDT 24
Finished Jul 04 04:49:38 PM PDT 24
Peak memory 248484 kb
Host smart-5cbcc30b-d3da-4fa3-bb85-a20926b594ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15700
91667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1570091667
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3104267175
Short name T285
Test name
Test status
Simulation time 407373832 ps
CPU time 29.3 seconds
Started Jul 04 04:49:30 PM PDT 24
Finished Jul 04 04:49:59 PM PDT 24
Peak memory 249092 kb
Host smart-004c5bf8-ddb1-4183-9a97-52e5e1b28432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31042
67175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3104267175
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.65560186
Short name T359
Test name
Test status
Simulation time 1723061182 ps
CPU time 21.51 seconds
Started Jul 04 04:49:29 PM PDT 24
Finished Jul 04 04:49:51 PM PDT 24
Peak memory 256180 kb
Host smart-c00f4f13-383f-4750-9e88-9e2db0d3a29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65560
186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.65560186
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1509971466
Short name T429
Test name
Test status
Simulation time 576598504270 ps
CPU time 3166.55 seconds
Started Jul 04 04:49:42 PM PDT 24
Finished Jul 04 05:42:29 PM PDT 24
Peak memory 290184 kb
Host smart-e46d6a84-d43d-4ec6-aa77-428709890997
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509971466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1509971466
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2709340866
Short name T129
Test name
Test status
Simulation time 101305862630 ps
CPU time 1994.13 seconds
Started Jul 04 04:49:31 PM PDT 24
Finished Jul 04 05:22:45 PM PDT 24
Peak memory 290292 kb
Host smart-c377bfaf-2ad1-4d0d-a857-d255196c7b39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709340866 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2709340866
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.4234782508
Short name T618
Test name
Test status
Simulation time 29509038021 ps
CPU time 2049.9 seconds
Started Jul 04 04:49:43 PM PDT 24
Finished Jul 04 05:23:53 PM PDT 24
Peak memory 286488 kb
Host smart-d5657151-62cb-403f-9d7e-99ab72ee749f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234782508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4234782508
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4103127040
Short name T407
Test name
Test status
Simulation time 14380923971 ps
CPU time 233.22 seconds
Started Jul 04 04:49:41 PM PDT 24
Finished Jul 04 04:53:34 PM PDT 24
Peak memory 256860 kb
Host smart-38bd5825-560b-4e5c-a512-1a82e9777972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031
27040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4103127040
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1218865404
Short name T658
Test name
Test status
Simulation time 2247566319 ps
CPU time 40.11 seconds
Started Jul 04 04:49:35 PM PDT 24
Finished Jul 04 04:50:16 PM PDT 24
Peak memory 257492 kb
Host smart-ddea32a5-e6fc-456b-b205-7932e25ac0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
65404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1218865404
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.940431267
Short name T14
Test name
Test status
Simulation time 37557002982 ps
CPU time 856.25 seconds
Started Jul 04 04:49:38 PM PDT 24
Finished Jul 04 05:03:54 PM PDT 24
Peak memory 273832 kb
Host smart-cca7d202-09b8-48fe-a2a8-dd5e61e46341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940431267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.940431267
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3434399450
Short name T310
Test name
Test status
Simulation time 8804705576 ps
CPU time 183.44 seconds
Started Jul 04 04:49:39 PM PDT 24
Finished Jul 04 04:52:43 PM PDT 24
Peak memory 249260 kb
Host smart-25942ed3-4d0e-47e3-a38b-6407aa01958d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434399450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3434399450
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.321315020
Short name T75
Test name
Test status
Simulation time 964844561 ps
CPU time 15.5 seconds
Started Jul 04 04:49:24 PM PDT 24
Finished Jul 04 04:49:39 PM PDT 24
Peak memory 249120 kb
Host smart-09d45fdc-cc48-403c-a284-66fb88c4a1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32131
5020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.321315020
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1989986852
Short name T125
Test name
Test status
Simulation time 3168784943 ps
CPU time 53.96 seconds
Started Jul 04 04:49:34 PM PDT 24
Finished Jul 04 04:50:28 PM PDT 24
Peak memory 249140 kb
Host smart-d4c09fca-26c7-47d7-aae8-08275400918d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899
86852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1989986852
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.150207628
Short name T206
Test name
Test status
Simulation time 236918590 ps
CPU time 12.35 seconds
Started Jul 04 04:49:33 PM PDT 24
Finished Jul 04 04:49:46 PM PDT 24
Peak memory 249120 kb
Host smart-f4cf5fc6-ea35-4140-b7ea-8b104aed1bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15020
7628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.150207628
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2023498640
Short name T683
Test name
Test status
Simulation time 427630524 ps
CPU time 12.52 seconds
Started Jul 04 04:49:37 PM PDT 24
Finished Jul 04 04:49:49 PM PDT 24
Peak memory 256672 kb
Host smart-1d0cd15b-ce5b-4392-b6a9-059bbff600af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20234
98640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2023498640
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3511814243
Short name T571
Test name
Test status
Simulation time 19760963930 ps
CPU time 1041.2 seconds
Started Jul 04 04:49:39 PM PDT 24
Finished Jul 04 05:07:00 PM PDT 24
Peak memory 283140 kb
Host smart-28153003-a7a6-4000-b86e-e750c45c7e1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511814243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3511814243
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.840210503
Short name T607
Test name
Test status
Simulation time 1976994668 ps
CPU time 156.91 seconds
Started Jul 04 04:49:33 PM PDT 24
Finished Jul 04 04:52:10 PM PDT 24
Peak memory 257304 kb
Host smart-293b98c1-d717-48dc-9d55-1b2b0c7003ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84021
0503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.840210503
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2735702101
Short name T693
Test name
Test status
Simulation time 1252218142 ps
CPU time 39.14 seconds
Started Jul 04 04:49:39 PM PDT 24
Finished Jul 04 04:50:19 PM PDT 24
Peak memory 249112 kb
Host smart-65ed0840-6be7-4411-a8f4-29dce572953f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27357
02101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2735702101
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.791662318
Short name T333
Test name
Test status
Simulation time 8167706646 ps
CPU time 810.89 seconds
Started Jul 04 04:49:33 PM PDT 24
Finished Jul 04 05:03:04 PM PDT 24
Peak memory 273800 kb
Host smart-657c6563-8e32-4896-8ec6-e4e8427aabf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791662318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.791662318
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.377629686
Short name T413
Test name
Test status
Simulation time 19173806025 ps
CPU time 1319.88 seconds
Started Jul 04 04:49:37 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 290280 kb
Host smart-53a69de9-dad3-4bde-84bb-09d810214f91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377629686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.377629686
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2971165643
Short name T311
Test name
Test status
Simulation time 10904982246 ps
CPU time 456.07 seconds
Started Jul 04 04:49:37 PM PDT 24
Finished Jul 04 04:57:14 PM PDT 24
Peak memory 249288 kb
Host smart-8fe3526a-f68d-4804-a7ce-61d0838adc19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971165643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2971165643
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3672831560
Short name T667
Test name
Test status
Simulation time 302432255 ps
CPU time 19.4 seconds
Started Jul 04 04:49:38 PM PDT 24
Finished Jul 04 04:49:57 PM PDT 24
Peak memory 249216 kb
Host smart-5d29a755-eadf-495a-b553-6ae3be2c8761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36728
31560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3672831560
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1009577245
Short name T435
Test name
Test status
Simulation time 4167247189 ps
CPU time 59.66 seconds
Started Jul 04 04:49:39 PM PDT 24
Finished Jul 04 04:50:39 PM PDT 24
Peak memory 249340 kb
Host smart-47a28a44-8eb7-4373-862f-f3b71403ef09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10095
77245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1009577245
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.120376050
Short name T676
Test name
Test status
Simulation time 165500001 ps
CPU time 17.57 seconds
Started Jul 04 04:49:35 PM PDT 24
Finished Jul 04 04:49:52 PM PDT 24
Peak memory 248688 kb
Host smart-b11881b4-3df4-444e-b667-7035a8f3e826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037
6050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.120376050
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.614520059
Short name T267
Test name
Test status
Simulation time 468368939 ps
CPU time 20.24 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 04:50:07 PM PDT 24
Peak memory 249172 kb
Host smart-6e10150a-ead8-413e-83aa-bb79558dfc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61452
0059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.614520059
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2398068206
Short name T461
Test name
Test status
Simulation time 48899963787 ps
CPU time 890.46 seconds
Started Jul 04 04:49:42 PM PDT 24
Finished Jul 04 05:04:33 PM PDT 24
Peak memory 272052 kb
Host smart-7487ca19-d12a-432e-a209-d6db3ebd0562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398068206 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2398068206
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3030229200
Short name T84
Test name
Test status
Simulation time 76937149540 ps
CPU time 2430.46 seconds
Started Jul 04 04:49:44 PM PDT 24
Finished Jul 04 05:30:15 PM PDT 24
Peak memory 289396 kb
Host smart-9fb28982-337f-4c6d-a6c6-85b80ddb8eec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030229200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3030229200
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3601788004
Short name T362
Test name
Test status
Simulation time 97368303 ps
CPU time 4.5 seconds
Started Jul 04 04:49:39 PM PDT 24
Finished Jul 04 04:49:43 PM PDT 24
Peak memory 240296 kb
Host smart-250f8ea7-259f-4612-88c0-62ee4d976706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36017
88004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3601788004
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1443791301
Short name T503
Test name
Test status
Simulation time 3097856116 ps
CPU time 50.69 seconds
Started Jul 04 04:49:42 PM PDT 24
Finished Jul 04 04:50:33 PM PDT 24
Peak memory 256496 kb
Host smart-701b6d72-0131-4a82-9a7f-8886057127e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14437
91301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1443791301
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1535595074
Short name T546
Test name
Test status
Simulation time 43493569695 ps
CPU time 2418.25 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 05:30:05 PM PDT 24
Peak memory 284448 kb
Host smart-8882cd59-f113-462f-a65f-c50378d76ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535595074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1535595074
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1714360906
Short name T434
Test name
Test status
Simulation time 52357596963 ps
CPU time 822.02 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 05:03:28 PM PDT 24
Peak memory 273660 kb
Host smart-97e957e5-71ee-43c0-aacd-23a6c189a866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714360906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1714360906
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.720130252
Short name T574
Test name
Test status
Simulation time 618514714 ps
CPU time 49.83 seconds
Started Jul 04 04:49:33 PM PDT 24
Finished Jul 04 04:50:23 PM PDT 24
Peak memory 256572 kb
Host smart-6a6a3300-dc47-4c47-9ac6-8b653a2d2f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72013
0252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.720130252
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.440328898
Short name T663
Test name
Test status
Simulation time 1667601841 ps
CPU time 44.64 seconds
Started Jul 04 04:49:41 PM PDT 24
Finished Jul 04 04:50:26 PM PDT 24
Peak memory 248560 kb
Host smart-0068d07a-3ef3-4d7a-a4cd-2c04c8c66566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44032
8898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.440328898
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.141080531
Short name T610
Test name
Test status
Simulation time 122328647 ps
CPU time 9.86 seconds
Started Jul 04 04:49:37 PM PDT 24
Finished Jul 04 04:49:47 PM PDT 24
Peak memory 248600 kb
Host smart-0574edf1-d73d-47ae-adaf-edc35d1dea52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14108
0531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.141080531
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.836399549
Short name T358
Test name
Test status
Simulation time 1131206666 ps
CPU time 21.48 seconds
Started Jul 04 04:49:33 PM PDT 24
Finished Jul 04 04:49:55 PM PDT 24
Peak memory 249584 kb
Host smart-23167ca2-32a5-44bd-aafd-b079a982423f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83639
9549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.836399549
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2893329943
Short name T100
Test name
Test status
Simulation time 46389197231 ps
CPU time 920.9 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 05:05:07 PM PDT 24
Peak memory 273984 kb
Host smart-d414d356-3f73-4c21-8820-946e7195be89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893329943 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2893329943
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.962926834
Short name T282
Test name
Test status
Simulation time 98843206966 ps
CPU time 2837 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 05:37:03 PM PDT 24
Peak memory 290216 kb
Host smart-f9eca327-1af4-408b-b605-30fd6b3bc45e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962926834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.962926834
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.4234017579
Short name T109
Test name
Test status
Simulation time 8729367857 ps
CPU time 70.97 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 04:51:00 PM PDT 24
Peak memory 257460 kb
Host smart-e0fd6893-0b5d-4132-ad53-090ef8d1ad69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42340
17579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.4234017579
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1529781587
Short name T628
Test name
Test status
Simulation time 818988591 ps
CPU time 23.73 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 04:50:17 PM PDT 24
Peak memory 249620 kb
Host smart-7a13cd67-0f15-48e5-8a79-240501937e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15297
81587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1529781587
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4246726031
Short name T322
Test name
Test status
Simulation time 90060880459 ps
CPU time 2558.57 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 05:32:24 PM PDT 24
Peak memory 289488 kb
Host smart-81de34d5-fd86-4067-903b-94dc3d7d3705
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246726031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4246726031
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3233973623
Short name T130
Test name
Test status
Simulation time 31209232319 ps
CPU time 1711.01 seconds
Started Jul 04 04:49:41 PM PDT 24
Finished Jul 04 05:18:13 PM PDT 24
Peak memory 289904 kb
Host smart-bfda3696-f8d3-41ae-985a-ba95e8e69d19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233973623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3233973623
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3392352868
Short name T302
Test name
Test status
Simulation time 5184892564 ps
CPU time 207.27 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 04:53:13 PM PDT 24
Peak memory 249292 kb
Host smart-30f014b1-d438-4509-a4be-08640ce9c499
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392352868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3392352868
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.671580181
Short name T360
Test name
Test status
Simulation time 742298868 ps
CPU time 30.02 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 04:50:17 PM PDT 24
Peak memory 256688 kb
Host smart-1696dc38-93b6-4d2d-a994-90cad1a30c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67158
0181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.671580181
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.920848633
Short name T431
Test name
Test status
Simulation time 93333042 ps
CPU time 13.08 seconds
Started Jul 04 04:49:44 PM PDT 24
Finished Jul 04 04:49:57 PM PDT 24
Peak memory 249108 kb
Host smart-83bddcd6-4a90-48a7-9c7a-21e8e4138d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92084
8633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.920848633
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2205422423
Short name T592
Test name
Test status
Simulation time 3793455363 ps
CPU time 68.18 seconds
Started Jul 04 04:49:41 PM PDT 24
Finished Jul 04 04:50:50 PM PDT 24
Peak memory 256500 kb
Host smart-cb74a8d6-4a7f-46a6-acc3-38ad0d9b89ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22054
22423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2205422423
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.823848922
Short name T256
Test name
Test status
Simulation time 23997487250 ps
CPU time 1353.12 seconds
Started Jul 04 04:49:47 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 265628 kb
Host smart-1534a29e-ba80-434f-81e1-3065fa6fb998
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823848922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.823848922
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.246052393
Short name T532
Test name
Test status
Simulation time 5253378673 ps
CPU time 201.83 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 04:53:08 PM PDT 24
Peak memory 257420 kb
Host smart-6367811f-548c-4ba0-9edd-e9177e07f449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24605
2393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.246052393
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.91321087
Short name T355
Test name
Test status
Simulation time 10939144053 ps
CPU time 42.42 seconds
Started Jul 04 04:49:43 PM PDT 24
Finished Jul 04 04:50:25 PM PDT 24
Peak memory 257492 kb
Host smart-9db69032-f3ee-4839-9f77-9a6ae2a890d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91321
087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.91321087
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1910083729
Short name T334
Test name
Test status
Simulation time 185610046226 ps
CPU time 2713.41 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 05:35:07 PM PDT 24
Peak memory 289572 kb
Host smart-7f4084bb-0e34-43e7-b247-72b02fd2f0eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910083729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1910083729
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.559054428
Short name T462
Test name
Test status
Simulation time 169583207166 ps
CPU time 2438.04 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 05:30:25 PM PDT 24
Peak memory 290148 kb
Host smart-f6235413-7de0-43bd-9cba-49211ae61296
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559054428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.559054428
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.181427858
Short name T603
Test name
Test status
Simulation time 7958343239 ps
CPU time 314.39 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 04:54:59 PM PDT 24
Peak memory 249064 kb
Host smart-78e2ce22-0b6f-423d-86c5-b93ae81bd66b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181427858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.181427858
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1878873244
Short name T373
Test name
Test status
Simulation time 751479850 ps
CPU time 51.73 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 04:50:38 PM PDT 24
Peak memory 257300 kb
Host smart-c487d24c-0eaa-43e7-8774-9151222d98a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18788
73244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1878873244
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3005486928
Short name T255
Test name
Test status
Simulation time 279633443 ps
CPU time 24.54 seconds
Started Jul 04 04:49:42 PM PDT 24
Finished Jul 04 04:50:07 PM PDT 24
Peak memory 257292 kb
Host smart-dfe73654-d8d8-49fb-84f5-de7a88af69da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30054
86928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3005486928
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.593872895
Short name T632
Test name
Test status
Simulation time 447241170 ps
CPU time 17.16 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 04:50:10 PM PDT 24
Peak memory 248752 kb
Host smart-561d408b-e1b6-437d-9008-88307f23089a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59387
2895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.593872895
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1043888143
Short name T66
Test name
Test status
Simulation time 79801583 ps
CPU time 11.23 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 04:50:01 PM PDT 24
Peak memory 257044 kb
Host smart-4a8a77f3-83d8-494d-af7c-2326f2cc5f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10438
88143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1043888143
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1674509622
Short name T639
Test name
Test status
Simulation time 183223647154 ps
CPU time 1327.45 seconds
Started Jul 04 04:49:42 PM PDT 24
Finished Jul 04 05:11:50 PM PDT 24
Peak memory 287068 kb
Host smart-5f3e0572-149d-4e7d-89b0-7136060184e1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674509622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1674509622
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.967692084
Short name T496
Test name
Test status
Simulation time 24503141938 ps
CPU time 1418.52 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 05:13:27 PM PDT 24
Peak memory 273800 kb
Host smart-92254694-dd56-47e6-8db7-f4f8fae44778
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967692084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.967692084
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2002218670
Short name T537
Test name
Test status
Simulation time 1234501836 ps
CPU time 45.04 seconds
Started Jul 04 04:49:44 PM PDT 24
Finished Jul 04 04:50:29 PM PDT 24
Peak memory 256884 kb
Host smart-4424989d-1487-4c68-9a3b-b22cc264a006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20022
18670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2002218670
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2540352359
Short name T293
Test name
Test status
Simulation time 5698427784 ps
CPU time 53.15 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 04:50:38 PM PDT 24
Peak memory 249304 kb
Host smart-7db65e97-cf46-4ea7-90ac-1bb9c01618f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25403
52359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2540352359
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.93787140
Short name T681
Test name
Test status
Simulation time 32872569455 ps
CPU time 2098.81 seconds
Started Jul 04 04:49:43 PM PDT 24
Finished Jul 04 05:24:42 PM PDT 24
Peak memory 283476 kb
Host smart-266a32c9-41f9-46ad-ace4-29d6b401fbd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93787140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.93787140
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.273886328
Short name T243
Test name
Test status
Simulation time 153797307149 ps
CPU time 2184.18 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 05:26:17 PM PDT 24
Peak memory 282032 kb
Host smart-4e32d85a-7cc6-4a6a-8083-e19c5593e4d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273886328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.273886328
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3667139116
Short name T303
Test name
Test status
Simulation time 50941454026 ps
CPU time 528.37 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 04:58:37 PM PDT 24
Peak memory 249216 kb
Host smart-b441f78c-70e5-4f66-82e8-854e6e21a9fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667139116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3667139116
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1617653650
Short name T542
Test name
Test status
Simulation time 503856812 ps
CPU time 20.65 seconds
Started Jul 04 04:49:46 PM PDT 24
Finished Jul 04 04:50:07 PM PDT 24
Peak memory 256576 kb
Host smart-1b6f7416-8f10-4f75-a31e-315596d584d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176
53650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1617653650
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2038144314
Short name T85
Test name
Test status
Simulation time 3230658320 ps
CPU time 47.53 seconds
Started Jul 04 04:49:50 PM PDT 24
Finished Jul 04 04:50:37 PM PDT 24
Peak memory 256936 kb
Host smart-fb3ec71e-4596-425a-9b49-dfbeaf995c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20381
44314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2038144314
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2271755170
Short name T524
Test name
Test status
Simulation time 118031368 ps
CPU time 16.33 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 04:50:09 PM PDT 24
Peak memory 256772 kb
Host smart-d9db5cd8-a9e3-4271-a924-601867316f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717
55170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2271755170
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.624140609
Short name T559
Test name
Test status
Simulation time 81053325 ps
CPU time 14.26 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 04:50:03 PM PDT 24
Peak memory 255380 kb
Host smart-a78079dd-f263-4c64-af4a-e926102ad92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62414
0609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.624140609
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3391269111
Short name T291
Test name
Test status
Simulation time 4518395810 ps
CPU time 460.36 seconds
Started Jul 04 04:49:50 PM PDT 24
Finished Jul 04 04:57:31 PM PDT 24
Peak memory 265692 kb
Host smart-822d5139-71a6-4038-972b-6c51e96cbfbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391269111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3391269111
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.586388719
Short name T249
Test name
Test status
Simulation time 18178381205 ps
CPU time 1093.12 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 05:08:05 PM PDT 24
Peak memory 272748 kb
Host smart-bca16ba6-20f8-48cb-8ec5-20b5e06640e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586388719 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.586388719
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3388879588
Short name T679
Test name
Test status
Simulation time 96955675250 ps
CPU time 1559.92 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 05:15:45 PM PDT 24
Peak memory 273520 kb
Host smart-c3fe633b-a7f3-4831-adf3-d03e2e1ace6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388879588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3388879588
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.326149404
Short name T579
Test name
Test status
Simulation time 2909986890 ps
CPU time 41.62 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 04:50:30 PM PDT 24
Peak memory 257400 kb
Host smart-1cd467e4-383b-49d4-aee9-c4c5125cf5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32614
9404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.326149404
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3120596890
Short name T445
Test name
Test status
Simulation time 1209084808 ps
CPU time 19.87 seconds
Started Jul 04 04:49:44 PM PDT 24
Finished Jul 04 04:50:04 PM PDT 24
Peak memory 256332 kb
Host smart-edfc0a25-031c-44a6-ad87-6060689d7cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31205
96890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3120596890
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.126806448
Short name T659
Test name
Test status
Simulation time 33381225999 ps
CPU time 794.86 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 05:03:03 PM PDT 24
Peak memory 273440 kb
Host smart-11f33fca-838a-4d58-a287-2c540dc1916c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126806448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.126806448
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3544278811
Short name T506
Test name
Test status
Simulation time 128992641149 ps
CPU time 1896.41 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 289192 kb
Host smart-66ed22c0-d7ac-4c04-915d-2b35f00ae9e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544278811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3544278811
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3902688394
Short name T264
Test name
Test status
Simulation time 19190174615 ps
CPU time 192.18 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:53:05 PM PDT 24
Peak memory 249112 kb
Host smart-cb9fb94b-eb38-4027-a394-33f8a28b8c98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902688394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3902688394
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1496499439
Short name T606
Test name
Test status
Simulation time 418661028 ps
CPU time 32.26 seconds
Started Jul 04 04:49:43 PM PDT 24
Finished Jul 04 04:50:16 PM PDT 24
Peak memory 257252 kb
Host smart-1483fd72-a24a-43cb-b96b-0493e5b3633c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14964
99439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1496499439
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.850286748
Short name T416
Test name
Test status
Simulation time 657409074 ps
CPU time 32.66 seconds
Started Jul 04 04:49:43 PM PDT 24
Finished Jul 04 04:50:16 PM PDT 24
Peak memory 249168 kb
Host smart-872de84a-34ef-4aae-8271-eee83e54ca05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85028
6748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.850286748
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3105964598
Short name T587
Test name
Test status
Simulation time 756429536 ps
CPU time 21.21 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 04:50:11 PM PDT 24
Peak memory 249172 kb
Host smart-0c57650d-39e3-41b4-b264-56c2fac658a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31059
64598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3105964598
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1601293748
Short name T557
Test name
Test status
Simulation time 363779484 ps
CPU time 9.41 seconds
Started Jul 04 04:49:45 PM PDT 24
Finished Jul 04 04:49:55 PM PDT 24
Peak memory 249080 kb
Host smart-f3f1640c-2ab7-4fae-933e-46f79c894492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16012
93748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1601293748
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1235495593
Short name T443
Test name
Test status
Simulation time 8811111263 ps
CPU time 1120.6 seconds
Started Jul 04 04:49:50 PM PDT 24
Finished Jul 04 05:08:31 PM PDT 24
Peak memory 287256 kb
Host smart-e8e2602a-e5e6-48e1-9b22-3cdd847a9776
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235495593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1235495593
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.487528628
Short name T670
Test name
Test status
Simulation time 134673828 ps
CPU time 3.68 seconds
Started Jul 04 04:49:51 PM PDT 24
Finished Jul 04 04:49:55 PM PDT 24
Peak memory 240180 kb
Host smart-c2a339ce-e2be-4f1c-8010-f7e339f01870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48752
8628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.487528628
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.518450153
Short name T112
Test name
Test status
Simulation time 125284404 ps
CPU time 12.61 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 04:50:06 PM PDT 24
Peak memory 256440 kb
Host smart-35168855-2599-4ef3-abb5-0528f0d93d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51845
0153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.518450153
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3354123257
Short name T317
Test name
Test status
Simulation time 59576003936 ps
CPU time 1258.03 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 05:10:54 PM PDT 24
Peak memory 285380 kb
Host smart-3805e0cd-849b-41a0-ac0b-c77593ce6798
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354123257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3354123257
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2136785280
Short name T645
Test name
Test status
Simulation time 49516823693 ps
CPU time 1404.33 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 05:13:19 PM PDT 24
Peak memory 290056 kb
Host smart-594a242f-7b03-4ff7-95a6-1a7acfbaa99d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136785280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2136785280
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.641163865
Short name T374
Test name
Test status
Simulation time 78447606 ps
CPU time 12.87 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 04:50:06 PM PDT 24
Peak memory 249152 kb
Host smart-449b5fc7-09be-4bc3-af32-1314c2ab746d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64116
3865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.641163865
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.574438134
Short name T98
Test name
Test status
Simulation time 1889942470 ps
CPU time 36.3 seconds
Started Jul 04 04:49:51 PM PDT 24
Finished Jul 04 04:50:28 PM PDT 24
Peak memory 257092 kb
Host smart-071267d0-0860-451b-bf8a-5139ffa6a27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57443
8134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.574438134
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1983325771
Short name T399
Test name
Test status
Simulation time 233749833 ps
CPU time 10.48 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 04:49:59 PM PDT 24
Peak memory 253760 kb
Host smart-ff8304cb-87de-4dca-b216-8739195028c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
25771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1983325771
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4219822792
Short name T365
Test name
Test status
Simulation time 861370594 ps
CPU time 54.32 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 04:50:44 PM PDT 24
Peak memory 257028 kb
Host smart-de3bfb62-6027-4afd-a64e-107be2572ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42198
22792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4219822792
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1864950794
Short name T478
Test name
Test status
Simulation time 2232285049 ps
CPU time 64.34 seconds
Started Jul 04 04:49:51 PM PDT 24
Finished Jul 04 04:50:56 PM PDT 24
Peak memory 257484 kb
Host smart-2cedc689-9526-4769-8f1f-5096bbbcc52c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864950794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1864950794
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1541372073
Short name T133
Test name
Test status
Simulation time 26987509033 ps
CPU time 1818.94 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 05:20:08 PM PDT 24
Peak memory 273800 kb
Host smart-50b41e5e-acc1-4482-9761-efac73449036
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541372073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1541372073
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3925701185
Short name T688
Test name
Test status
Simulation time 3673647540 ps
CPU time 264.35 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:54:17 PM PDT 24
Peak memory 257108 kb
Host smart-24cd9c14-e0a8-4fdb-8c2f-776ab161e660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39257
01185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3925701185
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.412381309
Short name T325
Test name
Test status
Simulation time 67952111723 ps
CPU time 1544.95 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 282348 kb
Host smart-b8a647c8-2f3c-4ce9-aede-32362df2a549
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412381309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.412381309
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2018017300
Short name T380
Test name
Test status
Simulation time 40108762239 ps
CPU time 956.75 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 05:05:53 PM PDT 24
Peak memory 273872 kb
Host smart-b89d05e1-c134-42b2-97cb-6e420ae64d0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018017300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2018017300
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3368364805
Short name T71
Test name
Test status
Simulation time 24596334076 ps
CPU time 313.23 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:55:05 PM PDT 24
Peak memory 256320 kb
Host smart-bddca8bd-9db4-4e27-9736-abfcdce6036f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368364805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3368364805
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.704793838
Short name T631
Test name
Test status
Simulation time 1340838269 ps
CPU time 23.11 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 04:50:13 PM PDT 24
Peak memory 255836 kb
Host smart-73201c8d-8fa9-47fd-be55-de4015fe117f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70479
3838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.704793838
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.4288698448
Short name T261
Test name
Test status
Simulation time 15157039912 ps
CPU time 72.58 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 04:51:06 PM PDT 24
Peak memory 256212 kb
Host smart-ec877bf9-c7ad-4892-a2cf-b7b65cb2ab87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42886
98448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4288698448
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2544863169
Short name T259
Test name
Test status
Simulation time 510306650 ps
CPU time 32.44 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 04:50:21 PM PDT 24
Peak memory 249108 kb
Host smart-2123aadc-95b0-4f02-b698-610c17e062e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
63169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2544863169
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1694553045
Short name T388
Test name
Test status
Simulation time 1379571791 ps
CPU time 44.3 seconds
Started Jul 04 04:50:00 PM PDT 24
Finished Jul 04 04:50:45 PM PDT 24
Peak memory 257324 kb
Host smart-35662967-d969-4a2d-9ae0-5a4672bec87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16945
53045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1694553045
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1454458195
Short name T250
Test name
Test status
Simulation time 84937568359 ps
CPU time 4924.09 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 06:11:54 PM PDT 24
Peak memory 289512 kb
Host smart-74496362-48d8-4405-98f3-ebe813600009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454458195 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1454458195
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1725409503
Short name T72
Test name
Test status
Simulation time 183568821 ps
CPU time 3.42 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:17 PM PDT 24
Peak memory 249476 kb
Host smart-52a3d192-d6e2-4637-a065-b2da0782f789
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1725409503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1725409503
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1864761937
Short name T617
Test name
Test status
Simulation time 1701347012 ps
CPU time 21.56 seconds
Started Jul 04 04:49:17 PM PDT 24
Finished Jul 04 04:49:38 PM PDT 24
Peak memory 249096 kb
Host smart-5b7e8d1a-2540-4478-b7b9-f2e980685dc7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1864761937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1864761937
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.132820377
Short name T251
Test name
Test status
Simulation time 10476630662 ps
CPU time 125.52 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:51:10 PM PDT 24
Peak memory 251304 kb
Host smart-a9fb6500-a412-4016-b7a7-9633f1469794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13282
0377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.132820377
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2830421740
Short name T570
Test name
Test status
Simulation time 936232372 ps
CPU time 31.55 seconds
Started Jul 04 04:48:52 PM PDT 24
Finished Jul 04 04:49:24 PM PDT 24
Peak memory 249136 kb
Host smart-2ead3746-8358-4af0-9e0e-ef2413864223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28304
21740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2830421740
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3232903687
Short name T351
Test name
Test status
Simulation time 12284550823 ps
CPU time 1121.46 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 273384 kb
Host smart-2a1db9c8-2f47-44ea-bda3-ce7080e9f3af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232903687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3232903687
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.258422387
Short name T180
Test name
Test status
Simulation time 49812842206 ps
CPU time 412.47 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:55:52 PM PDT 24
Peak memory 257056 kb
Host smart-dc3b49a2-792e-4498-9649-76196714cd14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258422387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.258422387
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1970050270
Short name T207
Test name
Test status
Simulation time 1383101434 ps
CPU time 45.81 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:47 PM PDT 24
Peak memory 256580 kb
Host smart-6efead60-7b70-4f53-aa06-2a8c0c75a0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19700
50270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1970050270
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1957673418
Short name T58
Test name
Test status
Simulation time 8882003225 ps
CPU time 39.38 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:49:37 PM PDT 24
Peak memory 256444 kb
Host smart-30c32a1f-366e-4742-8be9-cea9acdab74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
73418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1957673418
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2884622645
Short name T11
Test name
Test status
Simulation time 1242171953 ps
CPU time 22.37 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:21 PM PDT 24
Peak memory 271496 kb
Host smart-f446d672-c8f4-4703-a93f-a30545d842d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2884622645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2884622645
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1599757251
Short name T289
Test name
Test status
Simulation time 1790140695 ps
CPU time 28.44 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 04:49:31 PM PDT 24
Peak memory 249060 kb
Host smart-7c6eba3c-8e49-4197-9141-7bb864b69efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15997
57251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1599757251
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3589679199
Short name T377
Test name
Test status
Simulation time 667727082 ps
CPU time 39.83 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:49:44 PM PDT 24
Peak memory 256812 kb
Host smart-dcf09aed-161e-4825-a298-1765e8883792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35896
79199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3589679199
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3138690409
Short name T637
Test name
Test status
Simulation time 25230609339 ps
CPU time 1657.73 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 05:17:33 PM PDT 24
Peak memory 282076 kb
Host smart-bc091c68-8a57-4d9e-9026-2914c1eb80b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138690409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3138690409
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1709502111
Short name T567
Test name
Test status
Simulation time 7670561956 ps
CPU time 77.53 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 04:51:11 PM PDT 24
Peak memory 256944 kb
Host smart-4956ea67-e22b-4fc0-851d-ef14c6b265ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095
02111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1709502111
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.666832778
Short name T208
Test name
Test status
Simulation time 212141201 ps
CPU time 26.84 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:50:19 PM PDT 24
Peak memory 248648 kb
Host smart-3c56655f-eccf-44ef-ba47-4045ab8c7230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66683
2778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.666832778
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2361105930
Short name T335
Test name
Test status
Simulation time 42382497885 ps
CPU time 2616.94 seconds
Started Jul 04 04:49:55 PM PDT 24
Finished Jul 04 05:33:33 PM PDT 24
Peak memory 290216 kb
Host smart-e947a5ef-4421-4068-a1bc-ff4553b58619
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361105930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2361105930
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3985976836
Short name T417
Test name
Test status
Simulation time 225536457114 ps
CPU time 3120.22 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 05:41:58 PM PDT 24
Peak memory 290272 kb
Host smart-b5606a6f-075e-4864-b2df-7559fe622bd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985976836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3985976836
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.160068399
Short name T309
Test name
Test status
Simulation time 28281300006 ps
CPU time 505.5 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:58:18 PM PDT 24
Peak memory 249072 kb
Host smart-ef12452e-9774-4960-aad0-a7eb2ba04241
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160068399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.160068399
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.132682064
Short name T563
Test name
Test status
Simulation time 400254623 ps
CPU time 30.64 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 04:50:24 PM PDT 24
Peak memory 249212 kb
Host smart-58b3f537-1883-4f69-b839-66a1fbeeead5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13268
2064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.132682064
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.886612328
Short name T386
Test name
Test status
Simulation time 185541644 ps
CPU time 8.16 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:50:00 PM PDT 24
Peak memory 252692 kb
Host smart-1860cdde-dbf4-4491-a0e1-9c613354906e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88661
2328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.886612328
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.170914263
Short name T244
Test name
Test status
Simulation time 967346634 ps
CPU time 31.21 seconds
Started Jul 04 04:49:48 PM PDT 24
Finished Jul 04 04:50:20 PM PDT 24
Peak memory 257352 kb
Host smart-f8f5a8c5-42b8-4fa9-98c6-11c151da9c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17091
4263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.170914263
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3797602698
Short name T519
Test name
Test status
Simulation time 3098222668 ps
CPU time 21.25 seconds
Started Jul 04 04:49:50 PM PDT 24
Finished Jul 04 04:50:12 PM PDT 24
Peak memory 257088 kb
Host smart-5f25b989-930c-4b95-84bf-729568830bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37976
02698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3797602698
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3246460803
Short name T120
Test name
Test status
Simulation time 24238503332 ps
CPU time 1558.29 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 05:15:47 PM PDT 24
Peak memory 273832 kb
Host smart-15fb5d0c-b02b-44d5-ad32-8d5a43449402
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246460803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3246460803
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.4175167488
Short name T547
Test name
Test status
Simulation time 137660860488 ps
CPU time 1995.99 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 05:23:10 PM PDT 24
Peak memory 282648 kb
Host smart-787d544e-1635-4583-9a2f-6c8f55fa5413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175167488 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.4175167488
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.4107316734
Short name T137
Test name
Test status
Simulation time 177955671791 ps
CPU time 2872.36 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 05:37:47 PM PDT 24
Peak memory 288952 kb
Host smart-1416831b-9c7b-4fc5-b9d3-f9ad7a26270b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107316734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4107316734
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2202996365
Short name T686
Test name
Test status
Simulation time 7765080025 ps
CPU time 156.52 seconds
Started Jul 04 04:49:55 PM PDT 24
Finished Jul 04 04:52:32 PM PDT 24
Peak memory 256788 kb
Host smart-07ecae6f-e439-459d-98ca-f1efac91f6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22029
96365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2202996365
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2614611541
Short name T1
Test name
Test status
Simulation time 512601379 ps
CPU time 24.13 seconds
Started Jul 04 04:49:52 PM PDT 24
Finished Jul 04 04:50:16 PM PDT 24
Peak memory 248684 kb
Host smart-f01c36f6-9c15-44f5-9c12-9e12066004fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
11541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2614611541
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.35437974
Short name T280
Test name
Test status
Simulation time 239949240272 ps
CPU time 2718.46 seconds
Started Jul 04 04:49:55 PM PDT 24
Finished Jul 04 05:35:14 PM PDT 24
Peak memory 289448 kb
Host smart-086533fe-a107-41c2-b5c0-0ad143d3ba85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35437974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.35437974
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2821121027
Short name T516
Test name
Test status
Simulation time 25622236142 ps
CPU time 1685.87 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 05:18:03 PM PDT 24
Peak memory 273624 kb
Host smart-7305f4f9-5fb3-4013-bb03-43abce3968c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821121027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2821121027
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1216009367
Short name T647
Test name
Test status
Simulation time 9759889064 ps
CPU time 402.5 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 04:56:39 PM PDT 24
Peak memory 249296 kb
Host smart-7256b936-425e-40df-9e96-c8923045f313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216009367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1216009367
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1512537701
Short name T46
Test name
Test status
Simulation time 247975000 ps
CPU time 16.65 seconds
Started Jul 04 04:49:51 PM PDT 24
Finished Jul 04 04:50:08 PM PDT 24
Peak memory 249180 kb
Host smart-7f3d26fd-44d5-461d-afdf-07ea3f91b62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125
37701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1512537701
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1001281143
Short name T553
Test name
Test status
Simulation time 814812536 ps
CPU time 25.67 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 04:50:20 PM PDT 24
Peak memory 256728 kb
Host smart-852edec9-e262-4c2f-876a-da79c3df4326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012
81143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1001281143
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.235402629
Short name T450
Test name
Test status
Simulation time 307696905 ps
CPU time 26.13 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 04:50:23 PM PDT 24
Peak memory 256432 kb
Host smart-0df6f16e-2011-48d0-841e-8a4e60dc3b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23540
2629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.235402629
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2789496006
Short name T254
Test name
Test status
Simulation time 2747822301 ps
CPU time 78.37 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 04:51:15 PM PDT 24
Peak memory 250504 kb
Host smart-641c9c47-1a2d-4f4c-bb66-21e9970f8b7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789496006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2789496006
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3783248100
Short name T81
Test name
Test status
Simulation time 21457283011 ps
CPU time 694.36 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 05:01:27 PM PDT 24
Peak memory 273648 kb
Host smart-e72b2cc5-dcc2-44e5-aeb1-e038cc7b486b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783248100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3783248100
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2214847124
Short name T678
Test name
Test status
Simulation time 1575035970 ps
CPU time 42.98 seconds
Started Jul 04 04:49:53 PM PDT 24
Finished Jul 04 04:50:36 PM PDT 24
Peak memory 256916 kb
Host smart-84134469-3436-4aa2-b001-4607631ccbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22148
47124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2214847124
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1300997399
Short name T92
Test name
Test status
Simulation time 1193726206 ps
CPU time 45.69 seconds
Started Jul 04 04:49:51 PM PDT 24
Finished Jul 04 04:50:37 PM PDT 24
Peak memory 249672 kb
Host smart-a91888ce-770f-428b-bf2c-ccd52f78fe90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13009
97399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1300997399
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3377302319
Short name T33
Test name
Test status
Simulation time 77832868859 ps
CPU time 2358.78 seconds
Started Jul 04 04:49:55 PM PDT 24
Finished Jul 04 05:29:14 PM PDT 24
Peak memory 290140 kb
Host smart-e66c5771-e294-431c-94bc-b2d2cfb78c8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377302319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3377302319
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.909434935
Short name T421
Test name
Test status
Simulation time 105454297 ps
CPU time 7.21 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 04:50:04 PM PDT 24
Peak memory 249104 kb
Host smart-d29fc3ef-cefb-4332-8f58-5c69f65c8ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90943
4935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.909434935
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.982823678
Short name T540
Test name
Test status
Simulation time 1195234355 ps
CPU time 27.15 seconds
Started Jul 04 04:49:49 PM PDT 24
Finished Jul 04 04:50:16 PM PDT 24
Peak memory 248348 kb
Host smart-b0203f5b-10e1-4e80-9c1f-b56d8e0cb019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98282
3678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.982823678
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1360914142
Short name T487
Test name
Test status
Simulation time 574885664 ps
CPU time 26.39 seconds
Started Jul 04 04:49:50 PM PDT 24
Finished Jul 04 04:50:16 PM PDT 24
Peak memory 248712 kb
Host smart-24b06146-3313-4ae8-8bf2-ed37f7b08605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13609
14142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1360914142
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2845940218
Short name T669
Test name
Test status
Simulation time 505261217 ps
CPU time 11.29 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 04:50:08 PM PDT 24
Peak memory 255340 kb
Host smart-3f1eed69-1512-4276-8724-2ad4a7044361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28459
40218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2845940218
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3405155375
Short name T544
Test name
Test status
Simulation time 49806008358 ps
CPU time 3160.14 seconds
Started Jul 04 04:49:54 PM PDT 24
Finished Jul 04 05:42:35 PM PDT 24
Peak memory 306636 kb
Host smart-393ad820-3201-4acc-b7dd-6e80c79c0e40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405155375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3405155375
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1947024476
Short name T501
Test name
Test status
Simulation time 199175962656 ps
CPU time 4978.81 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 06:12:57 PM PDT 24
Peak memory 319376 kb
Host smart-1438b133-b33f-46a8-abe9-bbb952d1b719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947024476 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1947024476
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.672831521
Short name T279
Test name
Test status
Simulation time 82983541355 ps
CPU time 2288.26 seconds
Started Jul 04 04:50:00 PM PDT 24
Finished Jul 04 05:28:08 PM PDT 24
Peak memory 289112 kb
Host smart-443ff82f-9d29-4ae8-9eca-766ac5418346
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672831521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.672831521
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1906634073
Short name T398
Test name
Test status
Simulation time 4814008244 ps
CPU time 158.21 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 04:52:40 PM PDT 24
Peak memory 257476 kb
Host smart-99dca112-bcf1-4153-a52d-3a0170c839c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19066
34073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1906634073
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3217330928
Short name T24
Test name
Test status
Simulation time 1464440689 ps
CPU time 45.69 seconds
Started Jul 04 04:49:55 PM PDT 24
Finished Jul 04 04:50:41 PM PDT 24
Peak memory 248680 kb
Host smart-6d0007eb-e917-4b36-a292-b19c780049a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32173
30928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3217330928
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.808458136
Short name T580
Test name
Test status
Simulation time 55459687532 ps
CPU time 1175.48 seconds
Started Jul 04 04:49:59 PM PDT 24
Finished Jul 04 05:09:35 PM PDT 24
Peak memory 289476 kb
Host smart-a1f1791c-c4b4-4f21-a58b-6ff3dced178a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808458136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.808458136
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.4025023464
Short name T543
Test name
Test status
Simulation time 47134937840 ps
CPU time 2588.8 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 05:33:07 PM PDT 24
Peak memory 289088 kb
Host smart-09bafd30-4bca-4f91-8510-328543bbfc1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025023464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4025023464
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.971456026
Short name T640
Test name
Test status
Simulation time 45836762029 ps
CPU time 263.38 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 04:54:19 PM PDT 24
Peak memory 256408 kb
Host smart-7f89dec9-f235-4f84-ad8d-921c553fcd58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971456026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.971456026
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2036362129
Short name T361
Test name
Test status
Simulation time 1348693291 ps
CPU time 40.04 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 04:50:38 PM PDT 24
Peak memory 256596 kb
Host smart-0ed259b7-5958-48d1-b4e0-694e7a31d412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20363
62129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2036362129
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.590860857
Short name T63
Test name
Test status
Simulation time 78834256 ps
CPU time 6.22 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 04:50:08 PM PDT 24
Peak memory 253436 kb
Host smart-e2e3d91b-c14f-4f23-9ebb-8f370c5f704e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59086
0857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.590860857
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3023152147
Short name T64
Test name
Test status
Simulation time 462733873 ps
CPU time 22.95 seconds
Started Jul 04 04:49:59 PM PDT 24
Finished Jul 04 04:50:23 PM PDT 24
Peak memory 248556 kb
Host smart-aeff0ab9-219a-49ee-b843-87fe964d24c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30231
52147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3023152147
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.549385892
Short name T394
Test name
Test status
Simulation time 1918367043 ps
CPU time 12.78 seconds
Started Jul 04 04:49:59 PM PDT 24
Finished Jul 04 04:50:12 PM PDT 24
Peak memory 255688 kb
Host smart-5c02fe03-b314-4d3f-8312-647fe19c6e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54938
5892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.549385892
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.872456774
Short name T260
Test name
Test status
Simulation time 163231525178 ps
CPU time 2313.83 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 05:28:36 PM PDT 24
Peak memory 289532 kb
Host smart-174298d8-cd6e-4451-8d35-a440381d7902
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872456774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.872456774
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3995495129
Short name T529
Test name
Test status
Simulation time 273054807399 ps
CPU time 2235.32 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 05:27:13 PM PDT 24
Peak memory 298520 kb
Host smart-ec57e312-3f84-4bb4-acbf-458a2cff4377
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995495129 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3995495129
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1710648227
Short name T273
Test name
Test status
Simulation time 44372540771 ps
CPU time 2804.07 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 05:36:42 PM PDT 24
Peak memory 289516 kb
Host smart-2c8d7b43-993b-4773-b1b3-e9725eeac4be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710648227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1710648227
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2531193730
Short name T560
Test name
Test status
Simulation time 3640906495 ps
CPU time 57.91 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 04:50:55 PM PDT 24
Peak memory 257540 kb
Host smart-c7dfb239-ae10-403d-a61a-aa36f1487457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25311
93730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2531193730
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.817437266
Short name T551
Test name
Test status
Simulation time 122115735 ps
CPU time 8.26 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 04:50:05 PM PDT 24
Peak memory 248700 kb
Host smart-4e5e91ab-11a2-4d0e-a6e8-a68200404d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81743
7266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.817437266
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1551743456
Short name T330
Test name
Test status
Simulation time 55104736740 ps
CPU time 1337.06 seconds
Started Jul 04 04:50:00 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 289544 kb
Host smart-ef99adfb-4a72-4661-b722-fa20ebf28f19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551743456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1551743456
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.919624223
Short name T696
Test name
Test status
Simulation time 14214575033 ps
CPU time 1287 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 05:11:26 PM PDT 24
Peak memory 285548 kb
Host smart-c67ea7f8-27d9-4bd7-b754-370a8757f58a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919624223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.919624223
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2154741671
Short name T655
Test name
Test status
Simulation time 73672258262 ps
CPU time 422.48 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 04:57:04 PM PDT 24
Peak memory 255204 kb
Host smart-33cc0e81-71b5-4df9-aeef-5cd09fc816b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154741671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2154741671
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4192648886
Short name T347
Test name
Test status
Simulation time 217034218 ps
CPU time 5.1 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 04:50:03 PM PDT 24
Peak memory 249136 kb
Host smart-703ab310-2996-4044-a861-f6963843a136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41926
48886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4192648886
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3929869240
Short name T403
Test name
Test status
Simulation time 541417295 ps
CPU time 6.5 seconds
Started Jul 04 04:50:00 PM PDT 24
Finished Jul 04 04:50:07 PM PDT 24
Peak memory 251672 kb
Host smart-30f9df07-81f8-4243-a424-b7b0c29df331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39298
69240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3929869240
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2477750344
Short name T400
Test name
Test status
Simulation time 797362183 ps
CPU time 20.31 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 04:50:16 PM PDT 24
Peak memory 256740 kb
Host smart-fbf7e9ce-a516-412b-bcc1-e3344dda8622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24777
50344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2477750344
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3924278385
Short name T605
Test name
Test status
Simulation time 642417230 ps
CPU time 12.51 seconds
Started Jul 04 04:50:00 PM PDT 24
Finished Jul 04 04:50:13 PM PDT 24
Peak memory 249576 kb
Host smart-e7e6738f-59a6-41a6-83ea-c1c091f8925c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
78385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3924278385
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2807532452
Short name T294
Test name
Test status
Simulation time 179517611894 ps
CPU time 2745.85 seconds
Started Jul 04 04:49:57 PM PDT 24
Finished Jul 04 05:35:44 PM PDT 24
Peak memory 298212 kb
Host smart-9adc4b3d-f4b4-4bee-bf39-842ea5ab65dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807532452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2807532452
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.357759458
Short name T62
Test name
Test status
Simulation time 302962627305 ps
CPU time 4889.38 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 06:11:31 PM PDT 24
Peak memory 323012 kb
Host smart-5d29105e-a90d-4f0b-a086-1253eb733dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357759458 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.357759458
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3932167757
Short name T65
Test name
Test status
Simulation time 83917732820 ps
CPU time 1933.09 seconds
Started Jul 04 04:50:02 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 273788 kb
Host smart-b85ebe99-0723-4248-b1ba-a9a777cf4f21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932167757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3932167757
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2705535407
Short name T541
Test name
Test status
Simulation time 1030756255 ps
CPU time 73.12 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 04:51:11 PM PDT 24
Peak memory 257372 kb
Host smart-0df5051b-25ba-4e11-855b-18ac9be99052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27055
35407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2705535407
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.646942955
Short name T653
Test name
Test status
Simulation time 150905392 ps
CPU time 10.88 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 04:50:12 PM PDT 24
Peak memory 249128 kb
Host smart-0b389549-1207-4751-b20d-7040b2895a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64694
2955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.646942955
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2085801347
Short name T326
Test name
Test status
Simulation time 16681878157 ps
CPU time 1337.62 seconds
Started Jul 04 04:49:56 PM PDT 24
Finished Jul 04 05:12:14 PM PDT 24
Peak memory 286672 kb
Host smart-5ffed1be-3eb2-4bd7-942e-378c7bb1edaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085801347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2085801347
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3234441278
Short name T408
Test name
Test status
Simulation time 202771115957 ps
CPU time 1004.85 seconds
Started Jul 04 04:50:01 PM PDT 24
Finished Jul 04 05:06:47 PM PDT 24
Peak memory 273388 kb
Host smart-f95f3892-6827-4487-af5e-53fe2ddfe426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234441278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3234441278
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2126692879
Short name T266
Test name
Test status
Simulation time 83339126 ps
CPU time 6.91 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 04:50:05 PM PDT 24
Peak memory 249156 kb
Host smart-80f8e375-a5de-4c7e-8f76-e0c89d08af64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21266
92879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2126692879
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.8265360
Short name T269
Test name
Test status
Simulation time 184712528 ps
CPU time 23 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 04:50:21 PM PDT 24
Peak memory 256800 kb
Host smart-3ad01186-043a-48a7-9023-03c07b29795e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82653
60 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.8265360
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2614655526
Short name T209
Test name
Test status
Simulation time 253333855 ps
CPU time 6.43 seconds
Started Jul 04 04:50:00 PM PDT 24
Finished Jul 04 04:50:07 PM PDT 24
Peak memory 240332 kb
Host smart-ba4e0500-1d65-4d4f-b36f-726593772565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26146
55526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2614655526
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.593279369
Short name T523
Test name
Test status
Simulation time 354379600 ps
CPU time 30.68 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 04:50:29 PM PDT 24
Peak memory 257288 kb
Host smart-0a346e34-13eb-4f83-80eb-b863daddd437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59327
9369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.593279369
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2413556343
Short name T106
Test name
Test status
Simulation time 136054935668 ps
CPU time 2521.08 seconds
Started Jul 04 04:50:05 PM PDT 24
Finished Jul 04 05:32:07 PM PDT 24
Peak memory 289708 kb
Host smart-eefedc9e-09d6-4de5-b9ce-441d6a84e068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413556343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2413556343
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3287441203
Short name T389
Test name
Test status
Simulation time 6238467505 ps
CPU time 156.41 seconds
Started Jul 04 04:50:05 PM PDT 24
Finished Jul 04 04:52:42 PM PDT 24
Peak memory 257472 kb
Host smart-61b03474-e416-4d38-96a1-425720ef78f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32874
41203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3287441203
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2481692507
Short name T80
Test name
Test status
Simulation time 415797076 ps
CPU time 21.91 seconds
Started Jul 04 04:50:04 PM PDT 24
Finished Jul 04 04:50:26 PM PDT 24
Peak memory 248644 kb
Host smart-033f1e2d-b786-4261-99b4-11b6dcd06550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
92507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2481692507
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.10283789
Short name T319
Test name
Test status
Simulation time 146092391042 ps
CPU time 2208.77 seconds
Started Jul 04 04:50:04 PM PDT 24
Finished Jul 04 05:26:53 PM PDT 24
Peak memory 273780 kb
Host smart-b14739dc-6f25-45ed-9032-c9f453c3821b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10283789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.10283789
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1605352877
Short name T614
Test name
Test status
Simulation time 15493240408 ps
CPU time 740.32 seconds
Started Jul 04 04:50:05 PM PDT 24
Finished Jul 04 05:02:26 PM PDT 24
Peak memory 273384 kb
Host smart-a92b8604-04d0-48cd-a725-fa492f77c3b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605352877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1605352877
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3519556158
Short name T469
Test name
Test status
Simulation time 4229260635 ps
CPU time 42.7 seconds
Started Jul 04 04:50:04 PM PDT 24
Finished Jul 04 04:50:47 PM PDT 24
Peak memory 249256 kb
Host smart-a91eef6b-f4dc-49f0-8a1f-ec5ccf5cc270
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519556158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3519556158
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.4038362061
Short name T415
Test name
Test status
Simulation time 216137089 ps
CPU time 22.14 seconds
Started Jul 04 04:50:06 PM PDT 24
Finished Jul 04 04:50:28 PM PDT 24
Peak memory 249140 kb
Host smart-059502c3-a0c8-4de3-ba3a-3a3c937fc702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40383
62061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.4038362061
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4292893996
Short name T2
Test name
Test status
Simulation time 759268363 ps
CPU time 20.82 seconds
Started Jul 04 04:50:02 PM PDT 24
Finished Jul 04 04:50:23 PM PDT 24
Peak memory 248672 kb
Host smart-3639c5f3-88b4-44e0-896a-771fe8fcfbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42928
93996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4292893996
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1680735707
Short name T119
Test name
Test status
Simulation time 685993336 ps
CPU time 52.31 seconds
Started Jul 04 04:50:07 PM PDT 24
Finished Jul 04 04:51:00 PM PDT 24
Peak memory 256480 kb
Host smart-5483811f-4cdd-44ed-be12-173c9f17a1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807
35707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1680735707
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.196154059
Short name T694
Test name
Test status
Simulation time 3352114811 ps
CPU time 60.2 seconds
Started Jul 04 04:49:58 PM PDT 24
Finished Jul 04 04:50:58 PM PDT 24
Peak memory 257388 kb
Host smart-6baa7762-0d5a-4789-bddb-de1396fed11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
4059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.196154059
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1491137818
Short name T498
Test name
Test status
Simulation time 5172478589 ps
CPU time 333.66 seconds
Started Jul 04 04:50:05 PM PDT 24
Finished Jul 04 04:55:39 PM PDT 24
Peak memory 257432 kb
Host smart-1725e645-2651-40b8-b08d-aceccfb0e761
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491137818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1491137818
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.141951939
Short name T248
Test name
Test status
Simulation time 60015365340 ps
CPU time 3413.61 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 05:47:07 PM PDT 24
Peak memory 298588 kb
Host smart-b5e3ee2b-00c4-4afe-b1f4-f411bc0f85fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141951939 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.141951939
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1982844068
Short name T376
Test name
Test status
Simulation time 5106949278 ps
CPU time 84.24 seconds
Started Jul 04 04:50:03 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 256720 kb
Host smart-a033c9fa-8460-4fb8-b3e0-65f9523e3996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19828
44068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1982844068
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1430863487
Short name T514
Test name
Test status
Simulation time 1044568459 ps
CPU time 64.03 seconds
Started Jul 04 04:50:06 PM PDT 24
Finished Jul 04 04:51:10 PM PDT 24
Peak memory 249152 kb
Host smart-1d03eaf5-cef4-4e87-a546-76458b70c966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
63487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1430863487
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.376547332
Short name T314
Test name
Test status
Simulation time 66700818012 ps
CPU time 1384.07 seconds
Started Jul 04 04:50:09 PM PDT 24
Finished Jul 04 05:13:14 PM PDT 24
Peak memory 289628 kb
Host smart-83ac7bf4-42a0-4eee-8233-3bfa1ed02af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376547332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.376547332
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2461091756
Short name T522
Test name
Test status
Simulation time 7651286101 ps
CPU time 696.25 seconds
Started Jul 04 04:50:06 PM PDT 24
Finished Jul 04 05:01:43 PM PDT 24
Peak memory 273104 kb
Host smart-ce0302c1-a1d0-4cf1-8382-bdad9b8e684c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461091756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2461091756
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3299943565
Short name T307
Test name
Test status
Simulation time 8340221544 ps
CPU time 345.41 seconds
Started Jul 04 04:50:04 PM PDT 24
Finished Jul 04 04:55:49 PM PDT 24
Peak memory 249088 kb
Host smart-e7c34934-5755-4ea1-8fd5-be626872108b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299943565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3299943565
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2523324101
Short name T278
Test name
Test status
Simulation time 580384135 ps
CPU time 39.47 seconds
Started Jul 04 04:50:03 PM PDT 24
Finished Jul 04 04:50:43 PM PDT 24
Peak memory 256444 kb
Host smart-e68cdd93-2ac9-4992-9e76-0f77ccc6e84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25233
24101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2523324101
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1688952318
Short name T134
Test name
Test status
Simulation time 561126658 ps
CPU time 38.25 seconds
Started Jul 04 04:50:03 PM PDT 24
Finished Jul 04 04:50:42 PM PDT 24
Peak memory 256660 kb
Host smart-a4cab636-b28d-46d8-941f-b4088b963570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16889
52318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1688952318
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3462483783
Short name T118
Test name
Test status
Simulation time 1539364290 ps
CPU time 51.79 seconds
Started Jul 04 04:50:08 PM PDT 24
Finished Jul 04 04:51:00 PM PDT 24
Peak memory 249252 kb
Host smart-dc487f6b-93b9-4eee-a3f4-c5f1be905032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34624
83783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3462483783
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3302446095
Short name T110
Test name
Test status
Simulation time 241453044 ps
CPU time 4.89 seconds
Started Jul 04 04:50:02 PM PDT 24
Finished Jul 04 04:50:07 PM PDT 24
Peak memory 251276 kb
Host smart-38206aea-fb1b-49c2-bdfc-c8019ddbb23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33024
46095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3302446095
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3828915033
Short name T96
Test name
Test status
Simulation time 118939388341 ps
CPU time 1911 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 05:22:04 PM PDT 24
Peak memory 287000 kb
Host smart-a69a7a65-4992-411f-b6d1-fbc76c7068e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828915033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3828915033
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2084498425
Short name T77
Test name
Test status
Simulation time 1023193671 ps
CPU time 112.77 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:52:06 PM PDT 24
Peak memory 256456 kb
Host smart-5a6523fb-9b1c-4f16-9280-71ee9139860d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20844
98425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2084498425
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3074568174
Short name T405
Test name
Test status
Simulation time 1323013939 ps
CPU time 40.05 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:50:53 PM PDT 24
Peak memory 248644 kb
Host smart-402d92a2-820a-421c-ba21-d545b9638d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30745
68174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3074568174
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2051145119
Short name T332
Test name
Test status
Simulation time 73316264988 ps
CPU time 1488.32 seconds
Started Jul 04 04:50:15 PM PDT 24
Finished Jul 04 05:15:04 PM PDT 24
Peak memory 287064 kb
Host smart-ae1d2693-4dde-4c17-95d4-b622e5fbd36a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051145119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2051145119
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.52495241
Short name T268
Test name
Test status
Simulation time 19835732325 ps
CPU time 1699.29 seconds
Started Jul 04 04:50:11 PM PDT 24
Finished Jul 04 05:18:31 PM PDT 24
Peak memory 289412 kb
Host smart-3535ebe0-1db6-4d6b-ace0-cac023293841
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52495241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.52495241
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2153161750
Short name T205
Test name
Test status
Simulation time 6576120314 ps
CPU time 259.52 seconds
Started Jul 04 04:50:14 PM PDT 24
Finished Jul 04 04:54:34 PM PDT 24
Peak memory 249308 kb
Host smart-043366d0-9c3c-471e-86f7-8848223abe50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153161750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2153161750
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1361274165
Short name T242
Test name
Test status
Simulation time 1051959423 ps
CPU time 36.17 seconds
Started Jul 04 04:50:11 PM PDT 24
Finished Jul 04 04:50:47 PM PDT 24
Peak memory 249184 kb
Host smart-9d0b0c4c-9535-4eb7-84e7-b41b42c0ae43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13612
74165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1361274165
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1383115783
Short name T395
Test name
Test status
Simulation time 3155458359 ps
CPU time 44.71 seconds
Started Jul 04 04:50:11 PM PDT 24
Finished Jul 04 04:50:56 PM PDT 24
Peak memory 256928 kb
Host smart-8f219563-5645-493d-bc49-b63099593731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13831
15783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1383115783
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1957114442
Short name T672
Test name
Test status
Simulation time 830819764 ps
CPU time 50.7 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:51:03 PM PDT 24
Peak memory 257208 kb
Host smart-cdc1e372-da93-4c5c-98f4-1b0a5c0ce350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19571
14442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1957114442
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1627115936
Short name T595
Test name
Test status
Simulation time 4745004135 ps
CPU time 48.06 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:51:01 PM PDT 24
Peak memory 257228 kb
Host smart-34d1f10d-6c7c-474c-8b7e-42e0555da709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
15936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1627115936
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4171210532
Short name T354
Test name
Test status
Simulation time 91845320608 ps
CPU time 2707.69 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 05:35:20 PM PDT 24
Peak memory 290264 kb
Host smart-0089dd4a-e2a5-41b0-930c-5df14f1e6e72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171210532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4171210532
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2754413529
Short name T440
Test name
Test status
Simulation time 7923308024 ps
CPU time 686.37 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 05:01:39 PM PDT 24
Peak memory 273880 kb
Host smart-7c3627a0-2d00-4eec-a246-343a164a8ca1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754413529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2754413529
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.4183984567
Short name T204
Test name
Test status
Simulation time 626237775 ps
CPU time 65.52 seconds
Started Jul 04 04:50:11 PM PDT 24
Finished Jul 04 04:51:17 PM PDT 24
Peak memory 249140 kb
Host smart-b0d8de24-3e81-4bce-983d-a4cb5e382d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41839
84567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4183984567
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1471979372
Short name T460
Test name
Test status
Simulation time 5201792819 ps
CPU time 73.67 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:51:26 PM PDT 24
Peak memory 249168 kb
Host smart-7881fea6-a958-4a91-a8e9-10c546f5c061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14719
79372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1471979372
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3838295533
Short name T436
Test name
Test status
Simulation time 28797368465 ps
CPU time 1730.21 seconds
Started Jul 04 04:50:13 PM PDT 24
Finished Jul 04 05:19:03 PM PDT 24
Peak memory 289572 kb
Host smart-3178ea24-2402-4031-9ea0-1b6ca6bbaec4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838295533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3838295533
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4075328985
Short name T123
Test name
Test status
Simulation time 11668330772 ps
CPU time 499.28 seconds
Started Jul 04 04:50:11 PM PDT 24
Finished Jul 04 04:58:31 PM PDT 24
Peak memory 249072 kb
Host smart-43cc5b51-e84c-4a3d-88b9-4216d45e62e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075328985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4075328985
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1238019644
Short name T597
Test name
Test status
Simulation time 242051131 ps
CPU time 11.6 seconds
Started Jul 04 04:50:11 PM PDT 24
Finished Jul 04 04:50:23 PM PDT 24
Peak memory 257292 kb
Host smart-a73e8111-e10b-47f1-9f96-5179808e13a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12380
19644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1238019644
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1894747937
Short name T258
Test name
Test status
Simulation time 1985161706 ps
CPU time 23.86 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:50:37 PM PDT 24
Peak memory 255660 kb
Host smart-11c55f2c-2d4b-491e-8ee2-e73aae333800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18947
47937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1894747937
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.789554568
Short name T437
Test name
Test status
Simulation time 2194281938 ps
CPU time 74.77 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 257472 kb
Host smart-5b2f0e8b-e75e-4c5e-8ab2-7209c18d2962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78955
4568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.789554568
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4204350483
Short name T662
Test name
Test status
Simulation time 311163696 ps
CPU time 27.84 seconds
Started Jul 04 04:50:13 PM PDT 24
Finished Jul 04 04:50:41 PM PDT 24
Peak memory 256352 kb
Host smart-c2c86501-e019-453d-8600-7c7248d86953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043
50483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4204350483
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1822180620
Short name T265
Test name
Test status
Simulation time 157794184070 ps
CPU time 2374.08 seconds
Started Jul 04 04:50:10 PM PDT 24
Finished Jul 04 05:29:44 PM PDT 24
Peak memory 289812 kb
Host smart-ed4150d9-6907-41f0-861c-7c794a4d8aa3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822180620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1822180620
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.591679247
Short name T26
Test name
Test status
Simulation time 140531797 ps
CPU time 3.3 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:05 PM PDT 24
Peak memory 249472 kb
Host smart-e88a9c04-deeb-4738-9360-da84a71b795c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=591679247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.591679247
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3883372122
Short name T378
Test name
Test status
Simulation time 16721824665 ps
CPU time 1596.58 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 289856 kb
Host smart-351cea8b-6d4d-4c54-84a2-4fead83dcee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883372122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3883372122
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3184660914
Short name T616
Test name
Test status
Simulation time 2075025640 ps
CPU time 26.09 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 04:49:31 PM PDT 24
Peak memory 249096 kb
Host smart-d9348374-a198-4df0-ad12-6f115915d7b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3184660914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3184660914
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1904745027
Short name T393
Test name
Test status
Simulation time 4875867058 ps
CPU time 135.57 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 256732 kb
Host smart-c3f6a3b9-162d-4e8d-b7d4-c363fb6076dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19047
45027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1904745027
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3778868894
Short name T239
Test name
Test status
Simulation time 1152035567 ps
CPU time 45.7 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:49:45 PM PDT 24
Peak memory 248960 kb
Host smart-01b9c1ab-ce83-4cc9-aac6-8ef3b3e975b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37788
68894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3778868894
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1001749107
Short name T664
Test name
Test status
Simulation time 302669445569 ps
CPU time 1440.09 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 05:12:59 PM PDT 24
Peak memory 289052 kb
Host smart-51aa4591-754d-4c30-a18c-f8df1ea61ed6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001749107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1001749107
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.110122992
Short name T31
Test name
Test status
Simulation time 579331800129 ps
CPU time 2515.91 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 05:30:57 PM PDT 24
Peak memory 283304 kb
Host smart-d904108d-6cd1-42c4-ac19-988a8ca60197
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110122992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.110122992
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2061080012
Short name T10
Test name
Test status
Simulation time 45055118870 ps
CPU time 397.58 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:55:51 PM PDT 24
Peak memory 249316 kb
Host smart-012e810c-6120-486e-acb3-51690f5c62e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061080012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2061080012
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1573153178
Short name T452
Test name
Test status
Simulation time 1560964680 ps
CPU time 36.92 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:49:37 PM PDT 24
Peak memory 256464 kb
Host smart-f8fe863b-8052-4b9c-8db2-ade3c862cbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15731
53178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1573153178
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2362821887
Short name T526
Test name
Test status
Simulation time 955665985 ps
CPU time 37.19 seconds
Started Jul 04 04:48:47 PM PDT 24
Finished Jul 04 04:49:25 PM PDT 24
Peak memory 248964 kb
Host smart-7ac9dbc8-e0fe-4a35-a276-c5e0cbc4ffe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23628
21887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2362821887
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2846803851
Short name T36
Test name
Test status
Simulation time 1576279826 ps
CPU time 44.42 seconds
Started Jul 04 04:49:05 PM PDT 24
Finished Jul 04 04:49:49 PM PDT 24
Peak memory 267476 kb
Host smart-f2bac031-2114-4fa2-a6e3-4e59c7c0c68a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2846803851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2846803851
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.891669707
Short name T5
Test name
Test status
Simulation time 4549587766 ps
CPU time 75.12 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:50:17 PM PDT 24
Peak memory 256992 kb
Host smart-5b306439-4cc8-4bbe-9481-d2572f31f46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89166
9707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.891669707
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3504897586
Short name T371
Test name
Test status
Simulation time 928250465 ps
CPU time 16.36 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:49:15 PM PDT 24
Peak memory 249528 kb
Host smart-405d9a0b-9c56-4694-b456-d19f97e6a924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35048
97586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3504897586
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3629252214
Short name T472
Test name
Test status
Simulation time 65988684047 ps
CPU time 2325.07 seconds
Started Jul 04 04:50:21 PM PDT 24
Finished Jul 04 05:29:06 PM PDT 24
Peak memory 289748 kb
Host smart-fb9c59b6-e363-43ad-ab25-375a55178dc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629252214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3629252214
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1580443112
Short name T456
Test name
Test status
Simulation time 1064902494 ps
CPU time 94.19 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:51:52 PM PDT 24
Peak memory 257328 kb
Host smart-d6ec5977-5502-47eb-86e5-4f2f831aeb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15804
43112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1580443112
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1401985585
Short name T643
Test name
Test status
Simulation time 895663918 ps
CPU time 64.96 seconds
Started Jul 04 04:50:22 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 249128 kb
Host smart-cadc04d3-8a73-4fca-98db-bf7a32d5336b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14019
85585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1401985585
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3833852796
Short name T315
Test name
Test status
Simulation time 10272365763 ps
CPU time 874.39 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 05:04:53 PM PDT 24
Peak memory 273276 kb
Host smart-e21b20d6-eb94-49d5-9620-0bc2594015a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833852796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3833852796
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.997494660
Short name T235
Test name
Test status
Simulation time 48384860986 ps
CPU time 1489.57 seconds
Started Jul 04 04:50:23 PM PDT 24
Finished Jul 04 05:15:13 PM PDT 24
Peak memory 289584 kb
Host smart-7922c73b-b3fc-404c-a4dc-4e687baf3501
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997494660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.997494660
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2758101880
Short name T312
Test name
Test status
Simulation time 30206603746 ps
CPU time 238.34 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:54:17 PM PDT 24
Peak memory 255872 kb
Host smart-1779bf18-78ee-4dfd-8740-0b3154daaa54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758101880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2758101880
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.951172835
Short name T599
Test name
Test status
Simulation time 259243180 ps
CPU time 16.36 seconds
Started Jul 04 04:50:11 PM PDT 24
Finished Jul 04 04:50:27 PM PDT 24
Peak memory 249164 kb
Host smart-b941500d-b897-415c-989d-759d0b096aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95117
2835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.951172835
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1224625074
Short name T682
Test name
Test status
Simulation time 1837206306 ps
CPU time 13.07 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 04:50:34 PM PDT 24
Peak memory 255164 kb
Host smart-6f517f0c-b9dd-40c1-8191-ede541e1d3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12246
25074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1224625074
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1601883999
Short name T633
Test name
Test status
Simulation time 291725538 ps
CPU time 23.47 seconds
Started Jul 04 04:50:21 PM PDT 24
Finished Jul 04 04:50:45 PM PDT 24
Peak memory 256668 kb
Host smart-56098983-57e5-48a8-a16c-75b262426291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16018
83999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1601883999
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4207641303
Short name T241
Test name
Test status
Simulation time 109856181 ps
CPU time 9.76 seconds
Started Jul 04 04:50:12 PM PDT 24
Finished Jul 04 04:50:22 PM PDT 24
Peak memory 251972 kb
Host smart-2be7cb64-533a-4309-8e7c-df6b29e27a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42076
41303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4207641303
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1748994515
Short name T458
Test name
Test status
Simulation time 74285214169 ps
CPU time 2560.34 seconds
Started Jul 04 04:50:17 PM PDT 24
Finished Jul 04 05:32:58 PM PDT 24
Peak memory 290452 kb
Host smart-7150fb28-dfd6-48fb-b164-29d367ca8882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748994515 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1748994515
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3731197890
Short name T298
Test name
Test status
Simulation time 11992032927 ps
CPU time 1426.78 seconds
Started Jul 04 04:50:17 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 290220 kb
Host smart-ebac3d78-7127-4b9f-9d5a-d1504f4f2cff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731197890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3731197890
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3241223045
Short name T451
Test name
Test status
Simulation time 1999146904 ps
CPU time 126.05 seconds
Started Jul 04 04:50:17 PM PDT 24
Finished Jul 04 04:52:23 PM PDT 24
Peak memory 257036 kb
Host smart-9ca1877f-21f6-44ee-88b8-310d612942cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32412
23045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3241223045
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.4127259578
Short name T484
Test name
Test status
Simulation time 2215293608 ps
CPU time 69.8 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:51:28 PM PDT 24
Peak memory 249164 kb
Host smart-4c08fad1-3cc6-4ad6-9190-3692d57a53c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41272
59578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.4127259578
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2246142920
Short name T295
Test name
Test status
Simulation time 13605378915 ps
CPU time 901.91 seconds
Started Jul 04 04:50:23 PM PDT 24
Finished Jul 04 05:05:25 PM PDT 24
Peak memory 273756 kb
Host smart-d90768c1-8a73-4263-89ab-58d66ac129e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246142920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2246142920
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.22369250
Short name T383
Test name
Test status
Simulation time 206686589445 ps
CPU time 1695.47 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 05:18:36 PM PDT 24
Peak memory 273736 kb
Host smart-54311d9b-8ded-4815-9e17-139aba30dab2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22369250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.22369250
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1124470654
Short name T308
Test name
Test status
Simulation time 8251449219 ps
CPU time 337.82 seconds
Started Jul 04 04:50:19 PM PDT 24
Finished Jul 04 04:55:57 PM PDT 24
Peak memory 249268 kb
Host smart-08abc015-08d2-4439-91b4-5ee910cc410b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124470654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1124470654
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3305908593
Short name T510
Test name
Test status
Simulation time 187433333 ps
CPU time 4.14 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:50:23 PM PDT 24
Peak memory 249104 kb
Host smart-2a2351f0-790e-4225-b282-0733211a65ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33059
08593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3305908593
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.155290580
Short name T692
Test name
Test status
Simulation time 780958930 ps
CPU time 14.64 seconds
Started Jul 04 04:50:21 PM PDT 24
Finished Jul 04 04:50:35 PM PDT 24
Peak memory 254868 kb
Host smart-ef591327-520e-4ff2-a7ae-de7108095552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15529
0580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.155290580
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1165582531
Short name T83
Test name
Test status
Simulation time 455716735 ps
CPU time 16.74 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 04:50:37 PM PDT 24
Peak memory 254548 kb
Host smart-13073a8c-e596-4aa0-bc28-4cb6ad6081b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655
82531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1165582531
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1978556080
Short name T419
Test name
Test status
Simulation time 2084510231 ps
CPU time 34.98 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 04:50:56 PM PDT 24
Peak memory 256896 kb
Host smart-4bb0b5af-2303-4a1e-a82e-fd294396601e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19785
56080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1978556080
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2004896338
Short name T97
Test name
Test status
Simulation time 11933933658 ps
CPU time 1354 seconds
Started Jul 04 04:50:19 PM PDT 24
Finished Jul 04 05:12:53 PM PDT 24
Peak memory 289832 kb
Host smart-1fb79d64-c052-4b14-a06a-32866c1c4774
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004896338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2004896338
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1237160559
Short name T569
Test name
Test status
Simulation time 119027299170 ps
CPU time 1562.51 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 05:16:21 PM PDT 24
Peak memory 270772 kb
Host smart-d2534a6d-05da-4410-808f-b3fe12eedef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237160559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1237160559
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3382270195
Short name T252
Test name
Test status
Simulation time 3937498128 ps
CPU time 279.54 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 04:55:00 PM PDT 24
Peak memory 257012 kb
Host smart-fc35b542-88e5-4716-b453-2c0cb2baf764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33822
70195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3382270195
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2159857910
Short name T87
Test name
Test status
Simulation time 2863105215 ps
CPU time 55.96 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 04:51:16 PM PDT 24
Peak memory 257496 kb
Host smart-5d49d1cf-9e38-4d9b-9092-dbedb1b50cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21598
57910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2159857910
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.16281421
Short name T9
Test name
Test status
Simulation time 17198429718 ps
CPU time 1503.05 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 05:15:22 PM PDT 24
Peak memory 290240 kb
Host smart-c32355e3-0b30-4345-8cb6-80e034167bfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16281421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.16281421
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.744987121
Short name T493
Test name
Test status
Simulation time 89978514405 ps
CPU time 2410.85 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 05:30:31 PM PDT 24
Peak memory 287384 kb
Host smart-cdcd5fb4-5a54-45f4-8f98-6a6e1bf65439
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744987121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.744987121
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.240583143
Short name T593
Test name
Test status
Simulation time 20664800778 ps
CPU time 492.21 seconds
Started Jul 04 04:50:17 PM PDT 24
Finished Jul 04 04:58:30 PM PDT 24
Peak memory 248124 kb
Host smart-bb7e7995-a334-4d90-a961-1d87a1c1ee1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240583143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.240583143
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3684504512
Short name T382
Test name
Test status
Simulation time 716575056 ps
CPU time 19.93 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:50:38 PM PDT 24
Peak memory 256612 kb
Host smart-355385af-bc20-4eb7-ac07-1c808b53975e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36845
04512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3684504512
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3933224398
Short name T34
Test name
Test status
Simulation time 726745916 ps
CPU time 30.11 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:50:48 PM PDT 24
Peak memory 248732 kb
Host smart-409fe401-fc0c-4222-9511-5a7573b6b9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39332
24398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3933224398
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.844616125
Short name T357
Test name
Test status
Simulation time 12453601792 ps
CPU time 58.19 seconds
Started Jul 04 04:50:20 PM PDT 24
Finished Jul 04 04:51:19 PM PDT 24
Peak memory 249300 kb
Host smart-59a8e6ce-ea34-471e-b5bf-741843b30fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84461
6125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.844616125
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1690360031
Short name T348
Test name
Test status
Simulation time 2037244516 ps
CPU time 60.18 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:51:19 PM PDT 24
Peak memory 249104 kb
Host smart-5772f73f-7410-4520-9faf-b3fc8e2ed6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16903
60031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1690360031
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1989293270
Short name T590
Test name
Test status
Simulation time 45984034696 ps
CPU time 2493.13 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 05:31:51 PM PDT 24
Peak memory 290012 kb
Host smart-cf575e0b-1ce6-4746-af6f-8d6c13c9ad59
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989293270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1989293270
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3204177149
Short name T202
Test name
Test status
Simulation time 223744469732 ps
CPU time 3602.23 seconds
Started Jul 04 04:50:21 PM PDT 24
Finished Jul 04 05:50:24 PM PDT 24
Peak memory 321580 kb
Host smart-47a1e471-978c-4adc-aac4-c8ce67805095
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204177149 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3204177149
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3862681743
Short name T502
Test name
Test status
Simulation time 6056784975 ps
CPU time 586.54 seconds
Started Jul 04 04:50:23 PM PDT 24
Finished Jul 04 05:00:10 PM PDT 24
Peak memory 273416 kb
Host smart-398be158-b673-462c-a103-081d6fc27c8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862681743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3862681743
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1311719780
Short name T428
Test name
Test status
Simulation time 4720072617 ps
CPU time 66.78 seconds
Started Jul 04 04:50:26 PM PDT 24
Finished Jul 04 04:51:33 PM PDT 24
Peak memory 257500 kb
Host smart-b61cf05c-51a6-4c39-9b10-5577ebacb419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13117
19780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1311719780
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2287733180
Short name T660
Test name
Test status
Simulation time 3758513167 ps
CPU time 17.87 seconds
Started Jul 04 04:50:22 PM PDT 24
Finished Jul 04 04:50:40 PM PDT 24
Peak memory 256636 kb
Host smart-99db045a-2a67-4737-ad3c-57091c5951c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
33180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2287733180
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2821019142
Short name T624
Test name
Test status
Simulation time 29855262596 ps
CPU time 896.66 seconds
Started Jul 04 04:50:26 PM PDT 24
Finished Jul 04 05:05:23 PM PDT 24
Peak memory 273696 kb
Host smart-24be6d8a-6b49-414b-8d16-3943892306ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821019142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2821019142
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3605842378
Short name T409
Test name
Test status
Simulation time 42502199612 ps
CPU time 1224.55 seconds
Started Jul 04 04:50:24 PM PDT 24
Finished Jul 04 05:10:49 PM PDT 24
Peak memory 273504 kb
Host smart-994ba0bc-3936-4f03-9b36-1e60a871e41a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605842378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3605842378
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2906209571
Short name T349
Test name
Test status
Simulation time 534666181 ps
CPU time 22.07 seconds
Started Jul 04 04:50:19 PM PDT 24
Finished Jul 04 04:50:42 PM PDT 24
Peak memory 249172 kb
Host smart-389a617a-a772-4405-b945-16efd9b2b006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29062
09571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2906209571
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.997111661
Short name T444
Test name
Test status
Simulation time 43789792 ps
CPU time 4.11 seconds
Started Jul 04 04:50:23 PM PDT 24
Finished Jul 04 04:50:27 PM PDT 24
Peak memory 240308 kb
Host smart-38308bd2-1ee7-40ff-bd38-bef0c5e70de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99711
1661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.997111661
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.4229377752
Short name T424
Test name
Test status
Simulation time 176276110 ps
CPU time 18.02 seconds
Started Jul 04 04:50:25 PM PDT 24
Finished Jul 04 04:50:44 PM PDT 24
Peak memory 256540 kb
Host smart-ac197bb6-083e-4008-bcdb-1d789e7464e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42293
77752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4229377752
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3976086330
Short name T552
Test name
Test status
Simulation time 887843022 ps
CPU time 48.59 seconds
Started Jul 04 04:50:18 PM PDT 24
Finished Jul 04 04:51:07 PM PDT 24
Peak memory 257352 kb
Host smart-46591292-257a-4f1b-b200-215f9b7f59ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39760
86330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3976086330
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.529532788
Short name T60
Test name
Test status
Simulation time 125083083832 ps
CPU time 10276 seconds
Started Jul 04 04:50:26 PM PDT 24
Finished Jul 04 07:41:44 PM PDT 24
Peak memory 338340 kb
Host smart-845b1355-70f4-44a5-9bbe-23b7bb3d2169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529532788 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.529532788
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.985244683
Short name T108
Test name
Test status
Simulation time 131221270855 ps
CPU time 1610.88 seconds
Started Jul 04 04:50:27 PM PDT 24
Finished Jul 04 05:17:18 PM PDT 24
Peak memory 273576 kb
Host smart-7089eb5f-61f8-4ea9-b573-c6cd9555e0cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985244683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.985244683
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1222706835
Short name T427
Test name
Test status
Simulation time 20764451120 ps
CPU time 302.23 seconds
Started Jul 04 04:50:24 PM PDT 24
Finished Jul 04 04:55:27 PM PDT 24
Peak memory 256972 kb
Host smart-a7808543-4224-4023-a11a-1173e0877744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12227
06835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1222706835
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.858205153
Short name T79
Test name
Test status
Simulation time 551061974 ps
CPU time 24.47 seconds
Started Jul 04 04:50:26 PM PDT 24
Finished Jul 04 04:50:51 PM PDT 24
Peak memory 249648 kb
Host smart-3e75fbe5-2bc9-41a8-8bcd-7ee694a8b370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85820
5153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.858205153
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3595947539
Short name T236
Test name
Test status
Simulation time 389778959884 ps
CPU time 2140.09 seconds
Started Jul 04 04:50:25 PM PDT 24
Finished Jul 04 05:26:06 PM PDT 24
Peak memory 273816 kb
Host smart-ec507d9c-9680-40eb-bd59-eff9b99f1cff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595947539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3595947539
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3448442722
Short name T420
Test name
Test status
Simulation time 89172330545 ps
CPU time 1197.7 seconds
Started Jul 04 04:50:25 PM PDT 24
Finished Jul 04 05:10:23 PM PDT 24
Peak memory 289968 kb
Host smart-73cc94b5-ed47-42ce-b62e-3f01ad0c1029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448442722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3448442722
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3238513844
Short name T642
Test name
Test status
Simulation time 17482857670 ps
CPU time 374.47 seconds
Started Jul 04 04:50:27 PM PDT 24
Finished Jul 04 04:56:42 PM PDT 24
Peak memory 249280 kb
Host smart-7d07b7b2-d107-43c7-9231-575e7597fa9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238513844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3238513844
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1780085148
Short name T454
Test name
Test status
Simulation time 3277117093 ps
CPU time 56.83 seconds
Started Jul 04 04:50:25 PM PDT 24
Finished Jul 04 04:51:22 PM PDT 24
Peak memory 256732 kb
Host smart-dc1e67de-bab1-400a-a730-dc94923ff99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17800
85148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1780085148
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2187042470
Short name T566
Test name
Test status
Simulation time 4060117620 ps
CPU time 59.29 seconds
Started Jul 04 04:50:27 PM PDT 24
Finished Jul 04 04:51:26 PM PDT 24
Peak memory 249304 kb
Host smart-3dc4698b-99e2-431c-b203-acec734e0dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21870
42470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2187042470
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3143006199
Short name T286
Test name
Test status
Simulation time 232078999 ps
CPU time 25.46 seconds
Started Jul 04 04:50:27 PM PDT 24
Finished Jul 04 04:50:53 PM PDT 24
Peak memory 257304 kb
Host smart-ffb2b7df-aa25-41c1-81f3-5acd7c5bdacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31430
06199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3143006199
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3015061762
Short name T122
Test name
Test status
Simulation time 452537275 ps
CPU time 20.67 seconds
Started Jul 04 04:50:27 PM PDT 24
Finished Jul 04 04:50:48 PM PDT 24
Peak memory 256976 kb
Host smart-7f7aca0f-470e-4b04-ba31-7aca08d26d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
61762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3015061762
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2321867584
Short name T270
Test name
Test status
Simulation time 161712554976 ps
CPU time 2723.85 seconds
Started Jul 04 04:50:25 PM PDT 24
Finished Jul 04 05:35:49 PM PDT 24
Peak memory 290312 kb
Host smart-c9bcc20e-54f3-41d0-9e8a-1bb57efefd5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321867584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2321867584
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3818009476
Short name T105
Test name
Test status
Simulation time 33199151636 ps
CPU time 3848.13 seconds
Started Jul 04 04:50:25 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 331988 kb
Host smart-470bacaf-b4e8-47e5-9e09-d268dad8dd19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818009476 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3818009476
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2526850368
Short name T402
Test name
Test status
Simulation time 73558091247 ps
CPU time 2071.84 seconds
Started Jul 04 04:50:34 PM PDT 24
Finished Jul 04 05:25:07 PM PDT 24
Peak memory 273780 kb
Host smart-aaa13f07-d376-4d2d-b5bf-92e27d549876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526850368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2526850368
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1290319846
Short name T687
Test name
Test status
Simulation time 3502412335 ps
CPU time 205.98 seconds
Started Jul 04 04:50:26 PM PDT 24
Finished Jul 04 04:53:52 PM PDT 24
Peak memory 257500 kb
Host smart-6c252bf8-992a-41a6-8077-81f694218aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12903
19846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1290319846
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2944163311
Short name T530
Test name
Test status
Simulation time 256926145 ps
CPU time 33.66 seconds
Started Jul 04 04:50:24 PM PDT 24
Finished Jul 04 04:50:58 PM PDT 24
Peak memory 248712 kb
Host smart-133ffc46-73aa-440b-96d4-ef5821c5b2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
63311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2944163311
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3898162664
Short name T320
Test name
Test status
Simulation time 46267147537 ps
CPU time 1257.58 seconds
Started Jul 04 04:50:36 PM PDT 24
Finished Jul 04 05:11:34 PM PDT 24
Peak memory 273480 kb
Host smart-0284caa3-f91a-454e-95c9-35393efe7429
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898162664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3898162664
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.142373021
Short name T277
Test name
Test status
Simulation time 74079665300 ps
CPU time 2453.89 seconds
Started Jul 04 04:50:33 PM PDT 24
Finished Jul 04 05:31:28 PM PDT 24
Peak memory 289380 kb
Host smart-442ddc08-4c17-4ba4-a7f6-11869eec364d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142373021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.142373021
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1398173509
Short name T611
Test name
Test status
Simulation time 51541900735 ps
CPU time 548.6 seconds
Started Jul 04 04:50:34 PM PDT 24
Finished Jul 04 04:59:42 PM PDT 24
Peak memory 256076 kb
Host smart-53392fc9-e9f7-4cd9-85c8-7f12d111abfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398173509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1398173509
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.969426156
Short name T238
Test name
Test status
Simulation time 990455927 ps
CPU time 40.83 seconds
Started Jul 04 04:50:27 PM PDT 24
Finished Jul 04 04:51:08 PM PDT 24
Peak memory 256400 kb
Host smart-7a04dadc-2c96-402d-bda1-c6846ede1e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96942
6156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.969426156
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3014847613
Short name T56
Test name
Test status
Simulation time 701488264 ps
CPU time 19 seconds
Started Jul 04 04:50:26 PM PDT 24
Finished Jul 04 04:50:45 PM PDT 24
Peak memory 256736 kb
Host smart-5965ea0e-e839-478f-bf52-c4c0984a29c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30148
47613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3014847613
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3395816058
Short name T497
Test name
Test status
Simulation time 1479636411 ps
CPU time 51.76 seconds
Started Jul 04 04:50:26 PM PDT 24
Finished Jul 04 04:51:18 PM PDT 24
Peak memory 256724 kb
Host smart-85c7f7dd-b2f2-42b5-bd92-06629dc8062e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33958
16058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3395816058
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3129973839
Short name T370
Test name
Test status
Simulation time 862955447 ps
CPU time 59.73 seconds
Started Jul 04 04:50:27 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 257332 kb
Host smart-b5bc6ea2-57c6-4f66-88fa-2d9a20af6098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31299
73839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3129973839
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.734863627
Short name T94
Test name
Test status
Simulation time 49504882666 ps
CPU time 1698.14 seconds
Started Jul 04 04:50:33 PM PDT 24
Finished Jul 04 05:18:52 PM PDT 24
Peak memory 289116 kb
Host smart-acb42363-3a7c-474f-8e3a-e11d8b34d9e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734863627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.734863627
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3021913072
Short name T698
Test name
Test status
Simulation time 468506629739 ps
CPU time 2549.16 seconds
Started Jul 04 04:50:36 PM PDT 24
Finished Jul 04 05:33:05 PM PDT 24
Peak memory 289888 kb
Host smart-86bbb35c-7fb6-4478-82bd-bc77aeea1ba0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021913072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3021913072
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2551794747
Short name T356
Test name
Test status
Simulation time 18257299406 ps
CPU time 90.89 seconds
Started Jul 04 04:50:36 PM PDT 24
Finished Jul 04 04:52:07 PM PDT 24
Peak memory 256976 kb
Host smart-01a99cad-4ce2-47eb-aa75-c9c42095dd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25517
94747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2551794747
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.435366218
Short name T520
Test name
Test status
Simulation time 52797733 ps
CPU time 6.97 seconds
Started Jul 04 04:50:34 PM PDT 24
Finished Jul 04 04:50:41 PM PDT 24
Peak memory 249660 kb
Host smart-62b4985a-2588-43ac-9a9a-29a1567dcefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43536
6218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.435366218
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.724347586
Short name T650
Test name
Test status
Simulation time 26933819817 ps
CPU time 1362.72 seconds
Started Jul 04 04:50:35 PM PDT 24
Finished Jul 04 05:13:18 PM PDT 24
Peak memory 289568 kb
Host smart-f17d0e1d-cc0f-4c51-bfa5-e30416bbeba7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724347586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.724347586
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1991848923
Short name T448
Test name
Test status
Simulation time 26290044239 ps
CPU time 1330.23 seconds
Started Jul 04 04:50:34 PM PDT 24
Finished Jul 04 05:12:45 PM PDT 24
Peak memory 288976 kb
Host smart-ed26c000-3217-487c-b799-32cee8ee320e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991848923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1991848923
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4212142379
Short name T426
Test name
Test status
Simulation time 6142231606 ps
CPU time 246.01 seconds
Started Jul 04 04:50:32 PM PDT 24
Finished Jul 04 04:54:38 PM PDT 24
Peak memory 248192 kb
Host smart-b8c72254-dcc0-433c-b709-1c03da0e7f4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212142379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4212142379
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2985663983
Short name T495
Test name
Test status
Simulation time 679635713 ps
CPU time 38.32 seconds
Started Jul 04 04:50:34 PM PDT 24
Finished Jul 04 04:51:12 PM PDT 24
Peak memory 256728 kb
Host smart-992e5746-125c-4aae-a8d0-bc251c520142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29856
63983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2985663983
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3049767603
Short name T89
Test name
Test status
Simulation time 848918604 ps
CPU time 49.28 seconds
Started Jul 04 04:50:35 PM PDT 24
Finished Jul 04 04:51:25 PM PDT 24
Peak memory 249128 kb
Host smart-c27b9ebf-ab30-4f13-88ac-feb5ed9a5714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30497
67603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3049767603
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1233765382
Short name T646
Test name
Test status
Simulation time 2530987431 ps
CPU time 52.03 seconds
Started Jul 04 04:50:34 PM PDT 24
Finished Jul 04 04:51:27 PM PDT 24
Peak memory 249308 kb
Host smart-cd5f6058-4b4d-4de7-9223-ecce7bb8f6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12337
65382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1233765382
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2475564229
Short name T350
Test name
Test status
Simulation time 238289620 ps
CPU time 19.43 seconds
Started Jul 04 04:50:33 PM PDT 24
Finished Jul 04 04:50:53 PM PDT 24
Peak memory 256988 kb
Host smart-0cb78d97-4e92-496e-b512-be36a892acbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24755
64229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2475564229
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1345784736
Short name T262
Test name
Test status
Simulation time 139969575040 ps
CPU time 1963.72 seconds
Started Jul 04 04:50:36 PM PDT 24
Finished Jul 04 05:23:20 PM PDT 24
Peak memory 272952 kb
Host smart-0ee67550-05c6-4aa0-a1aa-1bfe5f7ae9b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345784736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1345784736
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1904272474
Short name T673
Test name
Test status
Simulation time 961930827 ps
CPU time 85.84 seconds
Started Jul 04 04:50:36 PM PDT 24
Finished Jul 04 04:52:02 PM PDT 24
Peak memory 256732 kb
Host smart-91c640e0-d292-4d2b-974f-43ca024d5e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19042
72474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1904272474
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.728576151
Short name T439
Test name
Test status
Simulation time 2289880662 ps
CPU time 38.22 seconds
Started Jul 04 04:50:35 PM PDT 24
Finished Jul 04 04:51:13 PM PDT 24
Peak memory 248936 kb
Host smart-b0dfc170-4fda-4d4c-ab2f-c0511c76100b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72857
6151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.728576151
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.12193487
Short name T583
Test name
Test status
Simulation time 50805809838 ps
CPU time 2678.86 seconds
Started Jul 04 04:50:36 PM PDT 24
Finished Jul 04 05:35:15 PM PDT 24
Peak memory 287292 kb
Host smart-be212ef0-d1dd-422e-a228-17fb364fec88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12193487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.12193487
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2753702467
Short name T685
Test name
Test status
Simulation time 172599908877 ps
CPU time 2564.88 seconds
Started Jul 04 04:50:43 PM PDT 24
Finished Jul 04 05:33:28 PM PDT 24
Peak memory 283548 kb
Host smart-55facc90-17d9-4db7-8573-571b49131715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753702467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2753702467
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2564474644
Short name T272
Test name
Test status
Simulation time 34264559355 ps
CPU time 346.66 seconds
Started Jul 04 04:50:37 PM PDT 24
Finished Jul 04 04:56:23 PM PDT 24
Peak memory 257056 kb
Host smart-27c61c59-f6b2-4dce-9a9e-66e8d40ee579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564474644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2564474644
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1905799429
Short name T651
Test name
Test status
Simulation time 108493790 ps
CPU time 4.05 seconds
Started Jul 04 04:50:33 PM PDT 24
Finished Jul 04 04:50:37 PM PDT 24
Peak memory 249176 kb
Host smart-ab3edfea-e41a-4c51-9369-7a31b54d5692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19057
99429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1905799429
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1727865873
Short name T636
Test name
Test status
Simulation time 2876872509 ps
CPU time 55.53 seconds
Started Jul 04 04:50:39 PM PDT 24
Finished Jul 04 04:51:34 PM PDT 24
Peak memory 256664 kb
Host smart-d9d51e4a-bae1-4e8f-9d3c-84fe22471334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17278
65873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1727865873
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.259099954
Short name T95
Test name
Test status
Simulation time 1881746257 ps
CPU time 50.16 seconds
Started Jul 04 04:50:32 PM PDT 24
Finished Jul 04 04:51:23 PM PDT 24
Peak memory 248888 kb
Host smart-e246fac2-4a06-4890-bb93-56edf8b68d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25909
9954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.259099954
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2860581132
Short name T391
Test name
Test status
Simulation time 921328100 ps
CPU time 20.15 seconds
Started Jul 04 04:50:36 PM PDT 24
Finished Jul 04 04:50:57 PM PDT 24
Peak memory 256004 kb
Host smart-5ef5cf81-78aa-4c2f-8939-352f87fa69a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
81132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2860581132
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1758137559
Short name T127
Test name
Test status
Simulation time 277958509767 ps
CPU time 3703.94 seconds
Started Jul 04 04:50:42 PM PDT 24
Finished Jul 04 05:52:27 PM PDT 24
Peak memory 299296 kb
Host smart-d38df3f3-0ebf-4647-b8a2-9baa466906e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758137559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1758137559
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2536176743
Short name T700
Test name
Test status
Simulation time 216373680643 ps
CPU time 3284.4 seconds
Started Jul 04 04:50:45 PM PDT 24
Finished Jul 04 05:45:30 PM PDT 24
Peak memory 289796 kb
Host smart-b6d45f6c-2b58-43e9-bfaf-c0e32d0e25d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536176743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2536176743
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2320623211
Short name T401
Test name
Test status
Simulation time 4215072225 ps
CPU time 240.19 seconds
Started Jul 04 04:50:43 PM PDT 24
Finished Jul 04 04:54:44 PM PDT 24
Peak memory 257460 kb
Host smart-4a915130-988e-489e-b358-3f77b2a7f8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23206
23211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2320623211
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2820906362
Short name T466
Test name
Test status
Simulation time 724878822 ps
CPU time 24.79 seconds
Started Jul 04 04:50:45 PM PDT 24
Finished Jul 04 04:51:10 PM PDT 24
Peak memory 256896 kb
Host smart-9dca7edf-797b-434c-a5b4-6daaec9819a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28209
06362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2820906362
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3075133225
Short name T657
Test name
Test status
Simulation time 120479974604 ps
CPU time 1974.3 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 05:23:36 PM PDT 24
Peak memory 285224 kb
Host smart-9bc4326a-d529-44a3-979e-5d8840c384c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075133225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3075133225
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4177298515
Short name T49
Test name
Test status
Simulation time 82781140297 ps
CPU time 2506.21 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 05:32:28 PM PDT 24
Peak memory 290068 kb
Host smart-8d7f1dff-0145-4506-a49e-2499cf81f3a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177298515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4177298515
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1149462381
Short name T568
Test name
Test status
Simulation time 4780761923 ps
CPU time 114.81 seconds
Started Jul 04 04:50:42 PM PDT 24
Finished Jul 04 04:52:37 PM PDT 24
Peak memory 255456 kb
Host smart-332f881e-f96e-422c-b394-ad1e08c1791b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149462381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1149462381
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3481512848
Short name T494
Test name
Test status
Simulation time 303912363 ps
CPU time 4.07 seconds
Started Jul 04 04:50:45 PM PDT 24
Finished Jul 04 04:50:49 PM PDT 24
Peak memory 249156 kb
Host smart-85300d13-206b-4772-a102-88e4ecf63174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34815
12848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3481512848
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.980221638
Short name T353
Test name
Test status
Simulation time 1044314216 ps
CPU time 30.72 seconds
Started Jul 04 04:50:43 PM PDT 24
Finished Jul 04 04:51:14 PM PDT 24
Peak memory 248636 kb
Host smart-500a824e-b974-4489-b643-6f2e7aff32a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98022
1638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.980221638
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.227094382
Short name T59
Test name
Test status
Simulation time 891850943 ps
CPU time 15.84 seconds
Started Jul 04 04:50:47 PM PDT 24
Finished Jul 04 04:51:03 PM PDT 24
Peak memory 249120 kb
Host smart-4eabe9bb-fb50-4a27-9cbc-268e48f797fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22709
4382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.227094382
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1459886416
Short name T689
Test name
Test status
Simulation time 1939890089 ps
CPU time 30.29 seconds
Started Jul 04 04:50:43 PM PDT 24
Finished Jul 04 04:51:14 PM PDT 24
Peak memory 257108 kb
Host smart-68f05fd9-9f5c-4027-a600-6f5786a77018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14598
86416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1459886416
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1274015651
Short name T558
Test name
Test status
Simulation time 3174023934 ps
CPU time 85.04 seconds
Started Jul 04 04:50:43 PM PDT 24
Finished Jul 04 04:52:08 PM PDT 24
Peak memory 257532 kb
Host smart-e5c81544-ab7a-40da-9aa5-194ed62a3311
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274015651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1274015651
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1055958760
Short name T572
Test name
Test status
Simulation time 148408059916 ps
CPU time 1089.91 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 05:08:51 PM PDT 24
Peak memory 270804 kb
Host smart-d4839ff3-5f45-4a11-84b2-bcebf766aaa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055958760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1055958760
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1372706901
Short name T281
Test name
Test status
Simulation time 6153218171 ps
CPU time 328.29 seconds
Started Jul 04 04:50:45 PM PDT 24
Finished Jul 04 04:56:14 PM PDT 24
Peak memory 257028 kb
Host smart-9c86b6e5-205b-4656-ba54-0f18ee287930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13727
06901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1372706901
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2907008834
Short name T90
Test name
Test status
Simulation time 574960365 ps
CPU time 35.55 seconds
Started Jul 04 04:50:45 PM PDT 24
Finished Jul 04 04:51:20 PM PDT 24
Peak memory 249156 kb
Host smart-d160ab8f-12e5-4cce-bef5-c9302c513ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29070
08834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2907008834
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2437587180
Short name T509
Test name
Test status
Simulation time 20768670473 ps
CPU time 932.93 seconds
Started Jul 04 04:50:42 PM PDT 24
Finished Jul 04 05:06:15 PM PDT 24
Peak memory 273776 kb
Host smart-599d37df-a37d-40cf-85ed-24c77a433183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437587180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2437587180
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.735366337
Short name T504
Test name
Test status
Simulation time 167874990193 ps
CPU time 2362.91 seconds
Started Jul 04 04:50:42 PM PDT 24
Finished Jul 04 05:30:06 PM PDT 24
Peak memory 289296 kb
Host smart-c8812552-0d42-4273-ad33-ae6fb11618a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735366337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.735366337
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3953687642
Short name T301
Test name
Test status
Simulation time 26841968292 ps
CPU time 596.57 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 05:00:38 PM PDT 24
Peak memory 249272 kb
Host smart-c640fa1d-41cf-45c1-bd7e-7d07d33f2753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953687642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3953687642
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2433694009
Short name T635
Test name
Test status
Simulation time 524974017 ps
CPU time 37.59 seconds
Started Jul 04 04:50:44 PM PDT 24
Finished Jul 04 04:51:21 PM PDT 24
Peak memory 256644 kb
Host smart-6afd2586-3576-45ea-8759-018c7c150926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24336
94009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2433694009
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1357200352
Short name T535
Test name
Test status
Simulation time 9413505983 ps
CPU time 76.2 seconds
Started Jul 04 04:50:40 PM PDT 24
Finished Jul 04 04:51:57 PM PDT 24
Peak memory 248992 kb
Host smart-654fddbc-41f5-4213-aa90-034d29b5270b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
00352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1357200352
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3562628276
Short name T392
Test name
Test status
Simulation time 569041034 ps
CPU time 39.55 seconds
Started Jul 04 04:50:41 PM PDT 24
Finished Jul 04 04:51:21 PM PDT 24
Peak memory 248924 kb
Host smart-68080d70-68f4-4488-9ed4-55d270204246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35626
28276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3562628276
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.117312017
Short name T433
Test name
Test status
Simulation time 376350872 ps
CPU time 29.95 seconds
Started Jul 04 04:50:46 PM PDT 24
Finished Jul 04 04:51:16 PM PDT 24
Peak memory 257316 kb
Host smart-fe2efd46-7e40-4f1c-871c-d2815afa1021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
2017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.117312017
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1265945196
Short name T601
Test name
Test status
Simulation time 2954653720 ps
CPU time 174.25 seconds
Started Jul 04 04:50:47 PM PDT 24
Finished Jul 04 04:53:41 PM PDT 24
Peak memory 257496 kb
Host smart-e4c4d39d-c070-404f-aabc-ae8ce20a2484
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265945196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1265945196
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4073144419
Short name T229
Test name
Test status
Simulation time 33305136 ps
CPU time 3.37 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:49:15 PM PDT 24
Peak memory 249432 kb
Host smart-fd70a9d0-2214-416f-a66c-b384fe3aa155
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4073144419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4073144419
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.985086084
Short name T423
Test name
Test status
Simulation time 178782510 ps
CPU time 10.78 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:49:08 PM PDT 24
Peak memory 249060 kb
Host smart-d3eb3cf0-9c67-4386-9b9a-501fa1224b34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=985086084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.985086084
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3402795942
Short name T37
Test name
Test status
Simulation time 1539650274 ps
CPU time 84.75 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 04:50:33 PM PDT 24
Peak memory 256696 kb
Host smart-b9630275-17b1-4d52-a898-4af76d225eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34027
95942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3402795942
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3905445397
Short name T86
Test name
Test status
Simulation time 823848043 ps
CPU time 49.71 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:50:00 PM PDT 24
Peak memory 256044 kb
Host smart-8b700355-e0e1-45a8-bcbe-78870f21c163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39054
45397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3905445397
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.808113555
Short name T327
Test name
Test status
Simulation time 225220419871 ps
CPU time 2671.82 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 05:33:34 PM PDT 24
Peak memory 287244 kb
Host smart-86747d79-1c72-4140-a69c-215fe0409e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808113555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.808113555
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.373026701
Short name T488
Test name
Test status
Simulation time 40794604466 ps
CPU time 2370.74 seconds
Started Jul 04 04:49:22 PM PDT 24
Finished Jul 04 05:28:53 PM PDT 24
Peak memory 283256 kb
Host smart-f69fddf9-ef04-45b1-b75d-7369751b4c99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373026701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.373026701
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.336013925
Short name T483
Test name
Test status
Simulation time 706528116 ps
CPU time 47.22 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:49:48 PM PDT 24
Peak memory 257252 kb
Host smart-89bd72e3-1645-47b1-9cec-eb8c624df6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33601
3925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.336013925
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3281041977
Short name T577
Test name
Test status
Simulation time 2298730591 ps
CPU time 34.72 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:36 PM PDT 24
Peak memory 256992 kb
Host smart-f92a5f68-ff56-45eb-8c6d-847da082ad8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32810
41977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3281041977
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.593891301
Short name T284
Test name
Test status
Simulation time 5176744678 ps
CPU time 61.95 seconds
Started Jul 04 04:49:02 PM PDT 24
Finished Jul 04 04:50:04 PM PDT 24
Peak memory 256712 kb
Host smart-85dc284f-3e99-4942-bcbf-0202b9c7174c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59389
1301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.593891301
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2090327087
Short name T114
Test name
Test status
Simulation time 3589420911 ps
CPU time 44.66 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 04:49:46 PM PDT 24
Peak memory 249612 kb
Host smart-e470dcbe-b37d-4ef3-838c-a5b3781a120b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
27087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2090327087
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3410060496
Short name T41
Test name
Test status
Simulation time 620824835 ps
CPU time 54.08 seconds
Started Jul 04 04:48:56 PM PDT 24
Finished Jul 04 04:49:50 PM PDT 24
Peak memory 257312 kb
Host smart-0d13d71a-fc4d-4102-8af7-29231192cd4b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410060496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3410060496
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2492791047
Short name T117
Test name
Test status
Simulation time 48830572731 ps
CPU time 795.94 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 05:02:28 PM PDT 24
Peak memory 270696 kb
Host smart-66493791-17d1-440e-a319-2313d3fd2fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492791047 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2492791047
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3812564476
Short name T226
Test name
Test status
Simulation time 49169639 ps
CPU time 3.08 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 04:49:06 PM PDT 24
Peak memory 249404 kb
Host smart-d1cfa3b4-ac69-4898-8340-1744556fa334
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3812564476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3812564476
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2316400708
Short name T591
Test name
Test status
Simulation time 29989788603 ps
CPU time 801.48 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 05:02:34 PM PDT 24
Peak memory 273756 kb
Host smart-75b506aa-ef83-42f8-9340-c7716fb396e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316400708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2316400708
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.4165751192
Short name T489
Test name
Test status
Simulation time 253362550 ps
CPU time 9.34 seconds
Started Jul 04 04:49:03 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 249140 kb
Host smart-e084cd5a-7472-45ff-8f89-b9f79a2671b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4165751192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.4165751192
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2108832241
Short name T549
Test name
Test status
Simulation time 151011425 ps
CPU time 4.25 seconds
Started Jul 04 04:49:22 PM PDT 24
Finished Jul 04 04:49:27 PM PDT 24
Peak memory 240972 kb
Host smart-6be39a53-45a8-4bfe-922e-662f1693b48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21088
32241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2108832241
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1603683932
Short name T695
Test name
Test status
Simulation time 49663932 ps
CPU time 2.91 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:17 PM PDT 24
Peak memory 240520 kb
Host smart-81ed3825-acd3-4088-aee8-dd511ffcfad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
83932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1603683932
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3029777560
Short name T331
Test name
Test status
Simulation time 45015021207 ps
CPU time 2708.75 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 05:34:20 PM PDT 24
Peak memory 286324 kb
Host smart-8885028b-f0d7-481a-8c2d-e898316e4bbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029777560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3029777560
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4047774683
Short name T602
Test name
Test status
Simulation time 28416027048 ps
CPU time 720.99 seconds
Started Jul 04 04:49:02 PM PDT 24
Finished Jul 04 05:01:03 PM PDT 24
Peak memory 266812 kb
Host smart-4957c58e-0c5d-497a-b951-876798de9788
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047774683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4047774683
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.971281171
Short name T39
Test name
Test status
Simulation time 17162764638 ps
CPU time 183.47 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:52:13 PM PDT 24
Peak memory 249280 kb
Host smart-5d259808-ec9b-4b1a-ae46-6bf6e3d89f71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971281171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.971281171
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1469642873
Short name T674
Test name
Test status
Simulation time 53322444 ps
CPU time 4.91 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:49:15 PM PDT 24
Peak memory 249112 kb
Host smart-dc502344-5abc-4b17-8d96-aac7d98d26c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14696
42873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1469642873
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3659601216
Short name T545
Test name
Test status
Simulation time 405424261 ps
CPU time 20.24 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:34 PM PDT 24
Peak memory 249180 kb
Host smart-5f42f749-3ce7-4053-8f56-f72245af95e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36596
01216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3659601216
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2323814868
Short name T598
Test name
Test status
Simulation time 3749526820 ps
CPU time 61.48 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:50:12 PM PDT 24
Peak memory 257424 kb
Host smart-4c21497e-828c-427d-a524-33f7fa367601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23238
14868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2323814868
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1903789087
Short name T465
Test name
Test status
Simulation time 1126013415 ps
CPU time 58.38 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:50:08 PM PDT 24
Peak memory 257324 kb
Host smart-7735a1e8-320d-46da-9114-476c2fa322f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
89087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1903789087
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2645184088
Short name T274
Test name
Test status
Simulation time 42902443338 ps
CPU time 2692.03 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 05:33:54 PM PDT 24
Peak memory 290192 kb
Host smart-99de1aea-fa2d-40cc-8d35-cb59dad3d8f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645184088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2645184088
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3343392849
Short name T225
Test name
Test status
Simulation time 136125249 ps
CPU time 3.64 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:05 PM PDT 24
Peak memory 249368 kb
Host smart-13cb0081-8fee-4e80-b3c7-a01933b6e74c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3343392849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3343392849
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3596996900
Short name T629
Test name
Test status
Simulation time 9803201554 ps
CPU time 839.1 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 05:02:58 PM PDT 24
Peak memory 273780 kb
Host smart-c9db2178-8117-465d-bcd0-7b98e2eb9d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596996900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3596996900
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1887296382
Short name T367
Test name
Test status
Simulation time 518683420 ps
CPU time 14.88 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 04:49:23 PM PDT 24
Peak memory 248928 kb
Host smart-5ae3d5af-3241-48b6-bcb9-7091a987a62e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1887296382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1887296382
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.844538783
Short name T432
Test name
Test status
Simulation time 1102138967 ps
CPU time 16.15 seconds
Started Jul 04 04:49:17 PM PDT 24
Finished Jul 04 04:49:33 PM PDT 24
Peak memory 255284 kb
Host smart-e1e2396a-6f1a-4b32-83c8-433c02e822fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84453
8783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.844538783
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3912244422
Short name T513
Test name
Test status
Simulation time 81431903 ps
CPU time 8.59 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:10 PM PDT 24
Peak memory 248720 kb
Host smart-a790dea1-a61b-47d7-9d48-007be80d7654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39122
44422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3912244422
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3462540810
Short name T666
Test name
Test status
Simulation time 78011945837 ps
CPU time 1310.17 seconds
Started Jul 04 04:49:12 PM PDT 24
Finished Jul 04 05:11:03 PM PDT 24
Peak memory 273044 kb
Host smart-4f4dfd54-1d68-430a-990e-56bbeb622683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462540810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3462540810
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1126110503
Short name T661
Test name
Test status
Simulation time 25661701052 ps
CPU time 1438.55 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 272636 kb
Host smart-d54561d3-a592-4301-8aab-2884323cd3a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126110503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1126110503
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.560535290
Short name T8
Test name
Test status
Simulation time 10573352555 ps
CPU time 217.96 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:52:47 PM PDT 24
Peak memory 249144 kb
Host smart-4a83f91a-e083-4639-927d-8c337ec31d2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560535290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.560535290
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2061790416
Short name T352
Test name
Test status
Simulation time 881555216 ps
CPU time 33.95 seconds
Started Jul 04 04:49:01 PM PDT 24
Finished Jul 04 04:49:36 PM PDT 24
Peak memory 256368 kb
Host smart-bc48edf5-862b-4b53-bca9-78731070470c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
90416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2061790416
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2988126026
Short name T477
Test name
Test status
Simulation time 1163812370 ps
CPU time 35.74 seconds
Started Jul 04 04:49:16 PM PDT 24
Finished Jul 04 04:49:52 PM PDT 24
Peak memory 249156 kb
Host smart-9c526090-fed7-41df-bc3f-398b735850b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
26026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2988126026
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.913989101
Short name T103
Test name
Test status
Simulation time 1578942019 ps
CPU time 45.65 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:50:00 PM PDT 24
Peak memory 249524 kb
Host smart-0110c303-69ba-4c1a-b52d-e74fc270fe0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91398
9101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.913989101
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3287078125
Short name T418
Test name
Test status
Simulation time 2457426129 ps
CPU time 67.74 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:50:17 PM PDT 24
Peak memory 257400 kb
Host smart-20675647-ccc0-4ee5-9fde-8c07be7c2a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32870
78125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3287078125
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2930570282
Short name T609
Test name
Test status
Simulation time 2771829100 ps
CPU time 32.72 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:49:42 PM PDT 24
Peak memory 256952 kb
Host smart-1a1356f0-774c-4d46-95b7-d184ad670611
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930570282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2930570282
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.177716921
Short name T230
Test name
Test status
Simulation time 46184051 ps
CPU time 4.57 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:49:15 PM PDT 24
Peak memory 249460 kb
Host smart-2d442e89-22d0-4bc8-b5bc-f4448fa10131
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=177716921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.177716921
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2503428955
Short name T29
Test name
Test status
Simulation time 75547648418 ps
CPU time 1648.99 seconds
Started Jul 04 04:49:07 PM PDT 24
Finished Jul 04 05:16:37 PM PDT 24
Peak memory 290228 kb
Host smart-05984932-cc6d-4afb-ad51-406cb12cd921
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503428955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2503428955
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2350790174
Short name T381
Test name
Test status
Simulation time 159622144 ps
CPU time 10.53 seconds
Started Jul 04 04:49:27 PM PDT 24
Finished Jul 04 04:49:38 PM PDT 24
Peak memory 249144 kb
Host smart-73039d33-2ba3-4a41-83c1-970fa50cb870
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2350790174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2350790174
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3708609743
Short name T699
Test name
Test status
Simulation time 2635613544 ps
CPU time 131.06 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 04:51:21 PM PDT 24
Peak memory 251464 kb
Host smart-f1724500-0e10-4bbb-8c1e-d4866ae26809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37086
09743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3708609743
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2142367268
Short name T517
Test name
Test status
Simulation time 1038679159 ps
CPU time 55.12 seconds
Started Jul 04 04:49:15 PM PDT 24
Finished Jul 04 04:50:10 PM PDT 24
Peak memory 257300 kb
Host smart-264c672f-9c18-4730-9e57-97f3450093bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423
67268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2142367268
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2877921707
Short name T324
Test name
Test status
Simulation time 27428925897 ps
CPU time 1367.08 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 05:11:58 PM PDT 24
Peak memory 287728 kb
Host smart-8130f193-55b8-4232-a7f4-5a2036f8a3a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877921707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2877921707
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1127836543
Short name T474
Test name
Test status
Simulation time 44654859424 ps
CPU time 1068.88 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 05:06:55 PM PDT 24
Peak memory 266628 kb
Host smart-7a1258f1-a110-4da8-9b8a-5ce192f6cdaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127836543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1127836543
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.79495482
Short name T588
Test name
Test status
Simulation time 5685741434 ps
CPU time 232.16 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 04:53:03 PM PDT 24
Peak memory 249268 kb
Host smart-bfdd8ede-9925-4deb-801c-f64388375fb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79495482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.79495482
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.916793043
Short name T573
Test name
Test status
Simulation time 909120116 ps
CPU time 48.15 seconds
Started Jul 04 04:49:11 PM PDT 24
Finished Jul 04 04:50:00 PM PDT 24
Peak memory 249144 kb
Host smart-0d0b5a37-173f-4f6f-8da3-4765eed8a3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91679
3043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.916793043
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3616361231
Short name T668
Test name
Test status
Simulation time 4277858063 ps
CPU time 69.03 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:50:23 PM PDT 24
Peak memory 248840 kb
Host smart-8f82255e-c7ad-4922-975f-73a462756a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36163
61231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3616361231
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3837524888
Short name T30
Test name
Test status
Simulation time 124861177 ps
CPU time 5.92 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:12 PM PDT 24
Peak memory 240896 kb
Host smart-13a22996-afa4-4f87-855a-d833d84b1586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375
24888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3837524888
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1486248224
Short name T556
Test name
Test status
Simulation time 1559712392 ps
CPU time 33.05 seconds
Started Jul 04 04:49:15 PM PDT 24
Finished Jul 04 04:49:48 PM PDT 24
Peak memory 257336 kb
Host smart-a2f60a6a-49a5-43a9-ad0c-91c584193b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14862
48224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1486248224
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1181434366
Short name T68
Test name
Test status
Simulation time 19223677675 ps
CPU time 1322.61 seconds
Started Jul 04 04:49:00 PM PDT 24
Finished Jul 04 05:11:04 PM PDT 24
Peak memory 272400 kb
Host smart-bc3f68ba-0ebb-4448-84d1-88edd8e86c16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181434366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1181434366
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.304586032
Short name T594
Test name
Test status
Simulation time 65556890987 ps
CPU time 1843.21 seconds
Started Jul 04 04:49:21 PM PDT 24
Finished Jul 04 05:20:04 PM PDT 24
Peak memory 305860 kb
Host smart-e627c614-91af-4db6-ac8b-f60e810fab86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304586032 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.304586032
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.133220675
Short name T222
Test name
Test status
Simulation time 167108482 ps
CPU time 4.55 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:49:11 PM PDT 24
Peak memory 249456 kb
Host smart-8df06dcb-9a5c-403d-a5cc-cdef1add7932
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=133220675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.133220675
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3112825987
Short name T74
Test name
Test status
Simulation time 65439074445 ps
CPU time 2022.27 seconds
Started Jul 04 04:49:10 PM PDT 24
Finished Jul 04 05:22:54 PM PDT 24
Peak memory 287364 kb
Host smart-adb0fdb6-efb2-4699-a04e-3caf8487908d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112825987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3112825987
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2419663199
Short name T539
Test name
Test status
Simulation time 1429801365 ps
CPU time 27.7 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 04:49:37 PM PDT 24
Peak memory 257372 kb
Host smart-a39f334a-e309-4755-bf8f-7c61b39e2be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24196
63199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2419663199
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2914689288
Short name T528
Test name
Test status
Simulation time 938601695 ps
CPU time 21.68 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 04:49:36 PM PDT 24
Peak memory 249120 kb
Host smart-890d8401-b35b-4502-8ef0-a9e9d4e691a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29146
89288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2914689288
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3831593907
Short name T329
Test name
Test status
Simulation time 37123979534 ps
CPU time 1688.05 seconds
Started Jul 04 04:49:13 PM PDT 24
Finished Jul 04 05:17:22 PM PDT 24
Peak memory 273224 kb
Host smart-4052bb96-90aa-41d7-92ff-39df93d2dbdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831593907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3831593907
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.69959559
Short name T505
Test name
Test status
Simulation time 29095526277 ps
CPU time 1869.46 seconds
Started Jul 04 04:49:09 PM PDT 24
Finished Jul 04 05:20:20 PM PDT 24
Peak memory 285316 kb
Host smart-bd2bc581-9c1b-4bf1-b5eb-62d7f1f30ffd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69959559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.69959559
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3157998356
Short name T300
Test name
Test status
Simulation time 14206672978 ps
CPU time 266.72 seconds
Started Jul 04 04:49:06 PM PDT 24
Finished Jul 04 04:53:33 PM PDT 24
Peak memory 249264 kb
Host smart-dfb02da9-dedc-41b0-ba1c-cd0ccfde7d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157998356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3157998356
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3620843490
Short name T438
Test name
Test status
Simulation time 377911172 ps
CPU time 23.89 seconds
Started Jul 04 04:48:57 PM PDT 24
Finished Jul 04 04:49:22 PM PDT 24
Peak memory 249176 kb
Host smart-889b4c04-494c-422b-99e6-a9640ab168ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36208
43490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3620843490
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4261027651
Short name T396
Test name
Test status
Simulation time 12591270246 ps
CPU time 62.95 seconds
Started Jul 04 04:48:58 PM PDT 24
Finished Jul 04 04:50:02 PM PDT 24
Peak memory 249008 kb
Host smart-01e9ffa3-b86e-4e36-b7fa-2364d0a2cd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42610
27651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4261027651
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1899090845
Short name T581
Test name
Test status
Simulation time 294557129 ps
CPU time 43.25 seconds
Started Jul 04 04:48:59 PM PDT 24
Finished Jul 04 04:49:43 PM PDT 24
Peak memory 257360 kb
Host smart-0651db8c-d6f0-493f-8b5c-d1083e2e3347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18990
90845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1899090845
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1906754581
Short name T414
Test name
Test status
Simulation time 410000976 ps
CPU time 35.09 seconds
Started Jul 04 04:49:04 PM PDT 24
Finished Jul 04 04:49:40 PM PDT 24
Peak memory 256608 kb
Host smart-9240025e-9537-4162-9f79-145ba6980938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19067
54581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1906754581
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.911383479
Short name T88
Test name
Test status
Simulation time 174938672000 ps
CPU time 2299.03 seconds
Started Jul 04 04:49:08 PM PDT 24
Finished Jul 04 05:27:28 PM PDT 24
Peak memory 290156 kb
Host smart-933fb094-7ad7-4982-85cb-91f8b0315e2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911383479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.911383479
Directory /workspace/9.alert_handler_stress_all/latest
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