Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64096533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31036203

1

T1

291764

T2

3763

T3

291048

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14300718	1			T1	111428		T2	1377		T3	105621
values[0x0]	39491599	1			T1	338633		T2	5444		T3	326504
values[0x1]	41340419	1			T1	403564		T2	5390		T3	409669

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54841581	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40291155

1

T1

400530

T2

4841

T3

409686

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	790366	1			T1	3364		T2	30		T3	3218
valid_sources[0x01]	303464	1			T1	3373		T2	19		T3	3324
valid_sources[0x02]	300710	1			T1	3324		T2	30		T3	3388
valid_sources[0x03]	742099	1			T1	3367		T2	40		T3	3173
valid_sources[0x04]	304083	1			T1	3304		T2	54		T3	3291
valid_sources[0x05]	294120	1			T1	3303		T2	26		T3	3250
valid_sources[0x06]	304938	1			T1	3240		T2	19		T3	3173
valid_sources[0x07]	944293	1			T1	3298		T2	54		T3	3213
valid_sources[0x08]	304658	1			T1	3348		T2	63		T3	3322
valid_sources[0x09]	665829	1			T1	3314		T2	71		T3	3289
valid_sources[0x0a]	305544	1			T1	3432		T2	55		T3	3356
valid_sources[0x0b]	308177	1			T1	3192		T2	41		T3	3261
valid_sources[0x0c]	610193	1			T1	3309		T2	32		T3	3246
valid_sources[0x0d]	306797	1			T1	3411		T2	38		T3	3338
valid_sources[0x0e]	292633	1			T1	3265		T2	29		T3	3355
valid_sources[0x0f]	297474	1			T1	3333		T2	40		T3	3374
valid_sources[0x10]	305418	1			T1	3367		T2	107		T3	3264
valid_sources[0x11]	296406	1			T1	3381		T2	55		T3	3255
valid_sources[0x12]	305461	1			T1	3159		T2	35		T3	3260
valid_sources[0x13]	304430	1			T1	3286		T2	38		T3	3449
valid_sources[0x14]	299816	1			T1	3328		T2	36		T3	3376
valid_sources[0x15]	299326	1			T1	3338		T2	15		T3	3370
valid_sources[0x16]	292865	1			T1	3268		T2	60		T3	3307
valid_sources[0x17]	299868	1			T1	3319		T2	41		T3	3270
valid_sources[0x18]	297992	1			T1	3385		T2	51		T3	3205
valid_sources[0x19]	303790	1			T1	3331		T2	81		T3	3336
valid_sources[0x1a]	299051	1			T1	3258		T2	26		T3	3268
valid_sources[0x1b]	1054680	1			T1	3355		T2	40		T3	3322
valid_sources[0x1c]	297007	1			T1	3333		T2	53		T3	3207
valid_sources[0x1d]	303569	1			T1	3371		T2	22		T3	3378
valid_sources[0x1e]	303712	1			T1	3373		T2	58		T3	3294
valid_sources[0x1f]	301469	1			T1	3341		T2	50		T3	3286
valid_sources[0x20]	648060	1			T1	3350		T2	20		T3	3293
valid_sources[0x21]	293517	1			T1	3316		T2	41		T3	3269
valid_sources[0x22]	707209	1			T1	3332		T2	28		T3	3427
valid_sources[0x23]	302450	1			T1	3404		T2	53		T3	3214
valid_sources[0x24]	304545	1			T1	3473		T2	28		T3	3293
valid_sources[0x25]	309585	1			T1	3367		T2	36		T3	3364
valid_sources[0x26]	307449	1			T1	3299		T2	82		T3	3301
valid_sources[0x27]	310095	1			T1	3238		T2	34		T3	3410
valid_sources[0x28]	788616	1			T1	3242		T2	86		T3	3253
valid_sources[0x29]	517458	1			T1	3312		T2	53		T3	3263
valid_sources[0x2a]	307868	1			T1	3427		T2	31		T3	3304
valid_sources[0x2b]	310286	1			T1	3331		T2	38		T3	3248
valid_sources[0x2c]	302910	1			T1	3338		T2	60		T3	3359
valid_sources[0x2d]	300612	1			T1	3438		T2	46		T3	3306
valid_sources[0x2e]	305049	1			T1	3326		T2	35		T3	3211
valid_sources[0x2f]	301969	1			T1	3421		T2	53		T3	3265
valid_sources[0x30]	314962	1			T1	3330		T2	68		T3	3300
valid_sources[0x31]	316104	1			T1	3360		T2	62		T3	3389
valid_sources[0x32]	323064	1			T1	3307		T2	50		T3	3176
valid_sources[0x33]	296642	1			T1	3278		T2	79		T3	3221
valid_sources[0x34]	295675	1			T1	3365		T2	19		T3	3369
valid_sources[0x35]	303887	1			T1	3380		T2	45		T3	3092
valid_sources[0x36]	304602	1			T1	3337		T2	52		T3	3187
valid_sources[0x37]	299180	1			T1	3386		T2	75		T3	3128
valid_sources[0x38]	301970	1			T1	3388		T2	45		T3	3339
valid_sources[0x39]	305996	1			T1	3356		T2	25		T3	3326
valid_sources[0x3a]	325484	1			T1	3335		T2	45		T3	3264
valid_sources[0x3b]	295172	1			T1	3443		T2	42		T3	3141
valid_sources[0x3c]	299491	1			T1	3311		T2	28		T3	3289
valid_sources[0x3d]	320200	1			T1	3210		T2	27		T3	3301
valid_sources[0x3e]	298246	1			T1	3399		T2	69		T3	3255
valid_sources[0x3f]	298072	1			T1	3358		T2	72		T3	3277
valid_sources[0x40]	765094	1			T1	3389		T2	55		T3	3237
valid_sources[0x41]	303315	1			T1	3301		T2	77		T3	3265
valid_sources[0x42]	300926	1			T1	3197		T2	22		T3	3358
valid_sources[0x43]	305433	1			T1	3348		T2	43		T3	3356
valid_sources[0x44]	304708	1			T1	3251		T2	24		T3	3282
valid_sources[0x45]	695785	1			T1	3308		T2	115		T3	3232
valid_sources[0x46]	298986	1			T1	3428		T2	60		T3	3370
valid_sources[0x47]	298829	1			T1	3427		T2	26		T3	3293
valid_sources[0x48]	295610	1			T1	3351		T2	44		T3	3423
valid_sources[0x49]	301640	1			T1	3365		T2	36		T3	3381
valid_sources[0x4a]	312077	1			T1	3398		T2	46		T3	3252
valid_sources[0x4b]	300105	1			T1	3223		T2	11		T3	3122
valid_sources[0x4c]	299234	1			T1	3405		T2	38		T3	3299
valid_sources[0x4d]	299823	1			T1	3482		T2	41		T3	3251
valid_sources[0x4e]	322274	1			T1	3247		T2	39		T3	3269
valid_sources[0x4f]	305236	1			T1	3362		T2	51		T3	3392
valid_sources[0x50]	305044	1			T1	3226		T2	24		T3	3299
valid_sources[0x51]	299718	1			T1	3329		T2	38		T3	3332
valid_sources[0x52]	694523	1			T1	3394		T2	56		T3	3287
valid_sources[0x53]	294941	1			T1	3316		T2	71		T3	3366
valid_sources[0x54]	298657	1			T1	3329		T2	72		T3	3144
valid_sources[0x55]	307119	1			T1	3248		T2	36		T3	3328
valid_sources[0x56]	293037	1			T1	3255		T2	62		T3	3323
valid_sources[0x57]	300060	1			T1	3229		T2	49		T3	3207
valid_sources[0x58]	320424	1			T1	3257		T2	53		T3	3270
valid_sources[0x59]	300173	1			T1	3437		T2	39		T3	3207
valid_sources[0x5a]	303580	1			T1	3246		T2	45		T3	3196
valid_sources[0x5b]	561518	1			T1	3382		T2	26		T3	3315
valid_sources[0x5c]	616835	1			T1	3293		T2	28		T3	3225
valid_sources[0x5d]	306382	1			T1	3308		T2	37		T3	3297
valid_sources[0x5e]	322186	1			T1	3239		T2	33		T3	3264
valid_sources[0x5f]	303813	1			T1	3342		T2	19		T3	3265
valid_sources[0x60]	299174	1			T1	3413		T2	43		T3	3273
valid_sources[0x61]	297806	1			T1	3313		T2	60		T3	3167
valid_sources[0x62]	304345	1			T1	3360		T2	17		T3	3295
valid_sources[0x63]	668177	1			T1	3225		T2	39		T3	3360
valid_sources[0x64]	305039	1			T1	3321		T2	28		T3	3273
valid_sources[0x65]	291457	1			T1	3311		T2	63		T3	3205
valid_sources[0x66]	293248	1			T1	3421		T2	49		T3	3346
valid_sources[0x67]	300336	1			T1	3289		T2	43		T3	3245
valid_sources[0x68]	304950	1			T1	3284		T2	41		T3	3339
valid_sources[0x69]	604270	1			T1	3381		T2	44		T3	3261
valid_sources[0x6a]	300345	1			T1	3354		T2	44		T3	3269
valid_sources[0x6b]	817444	1			T1	3406		T2	22		T3	3259
valid_sources[0x6c]	362671	1			T1	3365		T2	28		T3	3327
valid_sources[0x6d]	296422	1			T1	3385		T2	64		T3	3205
valid_sources[0x6e]	302420	1			T1	3462		T2	42		T3	3263
valid_sources[0x6f]	302900	1			T1	3297		T2	13		T3	3282
valid_sources[0x70]	673282	1			T1	3381		T2	39		T3	3246
valid_sources[0x71]	502649	1			T1	3403		T2	55		T3	3391
valid_sources[0x72]	301717	1			T1	3283		T2	59		T3	3232
valid_sources[0x73]	314452	1			T1	3358		T2	55		T3	3252
valid_sources[0x74]	342314	1			T1	3335		T2	37		T3	3335
valid_sources[0x75]	312030	1			T1	3299		T2	54		T3	3373
valid_sources[0x76]	307783	1			T1	3336		T2	41		T3	3367
valid_sources[0x77]	721490	1			T1	3340		T2	34		T3	3248
valid_sources[0x78]	298375	1			T1	3227		T2	68		T3	3311
valid_sources[0x79]	537407	1			T1	3291		T2	67		T3	3160
valid_sources[0x7a]	297682	1			T1	3403		T2	80		T3	3287
valid_sources[0x7b]	305249	1			T1	3334		T2	72		T3	3405
valid_sources[0x7c]	312243	1			T1	3324		T2	70		T3	3309
valid_sources[0x7d]	312858	1			T1	3204		T2	45		T3	3369
valid_sources[0x7e]	298433	1			T1	3329		T2	31		T3	3274
valid_sources[0x7f]	293073	1			T1	3292		T2	50		T3	3394
valid_sources[0x80]	297795	1			T1	3139		T2	33		T3	3372

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7124601

1

T1

62889

T2

708

T3

62041

values[0x0]

all_enables

biggest_size

15105037

1

T1

140195

T2

1978

T3

138544

values[0x1]

all_enables

biggest_size

8806565

1

T1

88680

T2

1077

T3

90463