Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T73,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14578	0	0
DisabledNoTrigBkwd_A	2147483647	854590	0	0
DisabledNoTrigFwd_A	2147483647	1546003554	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14578	0	0
T21	1379	657	0	0
T46	478003	0	0	0
T70	68891	0	0	0
T71	315962	0	0	0
T73	0	313	0	0
T75	410143	0	0	0
T76	36176	0	0	0
T95	231333	0	0	0
T193	3450	351	0	0
T194	2614	391	0	0
T195	995	171	0	0
T196	0	818	0	0
T197	0	802	0	0
T198	0	743	0	0
T199	0	423	0	0
T200	0	858	0	0
T201	0	1199	0	0
T202	0	1609	0	0
T203	0	584	0	0
T204	0	644	0	0
T205	0	719	0	0
T206	0	1998	0	0
T207	0	997	0	0
T208	0	473	0	0
T209	0	374	0	0
T210	0	454	0	0
T211	8265	0	0	0
T212	762188	0	0	0
T213	13408	0	0	0
T214	20785	0	0	0
T215	28696	0	0	0
T216	115592	0	0	0
T217	39302	0	0	0
T218	116727	0	0	0
T219	37435	0	0	0
T220	768679	0	0	0
T221	55356	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	854590	0	0
T1	1334888	3777	0	0
T2	436796	0	0	0
T3	3685244	2237	0	0
T6	0	5	0	0
T7	0	1	0	0
T8	0	1239	0	0
T9	0	65	0	0
T16	216200	0	0	0
T17	2480792	1603	0	0
T18	508728	1	0	0
T19	46612	1	0	0
T20	19104	0	0	0
T21	5516	8	0	0
T22	179800	4	0	0
T24	0	80	0	0
T26	0	230	0	0
T32	0	22	0	0
T37	0	5	0	0
T38	0	38	0	0
T41	0	26	0	0
T42	0	66	0	0
T43	0	96	0	0
T44	0	11	0	0
T45	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1546003554	0	0
T1	1334888	580230	0	0
T2	436796	429093	0	0
T3	3685244	2441758	0	0
T16	216200	171766	0	0
T17	2480792	1883513	0	0
T18	508728	498864	0	0
T19	46612	37220	0	0
T20	19104	16590	0	0
T21	5516	2488	0	0
T22	179800	149669	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T202,T204
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	692539132	4095	0	0
DisabledNoTrigBkwd_A	692539132	238378	0	0
DisabledNoTrigFwd_A	692539132	331158436	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	4095	0	0
T95	231333	0	0	0
T194	2614	391	0	0
T195	995	0	0	0
T202	0	1609	0	0
T204	0	644	0	0
T207	0	997	0	0
T210	0	454	0	0
T215	28696	0	0	0
T216	115592	0	0	0
T217	39302	0	0	0
T218	116727	0	0	0
T219	37435	0	0	0
T220	768679	0	0	0
T221	55356	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	238378	0	0
T1	333722	1866	0	0
T2	109199	0	0	0
T3	921311	20	0	0
T16	54050	0	0	0
T17	620198	84	0	0
T18	127182	1	0	0
T19	11653	1	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	4	0	0
T24	0	80	0	0
T37	0	5	0	0
T41	0	26	0	0
T42	0	66	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	331158436	0	0
T1	333722	130380	0	0
T2	109199	105414	0	0
T3	921311	633722	0	0
T16	54050	9829	0	0
T17	620198	161607	0	0
T18	127182	125507	0	0
T19	11653	2504	0	0
T20	4776	4684	0	0
T21	1379	616	0	0
T22	44950	15020	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T195,T201
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T38

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	692539132	2095	0	0
DisabledNoTrigBkwd_A	692539132	187510	0	0
DisabledNoTrigFwd_A	692539132	410092542	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	2095	0	0
T46	478003	0	0	0
T70	68891	0	0	0
T71	315962	0	0	0
T75	410143	0	0	0
T76	36176	0	0	0
T193	3450	351	0	0
T195	0	171	0	0
T201	0	1199	0	0
T209	0	374	0	0
T211	8265	0	0	0
T212	762188	0	0	0
T213	13408	0	0	0
T214	20785	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	187510	0	0
T1	333722	1184	0	0
T2	109199	0	0	0
T3	921311	620	0	0
T7	0	1	0	0
T8	0	1227	0	0
T9	0	62	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	230	0	0
T32	0	22	0	0
T38	0	36	0	0
T44	0	7	0	0
T45	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	410092542	0	0
T1	333722	136779	0	0
T2	109199	105421	0	0
T3	921311	727955	0	0
T16	54050	53979	0	0
T17	620198	112129	0	0
T18	127182	125507	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	620	0	0
T22	44950	44883	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T198,T199
1	1	Covered	T1,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	692539132	3015	0	0
DisabledNoTrigBkwd_A	692539132	197697	0	0
DisabledNoTrigFwd_A	692539132	400304901	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	3015	0	0
T4	130784	0	0	0
T21	1379	657	0	0
T22	44950	0	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T41	11551	0	0	0
T42	93515	0	0	0
T73	2479	0	0	0
T198	0	743	0	0
T199	0	423	0	0
T205	0	719	0	0
T208	0	473	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	197697	0	0
T1	333722	727	0	0
T2	109199	0	0	0
T3	921311	1597	0	0
T6	0	5	0	0
T8	0	12	0	0
T9	0	3	0	0
T16	54050	0	0	0
T17	620198	1519	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	8	0	0
T22	44950	0	0	0
T38	0	2	0	0
T43	0	96	0	0
T44	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	400304901	0	0
T1	333722	182063	0	0
T2	109199	109129	0	0
T3	921311	485942	0	0
T16	54050	53979	0	0
T17	620198	990275	0	0
T18	127182	122685	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	624	0	0
T22	44950	44883	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T73,T196,T197
1	1	Covered	T1,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T73

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	692539132	5373	0	0
DisabledNoTrigBkwd_A	692539132	231005	0	0
DisabledNoTrigFwd_A	692539132	404447675	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	5373	0	0
T4	130784	0	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T10	753004	0	0	0
T31	87600	0	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T42	93515	0	0	0
T73	2479	313	0	0
T196	0	818	0	0
T197	0	802	0	0
T200	0	858	0	0
T203	0	584	0	0
T206	0	1998	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	231005	0	0
T1	333722	4038	0	0
T2	109199	0	0	0
T3	921311	1545	0	0
T7	0	3	0	0
T8	0	947	0	0
T9	0	1766	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	1743	0	0
T38	0	40	0	0
T39	0	3	0	0
T64	0	60	0	0
T73	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	404447675	0	0
T1	333722	131008	0	0
T2	109199	109129	0	0
T3	921311	594139	0	0
T16	54050	53979	0	0
T17	620198	619502	0	0
T18	127182	125165	0	0
T19	11653	11572	0	0
T20	4776	2538	0	0
T21	1379	628	0	0
T22	44950	44883	0	0