Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T25
1	1	1	Covered	T1,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Covered	T1,T3,T18
1	1	0	Covered	T1,T3,T17
1	1	1	Covered	T1,T3,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T17
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T9,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T27,T28
1	1	Covered	T1,T3,T17

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T17
Phase1St	198	Covered	T1,T3,T17
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T1,T3,T17

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T17
IdleSt->TimeoutSt	159	Covered	T1,T3,T17
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T27,T29,T30
Phase0St->Phase1St	198	Covered	T1,T3,T17
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T3,T18,T7
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T3,T31,T32
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T3,T17,T22
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T17
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T3,T17
TimeoutSt->Phase0St	172	Covered	T1,T3,T17

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T18,T7
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T17,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1157	0	0
CheckAccumTrig0_A	2147483647	2416	0	0
CheckAccumTrig1_A	2147483647	106	0	0
CheckClr_A	2147483647	1157	0	0
CheckEn_A	2147483647	1216080737	0	0
CheckPhase0_A	2147483647	2760	0	0
CheckPhase1_A	2147483647	2706	0	0
CheckPhase2_A	2147483647	2639	0	0
CheckPhase3_A	2147483647	2584	0	0
CheckTimeout0_A	2147483647	3905	0	0
CheckTimeoutSt1_A	2147483647	497021	0	0
CheckTimeoutSt2_A	2147483647	3517	0	0
CheckTimeoutStTrig_A	2147483647	278	0	0
ErrorStAllEscAsserted_A	2147483647	5792	0	0
ErrorStIsTerminal_A	2147483647	4832	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1157	0	0
T4	523136	298	0	0
T5	1362752	0	0	0
T6	466940	0	0	0
T9	613152	0	0	0
T10	3012016	0	0	0
T12	0	318	0	0
T13	0	122	0	0
T31	350400	0	0	0
T35	0	259	0	0
T36	0	160	0	0
T37	28760	0	0	0
T38	118128	0	0	0
T39	56156	0	0	0
T40	104444	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2416	0	0
T1	1334888	26	0	0
T2	436796	0	0	0
T3	3685244	18	0	0
T6	0	1	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	7	0	0
T16	216200	0	0	0
T17	2480792	4	0	0
T18	508728	1	0	0
T19	46612	1	0	0
T20	19104	0	0	0
T21	5516	1	0	0
T22	179800	2	0	0
T24	0	1	0	0
T26	0	2	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106	0	0
T1	333722	2	0	0
T2	109199	0	0	0
T3	921311	0	0	0
T7	112082	0	0	0
T8	247724	0	0	0
T9	153288	1	0	0
T11	1369672	0	0	0
T14	40188	0	0	0
T15	500413	0	0	0
T26	1384194	2	0	0
T29	0	2	0	0
T32	651598	0	0	0
T43	25529	0	0	0
T44	16930	0	0	0
T45	298582	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	110017	0	0	0
T64	256965	0	0	0
T65	221419	0	0	0
T66	885365	0	0	0
T67	310828	0	0	0
T68	1237	0	0	0
T69	49445	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1157	0	0
T1	1334888	15	0	0
T2	436796	0	0	0
T3	3685244	13	0	0
T7	0	1	0	0
T9	0	3	0	0
T15	0	2	0	0
T16	216200	0	0	0
T17	2480792	2	0	0
T18	508728	1	0	0
T19	46612	0	0	0
T20	19104	0	0	0
T21	5516	0	0	0
T22	179800	1	0	0
T26	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1216080737	0	0
T1	1334888	579083	0	0
T2	436796	429089	0	0
T3	3685244	2309654	0	0
T16	216200	171763	0	0
T17	2480792	1883508	0	0
T18	508728	498860	0	0
T19	46612	35297	0	0
T20	19104	16587	0	0
T21	5516	2488	0	0
T22	179800	149666	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2760	0	0
T1	1334888	28	0	0
T2	436796	0	0	0
T3	3685244	23	0	0
T6	0	1	0	0
T7	0	1	0	0
T8	0	2	0	0
T9	0	9	0	0
T16	216200	0	0	0
T17	2480792	6	0	0
T18	508728	1	0	0
T19	46612	1	0	0
T20	19104	0	0	0
T21	5516	1	0	0
T22	179800	2	0	0
T24	0	1	0	0
T26	0	3	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T63	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2706	0	0
T1	1334888	35	0	0
T2	436796	0	0	0
T3	3685244	28	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	14	0	0
T16	216200	0	0	0
T17	2480792	7	0	0
T18	508728	0	0	0
T19	46612	1	0	0
T20	19104	0	0	0
T21	5516	1	0	0
T22	179800	2	0	0
T24	0	1	0	0
T26	0	3	0	0
T32	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T63	0	2	0	0
T73	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2639	0	0
T1	1334888	35	0	0
T2	436796	0	0	0
T3	3685244	27	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	14	0	0
T16	216200	0	0	0
T17	2480792	7	0	0
T18	508728	0	0	0
T19	46612	1	0	0
T20	19104	0	0	0
T21	5516	1	0	0
T22	179800	2	0	0
T24	0	1	0	0
T26	0	3	0	0
T32	0	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T63	0	2	0	0
T73	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2584	0	0
T1	1334888	35	0	0
T2	436796	0	0	0
T3	3685244	25	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	14	0	0
T16	216200	0	0	0
T17	2480792	6	0	0
T18	508728	0	0	0
T19	46612	1	0	0
T20	19104	0	0	0
T21	5516	1	0	0
T22	179800	1	0	0
T24	0	1	0	0
T26	0	3	0	0
T32	0	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T63	0	2	0	0
T73	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3905	0	0
T1	1001166	87	0	0
T2	327597	0	0	0
T3	3685244	87	0	0
T8	0	7	0	0
T9	0	59	0	0
T16	216200	0	0	0
T17	2480792	432	0	0
T18	508728	0	0	0
T19	46612	0	0	0
T20	19104	0	0	0
T21	5516	0	0	0
T22	179800	1	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T26	0	5	0	0
T31	0	2	0	0
T32	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	6	0	0
T43	0	1	0	0
T44	0	3	0	0
T46	0	73	0	0
T63	0	5	0	0
T68	0	1	0	0
T69	0	1	0	0
T74	0	1	0	0
T75	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	497021	0	0
T1	1001166	6447	0	0
T2	327597	0	0	0
T3	3685244	8989	0	0
T8	0	795	0	0
T9	0	3700	0	0
T16	216200	0	0	0
T17	2480792	75948	0	0
T18	508728	0	0	0
T19	46612	0	0	0
T20	19104	0	0	0
T21	5516	0	0	0
T22	179800	41	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T26	0	319	0	0
T31	0	341	0	0
T32	0	38	0	0
T38	0	50	0	0
T39	0	52	0	0
T40	0	412	0	0
T43	0	805	0	0
T44	0	630	0	0
T46	0	4830	0	0
T63	0	1067	0	0
T68	0	120	0	0
T69	0	142	0	0
T74	0	143	0	0
T75	0	1287	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3517	0	0
T1	1001166	83	0	0
T2	327597	0	0	0
T3	3685244	82	0	0
T8	0	6	0	0
T9	0	56	0	0
T16	216200	0	0	0
T17	2480792	429	0	0
T18	508728	0	0	0
T19	46612	0	0	0
T20	19104	0	0	0
T21	5516	0	0	0
T22	179800	1	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T26	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	6	0	0
T44	0	1	0	0
T46	0	614	0	0
T63	0	3	0	0
T68	0	1	0	0
T69	0	6	0	0
T74	0	5	0	0
T75	0	9	0	0
T76	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	278	0	0
T1	333722	2	0	0
T2	109199	0	0	0
T3	2763933	3	0	0
T8	0	1	0	0
T9	0	2	0	0
T16	162150	0	0	0
T17	2480792	3	0	0
T18	508728	0	0	0
T19	46612	0	0	0
T20	19104	0	0	0
T21	5516	0	0	0
T22	179800	0	0	0
T23	164466	0	0	0
T24	77367	0	0	0
T26	0	4	0	0
T27	0	1	0	0
T29	0	4	0	0
T41	11551	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	0	3	0	0
T47	0	4	0	0
T50	0	2	0	0
T51	0	1	0	0
T63	0	2	0	0
T69	0	1	0	0
T73	2479	0	0	0
T75	0	3	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5792	0	0
T4	523136	1422	0	0
T5	1362752	0	0	0
T6	466940	0	0	0
T9	613152	0	0	0
T10	3012016	0	0	0
T12	0	1448	0	0
T13	0	753	0	0
T31	350400	0	0	0
T35	0	1409	0	0
T36	0	760	0	0
T37	28760	0	0	0
T38	118128	0	0	0
T39	56156	0	0	0
T40	104444	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4832	0	0
T4	523136	1182	0	0
T5	1362752	0	0	0
T6	466940	0	0	0
T9	613152	0	0	0
T10	3012016	0	0	0
T12	0	1208	0	0
T13	0	633	0	0
T31	350400	0	0	0
T35	0	1169	0	0
T36	0	640	0	0
T37	28760	0	0	0
T38	118128	0	0	0
T39	56156	0	0	0
T40	104444	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1334888	1334832	0	0
T2	436796	436516	0	0
T3	3685244	3685196	0	0
T16	216200	215916	0	0
T17	2480792	2480680	0	0
T18	508728	508460	0	0
T19	46612	46288	0	0
T20	19104	18736	0	0
T21	5516	5284	0	0
T22	179800	179532	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1334888	1334832	0	0
T2	436796	436516	0	0
T3	3685244	3685196	0	0
T16	216200	215916	0	0
T17	2480792	2480680	0	0
T18	508728	508460	0	0
T19	46612	46288	0	0
T20	19104	18736	0	0
T21	5516	5284	0	0
T22	179800	179532	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T38

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T17
1	0	1	Covered	T1,T3,T18
1	1	0	Covered	T1,T3,T17
1	1	1	Covered	T1,T3,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T17
0	1	Covered	T3,T63,T26
1	0	Covered	T9,T48,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T9,T48,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Not Covered
1	1	Covered	T3,T63,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T38
1	Covered	T3,T9,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T38
1	Covered	T3,T9,T26

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T3,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T38
1	Covered	T1,T3,T9

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T38

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T38

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T38
Phase1St	198	Covered	T1,T3,T38
Phase2St	215	Covered	T1,T3,T38
Phase3St	233	Covered	T1,T3,T38
TerminalSt	249	Covered	T1,T3,T38
TimeoutSt	159	Covered	T1,T3,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T38
IdleSt->TimeoutSt	159	Covered	T1,T3,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T81,T82
Phase0St->Phase1St	198	Covered	T1,T3,T38
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T72,T83
Phase1St->Phase2St	215	Covered	T1,T3,T38
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T84,T62
Phase2St->Phase3St	233	Covered	T1,T3,T38
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T3,T85,T86
Phase3St->TerminalSt	249	Covered	T1,T3,T38
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T9
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T17
TimeoutSt->Phase0St	172	Covered	T3,T9,T63

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T38
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T9,T63
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T81,T82
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T38
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T38
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T72,T83
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T38
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T38
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T84,T62
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T38
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T85,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T38
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	692539132	243	0	0
CheckAccumTrig0_A	692539132	497	0	0
CheckAccumTrig1_A	692539132	23	0	0
CheckClr_A	692539132	227	0	0
CheckEn_A	692260011	319815116	0	0
CheckPhase0_A	692539132	578	0	0
CheckPhase1_A	692539132	567	0	0
CheckPhase2_A	692539132	556	0	0
CheckPhase3_A	692539132	543	0	0
CheckTimeout0_A	692539132	1231	0	0
CheckTimeoutSt1_A	692539132	167939	0	0
CheckTimeoutSt2_A	692539132	1145	0	0
CheckTimeoutStTrig_A	692539132	62	0	0
ErrorStAllEscAsserted_A	692539132	1425	0	0
ErrorStIsTerminal_A	692539132	1185	0	0
EscStateOut_A	692258276	692185008	0	0
u_state_regs_A	692539132	692363529	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	243	0	0
T4	130784	55	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	58	0	0
T13	0	32	0	0
T31	87600	0	0	0
T35	0	55	0	0
T36	0	43	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	497	0	0
T1	333722	6	0	0
T2	109199	0	0	0
T3	921311	9	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	6	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	2	0	0
T32	0	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	23	0	0
T7	112082	0	0	0
T8	247724	0	0	0
T9	153288	1	0	0
T11	684836	0	0	0
T14	40188	0	0	0
T26	692097	0	0	0
T43	25529	0	0	0
T44	16930	0	0	0
T48	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	110017	0	0	0
T64	256965	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	227	0	0
T1	333722	2	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T7	0	1	0	0
T9	0	3	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	2	0	0
T32	0	1	0	0
T46	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692260011	319815116	0	0
T1	333722	136613	0	0
T2	109199	105420	0	0
T3	921311	684531	0	0
T16	54050	53978	0	0
T17	620198	112129	0	0
T18	127182	125506	0	0
T19	11653	11571	0	0
T20	4776	4683	0	0
T21	1379	620	0	0
T22	44950	44882	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	578	0	0
T1	333722	6	0	0
T2	109199	0	0	0
T3	921311	10	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	7	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	3	0	0
T32	0	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T63	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	567	0	0
T1	333722	6	0	0
T2	109199	0	0	0
T3	921311	9	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	7	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	3	0	0
T32	0	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T63	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	556	0	0
T1	333722	6	0	0
T2	109199	0	0	0
T3	921311	9	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	7	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	3	0	0
T32	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T63	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	543	0	0
T1	333722	6	0	0
T2	109199	0	0	0
T3	921311	8	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	7	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	3	0	0
T32	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T63	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1231	0	0
T1	333722	1	0	0
T2	109199	0	0	0
T3	921311	5	0	0
T8	0	1	0	0
T9	0	4	0	0
T16	54050	0	0	0
T17	620198	425	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	2	0	0
T46	0	73	0	0
T63	0	2	0	0
T74	0	1	0	0
T75	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	167939	0	0
T1	333722	190	0	0
T2	109199	0	0	0
T3	921311	517	0	0
T8	0	19	0	0
T9	0	300	0	0
T16	54050	0	0	0
T17	620198	74806	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	194	0	0
T46	0	4830	0	0
T63	0	317	0	0
T74	0	143	0	0
T75	0	1287	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1145	0	0
T1	333722	1	0	0
T2	109199	0	0	0
T3	921311	4	0	0
T8	0	1	0	0
T9	0	3	0	0
T16	54050	0	0	0
T17	620198	425	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	1	0	0
T46	0	71	0	0
T63	0	1	0	0
T74	0	1	0	0
T75	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	62	0	0
T3	921311	1	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T26	0	1	0	0
T29	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T63	0	1	0	0
T75	0	2	0	0
T77	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1425	0	0
T4	130784	339	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	359	0	0
T13	0	198	0	0
T31	87600	0	0	0
T35	0	328	0	0
T36	0	201	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1185	0	0
T4	130784	279	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	299	0	0
T13	0	168	0	0
T31	87600	0	0	0
T35	0	268	0	0
T36	0	171	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692258276	692185008	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	692363529	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T73

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T17
1	0	1	Covered	T1,T3,T18
1	1	0	Covered	T1,T3,T17
1	1	1	Covered	T1,T3,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T17
0	1	Covered	T1,T17,T63
1	0	Covered	T26,T87,T77

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T87,T77

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Not Covered
1	1	Covered	T1,T17,T63

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T73

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T73
1	Covered	T1,T3,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T9,T26,T67

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T17
Phase1St	198	Covered	T1,T3,T17
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T1,T3,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T73
IdleSt->TimeoutSt	159	Covered	T1,T3,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T85,T55,T88
Phase0St->Phase1St	198	Covered	T1,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T56,T89,T90
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T91,T92,T93
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T77,T49,T92
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T40
TimeoutSt->Phase0St	172	Covered	T1,T17,T63

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T73
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T63
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T40
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T55,T88,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T56,T89,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T91,T92,T93
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T77,T49,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	692539132	272	0	0
CheckAccumTrig0_A	692539132	503	0	0
CheckAccumTrig1_A	692539132	25	0	0
CheckClr_A	692539132	228	0	0
CheckEn_A	692260011	327353158	0	0
CheckPhase0_A	692539132	595	0	0
CheckPhase1_A	692539132	586	0	0
CheckPhase2_A	692539132	572	0	0
CheckPhase3_A	692539132	564	0	0
CheckTimeout0_A	692539132	1110	0	0
CheckTimeoutSt1_A	692539132	112024	0	0
CheckTimeoutSt2_A	692539132	1010	0	0
CheckTimeoutStTrig_A	692539132	74	0	0
ErrorStAllEscAsserted_A	692539132	1420	0	0
ErrorStIsTerminal_A	692539132	1180	0	0
EscStateOut_A	692258276	692185008	0	0
u_state_regs_A	692539132	692363529	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	272	0	0
T4	130784	82	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	61	0	0
T13	0	22	0	0
T31	87600	0	0	0
T35	0	63	0	0
T36	0	44	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	503	0	0
T1	333722	5	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T7	0	1	0	0
T9	0	5	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	3	0	0
T38	0	1	0	0
T39	0	1	0	0
T64	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	25	0	0
T11	684836	0	0	0
T15	500413	0	0	0
T26	692097	1	0	0
T32	651598	0	0	0
T45	298582	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T65	221419	0	0	0
T66	885365	0	0	0
T67	310828	0	0	0
T68	1237	0	0	0
T69	49445	0	0	0
T77	0	1	0	0
T87	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	228	0	0
T1	333722	2	0	0
T2	109199	0	0	0
T3	921311	1	0	0
T9	0	1	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	1	0	0
T47	0	3	0	0
T71	0	1	0	0
T77	0	1	0	0
T100	0	2	0	0
T101	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692260011	327353158	0	0
T1	333722	130228	0	0
T2	109199	109128	0	0
T3	921311	579718	0	0
T16	54050	53978	0	0
T17	620198	619501	0	0
T18	127182	125164	0	0
T19	11653	11571	0	0
T20	4776	2538	0	0
T21	1379	628	0	0
T22	44950	44882	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	595	0	0
T1	333722	7	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	5	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T63	0	1	0	0
T73	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	586	0	0
T1	333722	7	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	5	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T63	0	1	0	0
T73	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	572	0	0
T1	333722	7	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	5	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T63	0	1	0	0
T73	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	564	0	0
T1	333722	7	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T7	0	1	0	0
T8	0	1	0	0
T9	0	5	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T63	0	1	0	0
T73	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1110	0	0
T1	333722	6	0	0
T2	109199	0	0	0
T3	921311	15	0	0
T8	0	1	0	0
T9	0	53	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	1	0	0
T40	0	5	0	0
T63	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	112024	0	0
T1	333722	685	0	0
T2	109199	0	0	0
T3	921311	2295	0	0
T8	0	110	0	0
T9	0	3247	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	5	0	0
T40	0	360	0	0
T63	0	517	0	0
T68	0	120	0	0
T69	0	142	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1010	0	0
T1	333722	4	0	0
T2	109199	0	0	0
T3	921311	15	0	0
T9	0	53	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T40	0	5	0	0
T46	0	485	0	0
T63	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T74	0	1	0	0
T75	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	74	0	0
T1	333722	2	0	0
T2	109199	0	0	0
T3	921311	0	0	0
T8	0	1	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T63	0	1	0	0
T74	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0
T102	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1420	0	0
T4	130784	356	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	334	0	0
T13	0	173	0	0
T31	87600	0	0	0
T35	0	364	0	0
T36	0	193	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1180	0	0
T4	130784	296	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	274	0	0
T13	0	143	0	0
T31	87600	0	0	0
T35	0	304	0	0
T36	0	163	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692258276	692185008	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	692363529	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T25
1	1	1	Covered	T1,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T16
1	0	1	Covered	T1,T3,T23
1	1	0	Covered	T1,T3,T20
1	1	1	Covered	T3,T17,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T17,T22
0	1	Covered	T3,T17,T9
1	0	Covered	T26,T46,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T17,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T46,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T22
1	0	Not Covered
1	1	Covered	T3,T17,T9

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T3,T22,T37

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T17,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T17
Phase1St	198	Covered	T1,T3,T17
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T3,T17,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T17
IdleSt->TimeoutSt	159	Covered	T3,T17,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T85,T34
Phase0St->Phase1St	198	Covered	T1,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T7,T8
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T27,T29
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T3,T17,T22
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T17,T22
TimeoutSt->Phase0St	172	Covered	T3,T17,T9

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T9
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T103,T61
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T7,T8
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T27,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T17,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	692539132	313	0	0
CheckAccumTrig0_A	692539132	887	0	0
CheckAccumTrig1_A	692539132	36	0	0
CheckClr_A	692539132	442	0	0
CheckEn_A	692260011	239712905	0	0
CheckPhase0_A	692539132	993	0	0
CheckPhase1_A	692539132	965	0	0
CheckPhase2_A	692539132	943	0	0
CheckPhase3_A	692539132	920	0	0
CheckTimeout0_A	692539132	717	0	0
CheckTimeoutSt1_A	692539132	86570	0	0
CheckTimeoutSt2_A	692539132	594	0	0
CheckTimeoutStTrig_A	692539132	87	0	0
ErrorStAllEscAsserted_A	692539132	1509	0	0
ErrorStIsTerminal_A	692539132	1269	0	0
EscStateOut_A	692258276	692185008	0	0
u_state_regs_A	692539132	692363529	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	313	0	0
T4	130784	76	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	89	0	0
T13	0	38	0	0
T31	87600	0	0	0
T35	0	73	0	0
T36	0	37	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	887	0	0
T1	333722	13	0	0
T2	109199	0	0	0
T3	921311	4	0	0
T16	54050	0	0	0
T17	620198	3	0	0
T18	127182	1	0	0
T19	11653	1	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	2	0	0
T24	0	1	0	0
T37	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	36	0	0
T11	684836	0	0	0
T15	500413	0	0	0
T26	692097	2	0	0
T29	0	1	0	0
T32	651598	0	0	0
T45	298582	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T65	221419	0	0	0
T66	885365	0	0	0
T67	310828	0	0	0
T68	1237	0	0	0
T69	49445	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	442	0	0
T1	333722	8	0	0
T2	109199	0	0	0
T3	921311	3	0	0
T16	54050	0	0	0
T17	620198	2	0	0
T18	127182	1	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	1	0	0
T31	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692260011	239712905	0	0
T1	333722	130217	0	0
T2	109199	105413	0	0
T3	921311	559463	0	0
T16	54050	9829	0	0
T17	620198	161605	0	0
T18	127182	125506	0	0
T19	11653	584	0	0
T20	4776	4683	0	0
T21	1379	616	0	0
T22	44950	15020	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	993	0	0
T1	333722	13	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T16	54050	0	0	0
T17	620198	4	0	0
T18	127182	1	0	0
T19	11653	1	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	2	0	0
T24	0	1	0	0
T37	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	965	0	0
T1	333722	13	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T16	54050	0	0	0
T17	620198	4	0	0
T18	127182	0	0	0
T19	11653	1	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	2	0	0
T24	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	943	0	0
T1	333722	13	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T16	54050	0	0	0
T17	620198	4	0	0
T18	127182	0	0	0
T19	11653	1	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	2	0	0
T24	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	920	0	0
T1	333722	13	0	0
T2	109199	0	0	0
T3	921311	5	0	0
T16	54050	0	0	0
T17	620198	3	0	0
T18	127182	0	0	0
T19	11653	1	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	1	0	0
T24	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	717	0	0
T3	921311	55	0	0
T8	0	4	0	0
T9	0	1	0	0
T16	54050	0	0	0
T17	620198	4	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	1	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T63	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	86570	0	0
T3	921311	5415	0	0
T8	0	507	0	0
T9	0	38	0	0
T16	54050	0	0	0
T17	620198	804	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	41	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T31	0	341	0	0
T39	0	52	0	0
T43	0	805	0	0
T44	0	419	0	0
T63	0	233	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	594	0	0
T3	921311	53	0	0
T8	0	4	0	0
T16	54050	0	0	0
T17	620198	3	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	1	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T46	0	38	0	0
T63	0	1	0	0
T69	0	5	0	0
T74	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	87	0	0
T3	921311	2	0	0
T9	0	1	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T29	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T77	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1509	0	0
T4	130784	373	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	387	0	0
T13	0	210	0	0
T31	87600	0	0	0
T35	0	362	0	0
T36	0	177	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1269	0	0
T4	130784	313	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	327	0	0
T13	0	180	0	0
T31	87600	0	0	0
T35	0	302	0	0
T36	0	147	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692258276	692185008	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	692363529	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T17
1	0	1	Covered	T1,T3,T18
1	1	0	Covered	T1,T3,T38
1	1	1	Covered	T1,T3,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T17
0	1	Covered	T17,T9,T44
1	0	Covered	T1,T3,T32

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T32

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T27,T28
1	1	Covered	T17,T9,T44

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T17,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T3,T9

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T17
Phase1St	198	Covered	T1,T3,T17
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T1,T3,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T17
IdleSt->TimeoutSt	159	Covered	T1,T3,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T33,T104
Phase0St->Phase1St	198	Covered	T1,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T105,T34,T106
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T77,T34
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T30,T105,T86
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T17
TimeoutSt->Phase0St	172	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T33,T104
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T105,T34,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T77,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T105,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	692539132	329	0	0
CheckAccumTrig0_A	692539132	529	0	0
CheckAccumTrig1_A	692539132	22	0	0
CheckClr_A	692539132	260	0	0
CheckEn_A	692260011	329199558	0	0
CheckPhase0_A	692539132	594	0	0
CheckPhase1_A	692539132	588	0	0
CheckPhase2_A	692539132	568	0	0
CheckPhase3_A	692539132	557	0	0
CheckTimeout0_A	692539132	847	0	0
CheckTimeoutSt1_A	692539132	130488	0	0
CheckTimeoutSt2_A	692539132	768	0	0
CheckTimeoutStTrig_A	692539132	55	0	0
ErrorStAllEscAsserted_A	692539132	1438	0	0
ErrorStIsTerminal_A	692539132	1198	0	0
EscStateOut_A	692258276	692185008	0	0
u_state_regs_A	692539132	692363529	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	329	0	0
T4	130784	85	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	110	0	0
T13	0	30	0	0
T31	87600	0	0	0
T35	0	68	0	0
T36	0	36	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	529	0	0
T1	333722	7	0	0
T2	109199	0	0	0
T3	921311	5	0	0
T6	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	1	0	0
T22	44950	0	0	0
T38	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	22	0	0
T1	333722	2	0	0
T2	109199	0	0	0
T3	921311	2	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T86	0	1	0	0
T107	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	260	0	0
T1	333722	5	0	0
T2	109199	0	0	0
T3	921311	4	0	0
T15	0	2	0	0
T16	54050	0	0	0
T17	620198	0	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	2	0	0
T27	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T70	0	1	0	0
T87	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692260011	329199558	0	0
T1	333722	182025	0	0
T2	109199	109128	0	0
T3	921311	485942	0	0
T16	54050	53978	0	0
T17	620198	990273	0	0
T18	127182	122684	0	0
T19	11653	11571	0	0
T20	4776	4683	0	0
T21	1379	624	0	0
T22	44950	44882	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	594	0	0
T1	333722	9	0	0
T2	109199	0	0	0
T3	921311	7	0	0
T6	0	1	0	0
T8	0	1	0	0
T9	0	2	0	0
T16	54050	0	0	0
T17	620198	2	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	1	0	0
T22	44950	0	0	0
T38	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	588	0	0
T1	333722	9	0	0
T2	109199	0	0	0
T3	921311	7	0	0
T6	0	1	0	0
T8	0	1	0	0
T9	0	2	0	0
T16	54050	0	0	0
T17	620198	2	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	1	0	0
T22	44950	0	0	0
T38	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	568	0	0
T1	333722	9	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T6	0	1	0	0
T8	0	1	0	0
T9	0	2	0	0
T16	54050	0	0	0
T17	620198	2	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	1	0	0
T22	44950	0	0	0
T38	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	557	0	0
T1	333722	9	0	0
T2	109199	0	0	0
T3	921311	6	0	0
T6	0	1	0	0
T8	0	1	0	0
T9	0	2	0	0
T16	54050	0	0	0
T17	620198	2	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	1	0	0
T22	44950	0	0	0
T38	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	847	0	0
T1	333722	80	0	0
T2	109199	0	0	0
T3	921311	12	0	0
T8	0	1	0	0
T9	0	1	0	0
T16	54050	0	0	0
T17	620198	2	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	2	0	0
T32	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	130488	0	0
T1	333722	5572	0	0
T2	109199	0	0	0
T3	921311	762	0	0
T8	0	159	0	0
T9	0	115	0	0
T16	54050	0	0	0
T17	620198	337	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T26	0	120	0	0
T32	0	38	0	0
T38	0	50	0	0
T40	0	52	0	0
T44	0	211	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	768	0	0
T1	333722	78	0	0
T2	109199	0	0	0
T3	921311	10	0	0
T8	0	1	0	0
T16	54050	0	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T32	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T46	0	20	0	0
T76	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	55	0	0
T9	0	1	0	0
T17	620198	1	0	0
T18	127182	0	0	0
T19	11653	0	0	0
T20	4776	0	0	0
T21	1379	0	0	0
T22	44950	0	0	0
T23	54822	0	0	0
T24	25789	0	0	0
T26	0	2	0	0
T41	11551	0	0	0
T44	0	1	0	0
T50	0	1	0	0
T69	0	1	0	0
T73	2479	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1438	0	0
T4	130784	354	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	368	0	0
T13	0	172	0	0
T31	87600	0	0	0
T35	0	355	0	0
T36	0	189	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	1198	0	0
T4	130784	294	0	0
T5	340688	0	0	0
T6	116735	0	0	0
T9	153288	0	0	0
T10	753004	0	0	0
T12	0	308	0	0
T13	0	142	0	0
T31	87600	0	0	0
T35	0	295	0	0
T36	0	159	0	0
T37	7190	0	0	0
T38	29532	0	0	0
T39	14039	0	0	0
T40	26111	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692258276	692185008	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692539132	692363529	0	0
T1	333722	333708	0	0
T2	109199	109129	0	0
T3	921311	921299	0	0
T16	54050	53979	0	0
T17	620198	620170	0	0
T18	127182	127115	0	0
T19	11653	11572	0	0
T20	4776	4684	0	0
T21	1379	1321	0	0
T22	44950	44883	0	0