Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	84249	1			T1	134		T8	1280		T20	1
class_i[0x1]	74865	1			T8	816		T23	402		T24	5
class_i[0x2]	67867	1			T4	29		T20	2144		T9	3
class_i[0x3]	70820	1			T5	11		T8	6522		T20	454

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	79596	1			T1	36		T4	5		T5	2
alert[0x1]	75654	1			T1	49		T4	4		T5	4
alert[0x2]	72366	1			T1	41		T4	12		T5	3
alert[0x3]	70185	1			T1	8		T4	8		T5	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

297531

1

T1

134

T4

20

T8

8618

esc_ping_fail

270

1

T4

9

T5

11

T9

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	79522	1			T1	36		T4	3		T8	2055
esc_integrity_fail	alert[0x1]	75578	1			T1	49		T4	3		T8	2229
esc_integrity_fail	alert[0x2]	72301	1			T1	41		T4	8		T8	2105
esc_integrity_fail	alert[0x3]	70130	1			T1	8		T4	6		T8	2229
esc_ping_fail	alert[0x0]	74	1			T4	2		T5	2		T9	1
esc_ping_fail	alert[0x1]	76	1			T4	1		T5	4		T9	1
esc_ping_fail	alert[0x2]	65	1			T4	4		T5	3		T9	1
esc_ping_fail	alert[0x3]	55	1			T4	2		T5	2		T232	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	84164	1			T1	134		T8	1280		T20	1
esc_integrity_fail	class_i[0x1]	74805	1			T8	816		T23	402		T24	5
esc_integrity_fail	class_i[0x2]	67811	1			T4	20		T20	2144		T46	133
esc_integrity_fail	class_i[0x3]	70751	1			T8	6522		T20	454		T9	5
esc_ping_fail	class_i[0x0]	85	1			T232	2		T117	6		T73	1
esc_ping_fail	class_i[0x1]	60	1			T197	6		T304	4		T298	7
esc_ping_fail	class_i[0x2]	56	1			T4	9		T9	3		T197	1
esc_ping_fail	class_i[0x3]	69	1			T5	11		T232	1		T73	4